Clock phase control circuit, clock phase control method, power amplification device and audio equipment
阅读说明：本技术 时钟相位控制电路、方法、功率放大装置及音频设备 (Clock phase control circuit, clock phase control method, power amplification device and audio equipment ) 是由 刘�东 姚炜 于 2020-04-09 设计创作，主要内容包括：本申请涉及集成电路时钟控制技术领域,涉及一种时钟相位控制电路、方法、功率放大装置及音频设备,所述电路包括：接口模块,用于基于接收的第一时钟信号和时钟相位参数设置信号生成时钟使能信号和时钟相位控制信号；时钟产生模块用于基于接收的第二时钟信号和所述时钟使能信号生成系统时钟信号；相位控制模块用于基于接收的所述时钟相位控制信号生成相位延迟控制信号；时钟分频触发模块,用于基于接收的所述第二时钟信号和所述相位延迟控制信号生成时钟分频触发信号；时钟分频器,用于基于接收的所述系统时钟信号、所述相位延迟控制信号及所述时钟分频触发信号生成工作时钟信号,实现对后一级电路时钟相位的精准控制。(The application relates to the technical field of integrated circuit clock control, and relates to a clock phase control circuit, a clock phase control method, a power amplification device and audio equipment, wherein the circuit comprises: an interface module for generating a clock enable signal and a clock phase control signal based on the received first clock signal and the clock phase parameter setting signal; the clock generation module is used for generating a system clock signal based on the received second clock signal and the clock enable signal; the phase control module is used for generating a phase delay control signal based on the received clock phase control signal; a clock division trigger module for generating a clock division trigger signal based on the received second clock signal and the phase delay control signal; and the clock frequency divider is used for generating a working clock signal based on the received system clock signal, the phase delay control signal and the clock frequency division trigger signal so as to realize accurate control on the clock phase of the next-stage circuit.)
1. A clock phase control circuit, comprising:
the interface module is used for receiving a first clock signal and a clock phase parameter setting signal and generating a clock enable signal and a clock phase control signal according to the first clock signal and the clock phase parameter setting signal;
the clock generation module is connected with the interface module and used for receiving a second clock signal and the clock enable signal and generating a system clock signal according to the second clock signal and the clock enable signal;
the phase control module is connected with the interface module and used for receiving the clock phase control signal and generating a phase delay control signal according to the clock phase control signal;
the clock frequency division triggering module is used for receiving the second clock signal and the phase delay control signal and generating a clock frequency division triggering signal according to the second clock signal and the phase delay control signal;
and the clock frequency divider is respectively connected with the clock generation module, the phase control module and the clock frequency division triggering module, and is used for receiving the system clock signal, the phase delay control signal and the clock frequency division triggering signal and generating a working clock signal according to the system clock signal, the phase delay control signal and the clock frequency division triggering signal, wherein the working clock signal is used for controlling the phase delay of a next-stage circuit.
2. The clock phase control circuit of claim 1, wherein:
the interface module is also used for generating different clock phase control signals based on the received different clock phase parameter setting signals;
the phase control module is further used for generating different clock frequency division trigger signals based on the received different clock phase control signals so as to control the clock frequency divider to generate working clock signals with different frequencies.
3. The clock phase control circuit of claim 2, wherein the clock divide-by-trigger module comprises:
the counter unit is used for receiving the second clock signal and generating a counting period value signal according to the second clock signal;
and the time sequence control unit is respectively connected with the counter unit and the phase control module, and is used for receiving the counting period value signal and the phase delay control signal and generating the clock frequency division trigger signal according to the counting period value signal and the phase delay control signal.
4. The clock phase control circuit of claim 3, wherein the counter unit is configured to:
acquiring integral multiples of the minimum period value of the working clock signal as the counting period value of the counter unit;
when the count value of the counter unit reaches the count period value, the counter unit generates the count period value signal.
5. The clock phase control circuit of claim 1, wherein the clock divide-by-trigger module comprises:
and the frame clock frequency divider is used for receiving the second clock signal and the phase delay control signal and generating the clock frequency division trigger signal according to the second clock signal and the phase delay control signal.
6. The clock phase control circuit of claim 5, wherein the frame clock divider is configured to:
acquiring 2 of the second clock signalNThe frequency division signal is used as the clock frequency division trigger signal, and N is a positive integer;
wherein, noting the frequency of the second clock signal as fs, noting the frequency value of the working clock signal as f, noting the period value of the clock frequency division trigger signal as M times of the period value of the working clock signal, where M is a positive integer, then N is calculated according to the following formula:
7. the clock phase control circuit of any of claims 1-6, further comprising:
the reset unit is connected with the clock frequency division triggering module and used for providing a reset signal for the clock frequency division triggering module so as to reset the counter unit; and/or
And the abnormal reset module is connected with the clock frequency divider and used for providing an abnormal reset signal for the clock frequency divider so as to reset the clock frequency divider.
8. The clock phase control circuit of any of claims 1-6, wherein:
the first clock signal is a clock signal of an I2C bus;
the second clock signal is the clock signal of the I2S bus.
9. A power amplification device, comprising:
a boost converter circuit; and
the clock phase control circuit of any of claims 1-8, the operating clock signal output by the clock phase control circuit to control a phase delay of the boost conversion circuit.
10. An audio device, comprising:
the power amplification circuits comprise boost conversion circuits;
a plurality of clock phase control circuits according to any one of claims 1 to 8, the number of the clock phase control circuits being the same as the number of the power amplification circuits, the clock phase control circuits being connected to the boost converter circuits of the power amplification circuits in a one-to-one manner for controlling the boost converter circuits of the power amplification circuits, respectively;
the working clock signals output by the clock phase control circuits respectively control the boost conversion circuits to generate preset phase delay.
11. The audio device of claim 10, wherein each of the clock phase control circuits is configured to output a different operating clock signal to respectively control each of the boost converter circuits to generate a different phase delay.
12. A clock phase control method is applied to a clock phase control circuit, the clock phase control circuit comprises an interface module, a clock generation module, a phase control module, a clock frequency division trigger module and a clock frequency divider, and the method is characterized by comprising the following steps:
controlling the interface module to generate a clock enable signal and a clock phase control signal based on the received first clock signal and the clock phase parameter setting signal;
controlling the clock generation module to generate a system clock signal according to a second clock signal and the clock enable signal;
controlling the phase control module to generate a phase delay control signal according to the clock phase control signal;
and controlling the clock frequency division triggering module to generate a clock frequency division triggering signal according to the second clock signal and the phase delay control signal, so that the clock frequency divider generates a working clock signal according to the system clock signal, the clock frequency division triggering signal and the phase delay control signal, and the working clock signal is used for controlling the phase delay of a next-stage circuit.
13. A clock phase control method applied to an audio device including a plurality of power amplification circuits having boost conversion circuits, and a plurality of clock phase control circuits according to any one of claims 1 to 8, the number of the clock phase control circuits being the same as the number of the power amplification circuits, the clock phase control circuits being connected to the boost conversion circuits of the power amplification circuits in a one-to-one manner, the method comprising:
generating working clock signals respectively by utilizing the clock phase control circuits according to the received first clock signals and the clock phase parameter setting signals;
and respectively controlling each boosting conversion circuit to generate preset phase delay by using each working clock signal.
14. The clock phase control method of claim 13, wherein the controlling the boost converter circuits to generate the predetermined phase delay by using the operating clock signals respectively comprises:
and respectively controlling the boosting conversion circuits to generate different phase delays by using the working clock signals.
Technical Field
The present disclosure relates to the field of integrated circuit clock control technologies, and in particular, to a clock phase control circuit, a clock phase control method, a power amplifier, and an audio device.
Background
With the development of multimedia intelligent devices and the improvement of the intelligent level of people's life, a plurality of audio power amplifiers are generally adopted in an audio system to realize a stereo effect, and are controlled by the same Integrated Circuit (I2C) bus and are started one by one, namely, the start of each audio power amplifier is in sequence; in addition, the working clock of the BOOST converter circuit in different audio amplifiers and the frequency of the frame clock WS in the audio bus (I2S) of the integrated circuit are generally not in integral multiple relationship.
However, in the conventional stereo device, the BOOST converter circuits in the audio power amplifiers may draw a large current when switching, and particularly, when the BOOST converter circuits in the audio power amplifiers are switched in the same direction, the BOOST converter circuits in the audio power amplifiers draw a large current at the same time, which may cause an excessive peak current of a battery in the stereo device, and easily causes an automatic shutdown of the stereo device when the battery power is low.
Disclosure of Invention
In view of the above, it is necessary to provide a clock phase control circuit, a method, a power amplification device, and an audio device capable of controlling a clock phase delay of a circuit in a subsequent stage in order to solve the above-mentioned problems in the background art.
A first aspect of the present application provides a clock phase control circuit, comprising:
the interface module is used for receiving a first clock signal and a clock phase parameter setting signal and generating a clock enable signal and a clock phase control signal according to the first clock signal and the clock phase parameter setting signal;
the clock generation module is connected with the interface module and used for receiving a second clock signal and the clock enable signal and generating a system clock signal according to the second clock signal and the clock enable signal;
the phase control module is connected with the interface module and used for receiving the clock phase control signal and generating a phase delay control signal according to the clock phase control signal;
the clock frequency division triggering module is used for receiving the second clock signal and the phase delay control signal and generating a clock frequency division triggering signal according to the second clock signal and the phase delay control signal;
and the clock frequency divider is respectively connected with the clock generation module, the phase control module and the clock frequency division triggering module, and is used for receiving the system clock signal, the phase delay control signal and the clock frequency division triggering signal and generating a working clock signal according to the system clock signal, the phase delay control signal and the clock frequency division triggering signal, wherein the working clock signal is used for controlling the phase delay of a next-stage circuit.
In the clock phase control circuit in the above embodiment, the interface module may receive a first clock signal and a clock phase parameter setting signal, and generate a clock enable signal and a clock phase control signal according to the first clock signal and the clock phase parameter setting signal; generating a system clock signal based on the received second clock signal and the clock enable signal by using a clock generation module; setting a phase control module to generate a phase delay control signal according to the received clock phase control signal; setting a clock frequency division trigger module to receive the second clock signal and the phase delay control signal and generate a clock frequency division trigger signal according to the second clock signal and the phase delay control signal; the clock frequency divider can generate a working clock signal based on the received system clock signal, the phase delay control signal and the clock frequency division trigger signal, and the working clock signal is used for controlling a next-stage circuit to generate a preset phase delay so as to realize accurate control of the working clock phase of the next-stage circuit.
In one embodiment, the interface module is configured to: generating different clock phase control signals based on the received different clock phase parameter setting signals; the phase control module is configured to: and generating different clock frequency division trigger signals based on the received different clock phase control signals to control the clock frequency divider to generate working clock signals with different frequencies.
In the clock phase control circuit in the above embodiment, different clock phase parameter setting signals are input to the interface module, so that the interface module generates different clock phase control signals, and further the phase control module generates different clock frequency division trigger signals based on the received different clock phase control signals to control the clock frequency divider to generate working clock signals with different frequencies. The frequency of the working clock signal output by the clock phase control circuit is changed according to different configuration parameters, and the phase delay of the next-stage circuit can be controlled while different frequency requirements of different application scenes are met.
In one embodiment, the clock division triggering module includes:
the counter unit is used for receiving the second clock signal and generating a counting period value signal according to the second clock signal;
and the time sequence control unit is respectively connected with the counter unit and the phase control module, and is used for receiving the counting period value signal and the phase delay control signal and generating the clock frequency division trigger signal according to the counting period value signal and the phase delay control signal.
In the clock phase control circuit in the above embodiment, since the clock generation module generates the system clock signal based on the received second clock signal and the clock enable signal, the working clock signal generated by the clock divider is generated based on the system clock signal, the counter unit is configured to generate the count period value signal based on the received second clock signal, the count period value of the counter unit can be set, so that when the counter unit reaches the preset count period value based on the count value obtained by the received second clock signal, the counter unit can provide the count period value signal to the timing control unit, so that the timing control unit generates the clock division trigger signal to trigger the clock divider to generate the working clock signal, and the working clock signal is used to control the next stage circuit to generate the preset phase delay, and the accurate control of the working clock phase of the next-stage circuit is realized.
In one embodiment, the counter unit is configured to:
acquiring integral multiples of the minimum period value of the working clock signal as the counting period value of the counter unit;
when the count value of the counter unit reaches the count period value, the counter unit generates the count period value signal.
In the clock phase control circuit in the above embodiment, the counter unit may be configured to obtain a number of frames in the received second clock signal, and output a count period value signal when the number reaches a preset value, so that the timing control unit generates the clock frequency division trigger signal based on the count period value signal and the phase delay control signal. The clock frequency division trigger signal may be a periodic pulse signal, and a period value of the clock frequency division trigger signal is an integer multiple of a period value of the working clock signal, so that the clock frequency division trigger signal may trigger the clock frequency divider to generate the working clock signal, and the working clock signal is used to control a next stage circuit to generate a preset phase delay, thereby implementing accurate control of a phase of the working clock of the next stage circuit.
In one embodiment, the clock division triggering module includes a frame clock divider configured to receive the second clock signal and the phase delay control signal and generate the clock division triggering signal according to the second clock signal and the phase delay control signal. The frame clock frequency divider may be configured to divide the frequency of the received second clock signal to obtain a periodic clock frequency division trigger signal, and the period value of the clock frequency division trigger signal may be set so that the clock frequency divider may identify a rising edge or a falling edge of the clock frequency division trigger signal to generate the working clock signal, and the working clock signal is used to control the next stage of circuit to generate a preset phase delay, thereby implementing accurate control of the working clock phase of the next stage of circuit.
In one embodiment, the frame clock divider is configured to:
acquiring 2 of the second clock signalNThe frequency division signal is used as the clock frequency division trigger signal, and N is a positive integer;
wherein, noting the frequency of the second clock signal as fs, noting the frequency value of the working clock signal as f, noting the period value of the clock frequency division trigger signal as M times of the period value of the working clock signal, where M is a positive integer, then N is calculated according to the following formula:
in the clock phase control circuit in the above embodiment, when the frequency value of the working clock signal is recorded as f, the frame clock frequency divider is configured to obtain 2 of the received second clock signalNThe frequency division signal is used as the clock frequency division trigger signal, N is a positive integer, the period value of the clock frequency division trigger signal is set to be M times of the period value of the working clock signal, M is a positive integer, the clock frequency division trigger module can obtain the clock frequency division trigger signal based on the second clock signal, the clock frequency divider can identify the rising edge or the falling edge of the clock frequency division trigger signal to generate the working clock signal, the working clock signal is used for controlling the next stage of circuit to generate preset phase delay, and accurate control of the working clock phase of the next stage of circuit is achieved.
In one embodiment, the clock phase control circuit further comprises:
the reset unit is connected with the clock frequency division triggering module and used for providing a reset signal for the clock frequency division triggering module so as to reset the counter unit; and/or
And the abnormal reset module is connected with the clock frequency divider and used for providing an abnormal reset signal for the clock frequency divider so as to reset the clock frequency divider.
In the clock phase control circuit in the above embodiment, the reset unit is connected to the clock frequency division trigger module and configured to provide a reset signal to the clock frequency division trigger module to reset the clock frequency division trigger module, so that a user can provide the reset signal to the clock frequency division trigger module based on the reset unit, and an abnormality of a frame clock signal counter caused by an internal abnormality of the clock phase control circuit is avoided. The clock frequency divider is connected with the clock frequency divider through the abnormal reset module and used for providing an abnormal reset signal for the clock frequency divider so as to reset the clock frequency divider, and the clock frequency divider can be triggered to reset when the phase-locked loop is unlocked or the I2S sampling rate is set to be wrong in the clock frequency divider.
In one embodiment, the first clock signal is a clock signal of an I2C bus; the second clock signal is the clock signal of the I2S bus. The clock signal of the I2C bus and the clock signal of the I2S bus are respectively used as the first clock signal and the second clock signal of the clock phase control circuit, so that the clock phase control circuit outputs a working clock signal to control the phase delay of the next-stage circuit, the structure and the layout of the clock phase control circuit are optimized, and the implementation difficulty and the implementation cost of the clock phase control circuit are reduced.
A second aspect of the present application provides a power amplifying device comprising:
a boost converter circuit; and
in any of the clock phase control circuits described in the embodiments of the present application, the operating clock signal output by the clock phase control circuit is used to control the phase delay of the boost converter circuit.
In the power amplifying device in the above embodiment, the interface module may receive a first clock signal and a clock phase parameter setting signal, and generate a clock enable signal and a clock phase control signal according to the first clock signal and the clock phase parameter setting signal; generating a system clock signal based on the received second clock signal and the clock enable signal by using a clock generation module; setting a phase control module to generate a phase delay control signal according to the received clock phase control signal; setting a clock frequency division trigger module to receive the second clock signal and the phase delay control signal and generate a clock frequency division trigger signal according to the second clock signal and the phase delay control signal; the clock frequency divider can generate a working clock signal based on the received system clock signal, the phase delay control signal and the clock frequency division trigger signal, and the working clock signal is used for controlling the boost conversion circuit to generate preset phase delay so as to realize accurate control of the working clock phase of the boost conversion circuit.
A third aspect of the present application provides an audio device comprising:
the power amplification circuits comprise boost conversion circuits;
the number of the clock phase control circuits is the same as that of the power amplification circuits, and the clock phase control circuits are connected with the boost conversion circuits of the power amplification circuits in a one-to-one manner and used for respectively controlling the boost conversion circuits of the power amplification circuits;
the working clock signals output by the clock phase control circuits respectively control the boost conversion circuits to generate preset phase delay.
In the audio device in the above embodiment, the interface module may receive a first clock signal and a clock phase parameter setting signal, and generate a clock enable signal and a clock phase control signal according to the first clock signal and the clock phase parameter setting signal; generating a system clock signal based on the received second clock signal and the clock enable signal by using a clock generation module; setting a phase control module to generate a phase delay control signal according to the received clock phase control signal; setting a clock frequency division trigger module to receive the second clock signal and the phase delay control signal and generate a clock frequency division trigger signal according to the second clock signal and the phase delay control signal; such that a clock divider may generate an operating clock signal based on the received system clock signal, the phase delay control signal, and the clock division trigger signal. The working clock signals of the clock phase control circuits are used for respectively controlling the boost conversion circuits in the power amplification circuits, so that the boost conversion circuits respectively generate preset phase delay, overload possibly caused by the homodromous switching of the boost conversion circuits is avoided, and the overload of a battery of audio equipment or overheating of a product is avoided.
In one embodiment, each of the clock phase control circuits is configured to output a different operating clock signal to respectively control each of the boost converter circuits to generate a different phase delay, so as to avoid overload of the power supply battery caused by the plurality of boost converter circuits drawing current in the same direction.
A fourth aspect of the present application provides a clock phase control method, applied to a clock phase control circuit, where the clock phase control circuit includes an interface module, a clock generation module, a phase control module, a clock frequency division trigger module, and a clock frequency divider, and the method includes:
controlling the interface module to generate a clock enable signal and a clock phase control signal based on the received first clock signal and the clock phase parameter setting signal;
controlling the clock generation module to generate a system clock signal according to a second clock signal and the clock enable signal;
controlling the phase control module to generate a phase delay control signal according to the clock phase control signal;
and controlling the clock frequency division triggering module to generate a clock frequency division triggering signal according to the second clock signal and the phase delay control signal, so that the clock frequency divider generates a working clock signal according to the system clock signal, the clock frequency division triggering signal and the phase delay control signal, and the working clock signal is used for controlling the phase delay of a next-stage circuit.
In the clock phase control method in the foregoing embodiment, the interface module may be controlled to receive a first clock signal and a clock phase parameter setting signal, and to generate a clock enable signal and a clock phase control signal according to the received first clock signal and the clock phase parameter setting signal; controlling a clock generation module to generate a system clock signal based on the received second clock signal and the clock enable signal; the control phase control module generates a phase delay control signal according to the received clock phase control signal; controlling a clock frequency division triggering module to receive the second clock signal and the phase delay control signal and generate a clock frequency division triggering signal according to the second clock signal and the phase delay control signal; thereby enabling a clock divider to generate an operating clock signal based on the received system clock signal, the phase delay control signal, and the clock division trigger signal. And controlling the next-stage circuit to generate a preset phase delay by using the working clock signal so as to realize accurate control of the working clock phase of the next-stage circuit.
A fifth aspect of the present application provides a clock phase control method applied to an audio device, where the audio device includes a plurality of power amplification circuits having boost converter circuits, and a plurality of clock phase control circuits as described in any of the embodiments of the present application, the number of the clock phase control circuits is the same as the number of the power amplification circuits, and the clock phase control circuits are connected to the boost converter circuits of the power amplification circuits in a one-to-one manner, where the method includes:
generating working clock signals respectively by utilizing the clock phase control circuits according to the received first clock signals and the clock phase parameter setting signals;
and respectively controlling each boosting conversion circuit to generate preset phase delay by using each working clock signal.
In the method for controlling the clock phase of the audio power amplifier in the above embodiment, a first clock signal and a clock phase parameter setting signal may be received based on an interface module, and a clock enable signal and a clock phase control signal may be generated according to the received first clock signal and the clock phase parameter setting signal; receiving a second clock signal and the clock enable signal based on a clock generation module and generating a system clock signal according to the second clock signal and the clock enable signal; generating a phase delay control signal according to the received clock phase control signal based on a phase control module; receiving the second clock signal and the phase delay control signal based on a clock frequency division trigger module, and generating a clock frequency division trigger signal according to the second clock signal and the phase delay control signal; the system clock signal, the phase delay control signal, and the clock division trigger signal may be received based on a clock divider, and an operating clock signal may be generated according to the system clock signal, the phase delay control signal, and the clock division trigger signal. The working clock signals of the clock phase control circuits are used for respectively controlling the boost conversion circuits in the power amplification circuits, so that the boost conversion circuits respectively generate preset phase delay, and overload possibly caused by the same-direction switching of the boost conversion circuits in the audio equipment is avoided. By controlling each boost conversion circuit in the audio equipment to switch according to the preset phase difference delay, the peak-shifting current extraction of each power amplification circuit in the audio equipment is realized during working, and the phenomenon that the product is overheated or is shut down due to battery overload is avoided.
In one embodiment, the controlling, by using each of the operating clock signals, each of the boost converter circuits to generate a predetermined phase delay includes: and the working clock signals are used for respectively controlling the boosting conversion circuits to generate different phase delays, so that the phenomenon that the power battery is overloaded due to the fact that the plurality of boosting conversion circuits extract current in the same direction is avoided.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain drawings of other embodiments based on these drawings without any creative effort.
Fig. 1 is a circuit diagram of a clock phase control circuit according to a first embodiment of the present application.
Fig. 2 is a circuit diagram of a clock phase control circuit according to a second embodiment of the present application.
Fig. 3 is a circuit diagram of a clock phase control circuit according to a third embodiment of the present application.
Fig. 4 is a circuit diagram of a clock phase control circuit provided in a fourth embodiment of the present application.
Fig. 5 is a circuit diagram of a clock phase control circuit provided in a fifth embodiment of the present application.
Fig. 6 is a schematic diagram of an architecture of a power amplifying device according to a sixth embodiment of the present application.
Fig. 7 is a schematic structural diagram of an audio device provided in a seventh embodiment of the present application.
Fig. 8 is a timing diagram of clock phase control of an audio device according to an eighth embodiment of the present application.
Fig. 9 is a flowchart illustrating a clock phase control method according to a ninth embodiment of the present application.
Fig. 10 is a flowchart illustrating a clock phase control method according to a tenth embodiment of the present application.
Fig. 11 is a flowchart illustrating a clock phase control method according to an eleventh embodiment of the present application.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Where the terms "comprising," "having," and "including" are used herein, another element may be added unless an explicit limitation is used, such as "only," "consisting of … …," etc. Unless mentioned to the contrary, terms in the singular may include the plural and are not to be construed as being one in number.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present application.
In this application, unless otherwise expressly stated or limited, the terms "connected" and "connecting" are used broadly and encompass, for example, direct connection, indirect connection via an intermediary, communication between two elements, or interaction between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, the term "number" may be one or more.
The I2S Bus is simple and effective and can effectively improve the quality of output data, and is widely applied in various embedded audio systems.I 2S is a three-wire Bus, 3 signals are a serial clock SCK, a frame clock WS and a serial data signal SD. serial clock SCK, and also a bit clock BCK, namely, 1 pulse exists on the SCK every time 1 bit of digital audio data is transmitted, the frequency of the SCK is equal to the sampling frequency × sampling bit number of 2 ×, during the data transmission process, a transmitter and a receiver of an I2 7 Bus can be used as a host of the system to provide the clock frequency of the system, the frame clock WS, namely, a command (Sound channel) is selected, the frequency for switching the data of the left and right Sound channels is equal to the sampling frequency of the MSB 352, and the frequency of the clock WS is equal to the sampling frequency of the MSB 2, so that the MSB can be generated by a serial clock signal 3526 or a serial clock BCK based on the MSB format of the SCK.
As shown in fig. 1, a clock phase control circuit 100 provided in an embodiment of the present application includes an interface module 10, a clock generation module 20, a phase control module 30, a clock frequency division trigger module 40, and a clock frequency divider 50, where the interface module 10 is configured to receive a first clock signal and a clock phase parameter setting signal, and generate a clock enable signal and a clock phase control signal according to the first clock signal and the clock phase parameter setting signal, the clock generation module 20 is connected to the interface module 10, and is configured to receive a second clock signal and the clock enable signal, and generate a system clock signal SC L according to the second clock signal and the clock enable signal, the phase control module 30 is connected to the interface module 10, and is configured to receive the clock phase control signal and generate a phase delay control signal according to the clock phase control signal, the clock frequency division trigger module 40 is configured to receive the second clock signal and the phase delay control signal, and is configured to generate a Time _ delay signal according to the second clock phase control signal and the phase delay control signal, the clock frequency division trigger module 40 is configured to receive a clock frequency division trigger signal Time _ C _ trigger signal, and a clock frequency division trigger signal 67k _ Time _ trigger signal, and a clock frequency division trigger signal, wherein the clock frequency division trigger module 30 is configured to generate a clock frequency division trigger signal 67k _ Time _ trigger signal, and a clock frequency division trigger signal, and a clock frequency control signal, and a clock frequency division trigger signal, and a working clock frequency division trigger signal, and.
Specifically, in the clock phase control circuit of the above embodiment, the interface module 10 may be configured to receive a first clock signal, for example, a clock signal and a clock phase parameter setting signal of an I2C bus 60, and generate a clock enable signal and a clock phase control signal according to the first clock signal and the clock phase parameter setting signal, the clock phase parameter setting signal may be configured to configure a frequency parameter and/or a phase parameter of an operating clock of a subsequent stage controlled by the clock phase control circuit, the timetime I2C bus 60 is configured to provide the interface module 10 with the first clock signal and the clock phase parameter setting signal, so that the interface module 10 generates a clock enable signal and a clock phase control signal according to the received first clock signal and the clock phase parameter setting signal, the clock generation module 20 is connected to the interface module 10, the clock generation module 20 receives a second clock signal, for example, the I2S bus 70, and the clock enable signal, and generates a system clock signal L according to the received clock signal, the clock generation module 20 is connected to receive the clock signal and the clock enable signal, the interface module 10 is configured to receive the clock signal, the clock phase control circuit is configured to receive the clock signal, the clock phase delay control circuit generates a clock signal according to a clock signal, the clock phase delay control signal, the clock generation circuit generates a frequency division delay, and the clock generation circuit generates a frequency division control signal according to a frequency division control signal, the clock generation circuit generates a frequency division control signal, and the clock frequency division control circuit, and the clock generation circuit generates a frequency division control circuit, and the clock generation circuit may control circuit generates a clock generation circuit according to control circuit, and the clock generation circuit.
Preferably, in the clock phase control circuit in the above embodiment, the interface module 10 may be configured to: generating different clock phase control signals based on the received different clock phase parameter setting signals; and the phase control module 30 is configured to: and generating different clock frequency division trigger signals based on the received different clock phase control signals to control the clock frequency divider to generate working clock signals with different frequencies. The frequency of the working clock signal output by the clock phase control circuit is changed according to different configuration parameters, and different frequency requirements of different application scenes can be met while the phase delay of the next-stage circuit is controlled.
Further, in a clock phase control circuit 100 provided in an embodiment of the present application, as shown in fig. 2, a clock division triggering module 40 includes a counter unit 41 and a timing control unit 42. The counter unit 41 is configured to receive a second clock signal and generate a counting period value signal according to the second clock signal; the timing control unit 42 is respectively connected to the counter unit 41 and the phase control module 30, and configured to receive the count period value signal and the phase delay control signal, and generate the clock division trigger signal Time _ OK according to the count period value signal and the phase delay control signal.
Specifically, in the clock phase control circuit in the above embodiment, since the clock generation module 20 generates the system clock signal SC L based on the received second clock signal, for example, the clock signal of the I2S bus and the clock enable signal, and the operation clock signal BOOST _ C L K generated by the clock divider 50 is generated based on the system clock signal SC L, the counter unit 41 is configured to generate a count period value signal based on the received second clock signal, and the count period value of the counter unit 41 may be set, so that when the count value obtained by the counter unit 41 based on the received second clock signal reaches the preset count period value, the counter unit 41 may provide the count period value signal to the timing control unit 42, so that the timing control unit 42 generates the clock division trigger signal Time _ OK to trigger the clock divider 50 to generate the operation clock signal BOOST _ C L K, and the operation clock signal BOOST _ C L K is used to control the next-stage circuit to generate the preset phase delay, thereby implementing accurate control of the operation clock phase of the next-stage circuit.
Further, in the clock phase control circuit in the above embodiment, the counter unit is configured to:
acquiring integral multiples of the minimum period value of the working clock signal as the counting period value of the counter unit;
when the count value of the counter unit reaches the count period value, the counter unit generates the count period value signal.
In the clock phase control circuit in the above embodiment, the counter unit may be configured to read a number of frames in the acquired second clock signal, and output a count period value signal when the number reaches a preset value, so that the timing control unit outputs the clock frequency division trigger signal based on the count period value signal and the phase delay control signal. The clock division trigger signal may be set to be a periodic pulse signal, and a period value of the clock division trigger signal may be an integer multiple of a minimum period value of the operating clock signal, so that the clock division trigger signal may trigger the clock divider to generate the operating clock signal. If the frequency of the working clock signal generated by the clock frequency divider is a fixed value, the integral multiple of the period value of the working clock signal can be directly obtained as the counting period value of the counter unit; if the frequency of the working clock signal generated by the clock divider is adjustable, for example, the working clock signal has two different frequency values, that is, the working clock signal has two different period values, the least common multiple of the two different period values can be obtained as the counting period value of the counter unit. The working clock signal is used for controlling a next-stage circuit to generate preset phase delay, so that the accurate control of the working clock phase of the next-stage circuit is realized.
Further, in a clock phase control circuit 100 provided in an embodiment of the present application, as shown in fig. 3, the clock division triggering module 40 includes a frame clock divider 43, where the frame clock divider 43 is configured to receive the second clock signal and generate a clock division triggering signal Time _ OK. according to the second clock signal, the frame clock divider 43 may be configured to divide the received second clock signal by frequency to obtain a periodic clock division triggering signal, the period value of the clock division triggering signal may be set so that the clock divider 50 may identify a rising edge or a falling edge of the clock division triggering signal Time _ OK, and after identifying the rising edge or the falling edge of the clock division triggering signal Time _ OK, the clock divider may divide the system clock signal SC L provided by the clock generation module 20 by a preset delay to generate the operating clock signal BOOST _ C L K, and the operating clock signal is used to control a next-stage circuit, such as a preset phase delay generated by a load, so as to achieve accurate control of the operating clock phase of the load.
Further, in the clock phase control circuit in the above embodiment, the frame clock divider is configured to:
acquiring 2 of the second clock signalNThe frequency division signal is used as the clock frequency division trigger signal, and N is a positive integer;
if the frequency of the second clock signal is fs, the frequency of the working clock signal is f, the period value of the clock frequency division trigger signal is M times of the period value of the working clock signal, and M is a positive integer, then:
thus, N can be calculated according to the following formula:
in the clock phase control circuit in the above embodiment, the frame clock divider is configured to obtain 2 of the received second clock signalNThe frequency division signal is used as the clock frequency division trigger signal, N is a positive integer, the period value of the clock frequency division trigger signal is set to be M times of the period value of the working clock signal, M is a positive integer, the clock frequency division trigger module can obtain the clock frequency division trigger signal based on the second clock signal, the clock frequency divider can identify the rising edge or the falling edge of the clock frequency division trigger signal to generate the working clock signal, the working clock signal is used for controlling the next stage of circuit to generate preset phase delay, and accurate control of the working clock phase of the next stage of circuit is achieved.
Further, in the clock phase control circuit in the above embodiment, if the frequency of the working clock signal generated by the clock divider is adjustable, for example, the working clock signal has two different frequency values, that is, the working clock signal has two different period values, a least common multiple of the two different period values may be obtained as the period value of the clock division trigger signal.
Further, in a clock phase control circuit 100 provided in an embodiment of the present application, as shown in fig. 4, a reset unit 80 is further included, and the reset unit 80 is connected to the clock division triggering module 40 and configured to provide a reset signal to the clock division triggering module to reset the clock division triggering module.
Specifically, as shown in fig. 4, a reset unit 80 may be provided in connection with the counter unit 41 for providing a reset signal to the counter unit 41 to reset the counter unit 41. So that the user can supply the reset signal to the counter unit 41 based on the reset unit 80 to avoid the frame clock signal counter abnormality caused by the clock phase control circuit internal abnormality.
Further, in a clock phase control circuit 100 provided in an embodiment of the present application, as shown in fig. 5, an exception reset module 90 is further included, where the exception reset module 90 is connected to the clock divider 50 and is configured to provide an exception reset signal to the clock divider 50 to reset the clock divider 50. The clock frequency divider is connected with the clock frequency divider through the abnormal reset module and used for providing an abnormal reset signal for the clock frequency divider so as to reset the clock frequency divider, and the clock frequency divider can be triggered to reset when the phase-locked loop is unlocked or the I2S sampling rate is set to be wrong in the clock frequency divider.
Furthermore, in the clock Phase control circuit in the above embodiment, as shown in fig. 5, the interface module 10 may employ an I2C interface module 11, may employ an I2C interface module 11 to receive a clock signal and a clock Phase parameter setting signal of an I2C bus 60, and generate a clock enable signal and a clock Phase control signal according to the I2C bus clock signal and the clock Phase parameter setting signal, a user may employ at least one of an I2C interface module and an I2C bus 60 to control a frequency parameter and/or a Phase parameter of a working clock of a subsequent stage circuit controlled by the clock Phase control circuit, and may employ a P LL circuit or a crystal oscillator circuit to generate a clock signal, which may not only improve accuracy of the clock Phase control circuit in controlling Phase difference of each audio frequency, but also reduce complexity and cost of circuit design, and may set a Phase-locked loop circuit 20 to set a frequency value of a clock Phase counter 21 to generate a clock signal, a clock Phase signal count signal, a clock cycle count signal, a cycle count signal, a cycle count, a clock cycle, a clock cycle, and a clock cycle count, a clock cycle of a clock cycle.
As shown in fig. 6, a power amplification apparatus 200 provided in an embodiment of the present application includes a boost converter circuit 201; and the clock phase control circuit 100 in any of the embodiments of the present application, the working clock signal output by the clock phase control circuit 100 is used to control the phase delay of the boost converter circuit 201.
Specifically, a first clock signal and a clock phase parameter setting signal may be received based on an interface module, and a clock enable signal and a clock phase control signal may be generated according to the first clock signal and the clock phase parameter setting signal; generating a system clock signal based on the received second clock signal and the clock enable signal by using a clock generation module; setting a phase control module to generate a phase delay control signal according to the received clock phase control signal; setting a clock frequency division trigger module to receive the second clock signal and the phase delay control signal and generate a clock frequency division trigger signal according to the second clock signal and the phase delay control signal; the clock frequency divider can generate a working clock signal based on the received system clock signal, the phase delay control signal and the clock frequency division trigger signal, and the working clock signal is used for controlling the boost conversion circuit to generate preset phase delay so as to realize accurate control of the working clock phase of the boost conversion circuit.
In an embodiment of the present application, an audio device includes a plurality of power amplification circuits, where each of the power amplification circuits includes a boost converter circuit, and a plurality of clock phase control circuits as described in any of the embodiments of the present application, where the number of the clock phase control circuits is the same as that of the power amplification circuits, and the clock phase control circuits are connected to the boost converter circuits of the power amplification circuits in a one-to-one manner, and are used to control the boost converter circuits of the power amplification circuits, respectively; the working clock signal output by each clock phase control circuit is used for respectively controlling each boost conversion circuit to generate preset phase delay.
Preferably, each of the clock phase control circuits may be configured to output a different operating clock signal to respectively control each of the boost converter circuits to generate a different phase delay, so as to avoid overload of the power supply battery caused by current being drawn in the same direction by the plurality of boost converter circuits.
Specifically, as shown in fig. 7, an audio device 300 provided in an embodiment of the present application includes a power amplifier circuit a, a power amplifier circuit B, a clock phase control circuit a, and a clock phase control circuit B, where the power amplifier circuit a and the power amplifier circuit B respectively include a BOOST converter circuit, where an operating clock signal BOOST _ C L K _ a output by the clock phase control circuit a is used for controlling the BOOST converter circuit in the power amplifier circuit a to generate a preset phase delay, and an operating clock signal BOOST _ C L K _ B output by the clock phase control circuit B is used for controlling the BOOST converter circuit in the power amplifier circuit B to generate a preset phase delay.
Specifically, in the audio device of the above embodiment, after configuring clock phase parameters of the power amplifier circuit a and the power amplifier circuit B through the I2C bus 60 and the I2C interface module by the control circuit 301 as shown in fig. 7-8, the I2C interface module may be configured to receive a clock signal and a clock phase parameter setting signal of the I2C bus 60 and generate a clock enable signal and a clock phase control signal according to the clock signal of the Time I2C bus 60 and the clock phase parameter setting signal, the clock generation module may be configured to generate a system clock signal based on the clock signal of the I2S bus 70 and the clock enable signal, the clock phase control module may be configured to generate a phase delay control signal according to the received clock phase control signal, the clock division trigger module may be configured to receive the clock signal and the phase delay control signal of the I2S bus 70 and the phase delay control signal, and the clock division trigger signal may be configured to generate clock signals according to a clock signal count up clock signal and clock phase delay clock signal count signal of the clock signal generated by the clock division trigger circuit B, clock division trigger circuit C, and clock division trigger circuit C, the clock division trigger circuit may be configured to generate clock signal, and clock signal, the clock signal may be configured to generate clock signal according to count up clock signal, and clock signal count up clock signal of the clock signal generation circuit B switch clock signal of the clock signal generation circuit, clock division clock signal of the clock generation circuit, clock signal generation unit of the clock generation timing switch timing control unit of the clock generation timing generation unit, the timing generation.
In the audio device in the above embodiment, the controller of the control circuit may at least adopt one of a single chip, an ARM, a DSP, or an FPGA.
In an embodiment of the present application, a clock phase control method is provided, which is applied to a clock phase control circuit, where the clock phase control circuit may be the clock phase control circuit described in any embodiment of the present application, and the clock phase control circuit includes an interface module, a clock generation module, a phase control module, a clock division trigger module, and a clock divider, as shown in fig. 9, the method includes:
step 202: controlling the interface module to generate a clock enable signal and a clock phase control signal based on the received first clock signal and the clock phase parameter setting signal.
Step 204: and controlling the clock generation module to generate a system clock signal according to a second clock signal and the clock enable signal.
Step 206: and controlling the phase control module to generate a phase delay control signal according to the clock phase control signal.
Step 208: and controlling the clock frequency division triggering module to generate a clock frequency division triggering signal according to the second clock signal and the phase delay control signal, so that the clock frequency divider generates a working clock signal according to the system clock signal, the clock frequency division triggering signal and the phase delay control signal, and the working clock signal is used for controlling the phase delay of a next-stage circuit.
Specifically, in the clock phase control method in the foregoing embodiment, the interface module may be controlled to receive a first clock signal and a clock phase parameter setting signal, and to generate a clock enable signal and a clock phase control signal according to the received first clock signal and the clock phase parameter setting signal; controlling a clock generation module to generate a system clock signal based on the received second clock signal and the clock enable signal; the control phase control module generates a phase delay control signal according to the received clock phase control signal; controlling a clock frequency division triggering module to receive the second clock signal and the phase delay control signal and generate a clock frequency division triggering signal according to the second clock signal and the phase delay control signal; thereby enabling a clock divider to generate an operating clock signal based on the received system clock signal, the phase delay control signal, and the clock division trigger signal. And controlling the next-stage circuit to generate a preset phase delay by using the working clock signal so as to realize accurate control of the working clock phase of the next-stage circuit.
Further, in an embodiment of the present application, a clock phase control method for an audio power amplifier is provided, which is applied to an audio device, where the audio device includes a plurality of power amplification circuits having boost converter circuits, and a plurality of clock phase control circuits as described in any embodiment of the present application, where the number of the clock phase control circuits is the same as the number of the power amplification circuits, and the clock phase control circuits are connected to the boost converter circuits of the power amplification circuits in a one-to-one manner, as shown in fig. 10, where the method includes:
step 302: and respectively generating working clock signals by using the clock phase control circuits according to the received first clock signals and the clock phase parameter setting signals.
Step 304: and respectively controlling each boosting conversion circuit to generate preset phase delay by using each working clock signal.
Specifically, in the method for controlling the phase of the audio power amplifier clock in the above embodiment, the clock generation module may output the system clock signal based on the serial clock signal or the frame clock signal of the I2S bus and the clock enable signal output by the I2C interface module, so that the clock generation module provides the system clock signal to the clock divider; generating, by a phase control module, a phase delay control signal based on a clock phase control signal output by the I2C interface module; generating a clock frequency division trigger signal by a clock frequency division trigger module on the basis of the acquired serial clock signal or frame clock signal of the I2S bus and the phase delay control signal, wherein the clock frequency division trigger signal is a periodic pulse signal; generating, by a clock divider, a working clock signal based on the system clock signal, the phase delay parameter signal, and the clock division trigger signal. The working clock signals of the clock phase control circuits are used for respectively controlling the boost conversion circuits in the power amplification circuits, so that the boost conversion circuits respectively generate preset phase delay, and overload possibly caused by the same-direction switching of the boost conversion circuits in the audio equipment is avoided. By controlling each boost conversion circuit in the audio equipment to switch according to the preset phase difference delay, the peak-shifting current extraction of each power amplification circuit in the audio equipment is realized during working, and the phenomenon that the product is overheated or is shut down due to battery overload is avoided.
Further, in an embodiment of the present application, a method for controlling a phase of an audio power amplifier clock is provided, as shown in fig. 11, step 304 includes:
step 3041: and respectively controlling the boosting conversion circuits to generate different phase delays by using the working clock signals.
The clock phase control circuits are configured to output different working clock signals so as to respectively control the boost conversion circuits to generate different phase delays, and the phenomenon that the plurality of boost conversion circuits draw current in the same direction to cause overload of a power supply battery is avoided.
For specific limitations of the clock phase control method in the above embodiments, reference may be made to the limitations of the clock phase control circuit, which are not described herein again.
It should be understood that although the various steps in the flowcharts of fig. 9-11 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 9-11 may include several sub-steps or several stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
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