阅读说明：本技术 基于siwave软件的arm pdn优化设计方法 (ARM PDN optimization design method based on SIWAVE software ) 是由 李天强 于 2020-02-20 设计创作，主要内容包括：本发明提供了一种基于SIWAVE软件的ARM PDN优化设计方法,首先确定ARM的电源分配网络PDN的目标阻抗；在SIWAVE软件中,使用PDN电容指定S参数,编译Z参数；通过改变PDN布局或电容选择,使Z参数与目标阻抗的差值在设定范围内；确定需要优化的电容；设定仿真参数,重新编译计算,通过改变电容选择,使仿真阻抗在目标阻抗内,此时软件会自动去掉高环路电感的电容,得到最终的仿真结果；据此更改ARM PDN原理图,形成最终ARM PDN设计。本发明可以自动优化和配置电容的型号和数量,实现最佳的ARM PDN布局设计,从而能节省PCB空间,降低ARM电源噪声,提高EMC一次通过率,节省成本。(The invention provides an ARM PDN optimization design method based on SIWAVE software, which comprises the steps of firstly determining the target impedance of a power distribution network PDN of an ARM; in SIWAVE software, a PDN capacitor is used for designating an S parameter, and a Z parameter is compiled; the difference value of the Z parameter and the target impedance is in a set range by changing PDN layout or capacitance selection; determining the capacitance needing to be optimized; setting simulation parameters, recompiling and calculating, and changing capacitance selection to enable the simulation impedance to be within the target impedance, wherein at the moment, software can automatically remove the capacitance of the high-loop inductor to obtain a final simulation result; and changing the ARM PDN schematic diagram to form the final ARM PDN design. The invention can automatically optimize and configure the type and the number of the capacitors, and realize the optimal ARM PDN layout design, thereby saving the PCB space, reducing the ARM power supply noise, improving the EMC one-time passing rate and saving the cost.)

1. An ARM PDN optimization design method based on SIWAVE software is characterized by comprising the following steps:

step S1: determining target impedance of a power distribution network PDN of the ARM;

step S2: compiling a Z parameter of the PDN by using a designated S parameter of the capacitance of the PDN in a PI Advisor application function module of SIWAVE software; comparing the Z parameter to the target impedance: if the difference value is in the set range, go to step S3; otherwise, resetting the PDN layout or capacitance selection, recompiling and calculating until the difference value of the PDN layout or capacitance selection is within a set range, and turning to the step S3;

step S3: determining the capacitance needing to be optimized;

step S4: the method comprises the steps of appointing capacitors of multiple models for capacitors needing to be optimized, and setting the number of the capacitors of each model;

step S5: setting simulation parameters through a PI Advisor application function module of SIWAVE simulation software, recompiling and calculating, and selecting a simulation configuration scheme; comparing the simulated impedance of the selected simulated configuration scheme to the target impedance: if the simulated impedance is less than or equal to the target impedance, go to step S6; otherwise, resetting the capacitance selection, recompiling and calculating until the simulated impedance is less than or equal to the target impedance, and turning to step S6;

step S6: when the simulation impedance is smaller than or equal to the target impedance, removing the capacitance of the high-loop inductor by using SIWAVE simulation software to obtain a final simulation result;

step S7: and according to the final simulation result, changing the ARM PDN schematic diagram, updating the PDN layout design and forming the final ARMPDN design.

2. The ARM PDN optimization design method based on SIWAVE software as claimed in claim 1, wherein: in step S1, the target impedance is calculated by: the product of the operating voltage and the percentage of the allowed ripple voltage is divided by half the maximum transient current.

3. The ARM PDN optimization design method based on SIWAVE software as claimed in claim 1, wherein: in the step S2, if the value of the Z parameter between 100kHz and 50MHz is within 130% of the target impedance, directly switching to the step S3;

otherwise, optimizing L ayout layout design of the PDN, or increasing the capacitance quantity at the effective position, or changing the capacitance model at the effective position, compiling the Z parameter of the PDN again until the value of the Z parameter between 100kHz and 50MHz is within 130% of the target impedance, and turning to step S3.

4. The ARM PDN optimization design method based on SIWAVE software as claimed in claim 1, wherein: in step S3, the capacitance to be optimized is a capacitance whose capacitance value exceeds a set threshold value.

5. The ARM PDN optimization design method based on SIWAVE software as claimed in claim 4, wherein: the set threshold is 10 uF.

6. The ARM PDN optimization design method based on SIWAVE software as claimed in claim 1, wherein: in step S3, the capacitors to be optimized are capacitors distributed on the bottom layer of the ARM and DDR3 BGA packages.

7. The ARM PDN optimization design method based on SIWAVE software as claimed in claim 1, wherein: in step S4, the capacitance types are distributed in the upper and lower 3 capacitance ranges of the capacitance value of the current capacitance.

8. The ARM PDN optimization design method based on SIWAVE software as claimed in claim 1 or 7, wherein: in step S4, the capacitor model is selected according to the application level of the automotive electronics.

9. The ARM PDN optimization design method based on SIWAVE software as claimed in claim 1, wherein: in step S5, when the simulated impedance exceeds the target impedance, the following determination is made:

if the highest value of the simulated impedance exceeds 20% of the target impedance, adding capacitors with proper types aiming at the frequency points exceeding the target impedance; recompiling and calculating until the simulated impedance is within the target impedance, and turning to the step S6;

and if the highest value of the simulated impedance is within 120 percent of the target impedance, selecting the capacitance of the equivalent inductance ES L lower than the current capacitance for the frequency points exceeding the target impedance, recompiling and calculating until the simulated impedance is within the target impedance, and turning to the step S6.

Technical Field

The invention relates to an ARM PDN optimization design method, in particular to an ARM PDN optimization design method based on simulation of SIWAVE software, and belongs to the technical field of automobile electronic power simulation.

Background

The ARM processor is the first RISC microprocessor designed by Acorn computer Limited for the low-budget market. In the field of automotive electronics, the use of ARM is more and more widespread, the function of ARM is more and more powerful, and PDN (power distribution network) of ARM is more and more. The size of the ARM is smaller and smaller, the voltage of the power supply is lower and lower, the power supply voltage of the power supply is about 0.8V, and the ripple requirement on the power supply is higher and higher. Placing capacitors with proper quantity, packaging, capacitance value and model becomes the key for improving the performance of the PDN, and good PDN performance is a key index of EMC (electromagnetic compatibility) performance of a high-speed signal PCB (printed circuit board).

With the rapid development of the automotive electronics industry and the massive use of high-speed communication data, wireless data processing and high-definition large screens, the requirement on the ARM is higher and higher. Because the ARM has as many as dozens of key PDNs, the number of decoupling capacitors connected in parallel to a single PDN is very limited, and it is necessary to select capacitors with appropriate number and type.

In the conventional technology, the performance of the PDN is usually improved by increasing the number of capacitors, which is very poor, and this method not only wastes capacitors but also occupies a large PCB space and requires a long debugging time. In addition, multiple capacitive solders also cause an increase in mounting inductance, increasing data errors on the circuit board.

Currently, there are several methods for optimizing and evaluating ARM PDN:

(1) the ripple of the power supply was tested using an oscilloscope. This is a conventional assessment method. Measurements made based on the physical properties of the PCB require a finished PCB and related materials. The method has low precision for high-frequency noise, and needs to be changed, manufactured and measured again when the test result has problems. This is a challenge to both the development cost and development time of the project.

(2) The power plane impedance Z11 was tested using a network analyzer. This is a relatively new test method. A comprehensive test method based on the physical characteristics of the PCB and the via hole, the capacitance and inductance characteristics of the installation and the like. The method is effective and has reference value for the PDN system with the power supply noise within 30 MHz; however, for the PDN system with noise greater than 30MHz, it is difficult to obtain data with reference value due to the limit values of the test point position, the test harness, the test fixture, and the like.

(3) And (6) simulating. The power plane impedance of the capacitor combined in the current state can be simulated by using Hyperlynx19.2 version simulation software, and whether the requirement of target impedance is met or not is judged, but the model and the number of the capacitor cannot be automatically configured. The number of capacitors or the types of the capacitors needs to be readjusted in each simulation, and the adjustment effect is poor.

The SIWAVE software is software integrating electromagnetic field simulation, signal integrity simulation, power integrity simulation, electronic thermal simulation and chip simulation, and obtains more real data by extracting S parameters of 2D and 3D devices, PCB transmission lines and the like to establish a system and a high-precision complex simulation circuit.

The ARM PDN is a power distribution network system distributed inside the PCB below the ARM chip. The number of important power supplies of ARM is at least 6, the number of layers of PCB is 6 to 8, and considering the distribution of DDR3 signal layers and other important signal lines and the distribution of Ground reference layers, the planar distribution of the important power supplies is very critical and important, and the capacitance distribution of the network is also very critical. Therefore, how to distribute the appropriate capacitance is very difficult for a PDN.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a method for realizing the optimal ARM PDN layout design by automatically optimizing and configuring the type and the number of capacitors according to target impedance.

In order to solve the technical problems, the technical scheme of the invention is to provide an ARMPDN optimization design method based on SIWAVE software, which comprises the following steps:

step S1: determining target impedance of a power distribution network PDN of the ARM;

step S2: compiling a Z parameter of the PDN by using a designated S parameter of the capacitance of the PDN in a PI Advisor application function module of SIWAVE software; comparing the Z parameter to the target impedance: if the difference value is in the set range, go to step S3; otherwise, resetting the PDN layout or capacitance selection, recompiling and calculating until the difference value of the PDN layout or capacitance selection is within a set range, and turning to the step S3;

step S3: determining the capacitance needing to be optimized;

step S4: the method comprises the steps of appointing capacitors of multiple models for capacitors needing to be optimized, and setting the number of the capacitors of each model;

step S5: setting simulation parameters through a PI Advisor application function module of SIWAVE simulation software, recompiling and calculating, and selecting a simulation configuration scheme; comparing the simulated impedance of the selected simulated configuration scheme to the target impedance: if the simulated impedance is less than or equal to the target impedance, go to step S6; otherwise, resetting the capacitance selection, recompiling and calculating until the simulated impedance is less than or equal to the target impedance, and turning to step S6;

step S6: when the simulation impedance is smaller than or equal to the target impedance, the SIWAVE simulation software can automatically remove the capacitance of the high-loop inductor to obtain a final simulation result;

step S7: and according to the final simulation result, changing the ARM PDN schematic diagram, updating the PDN layout design and forming the final ARM PDN design.

Preferably, in step S1, the target impedance is calculated by: the product of the operating voltage and the percentage of the allowed ripple voltage is divided by half the maximum transient current.

Preferably, in the step S2, if the value of the Z parameter between 100kHz and 50MHz is within 130% of the target impedance, go directly to step S3;

otherwise, optimizing L ayout layout design of the PDN, or increasing the capacitance quantity at the effective position, or changing the capacitance model at the effective position, compiling the Z parameter of the PDN again until the value of the Z parameter between 100kHz and 50MHz is within 130% of the target impedance, and turning to step S3.

Preferably, in step S3, the capacitance to be optimized is a capacitance whose capacitance value exceeds a set threshold value.

More preferably, the set threshold is 10 uF.

Preferably, in the step S3, the capacitors to be optimized are capacitors distributed on the bottom layer of the ARM and DDR3 BGA packages.

Preferably, in step S4, the capacitance types are distributed in the upper and lower 3 capacitance ranges of the capacitance of the current capacitance.

Preferably, in the step S4, the model of the capacitor is selected to meet the application level of the automotive electronics.

Preferably, in step S5, when the simulated impedance exceeds the target impedance, the following judgment is made:

if the highest value of the simulated impedance exceeds 20% of the target impedance, adding capacitors with proper types aiming at the frequency points exceeding the target impedance; recompiling and calculating until the simulated impedance is within the target impedance, and turning to the step S6;

and if the highest value of the simulated impedance is within 120 percent of the target impedance, selecting the capacitance of the equivalent inductance ES L lower than the current capacitance for the frequency points exceeding the target impedance, recompiling and calculating until the simulated impedance is within the target impedance, and turning to the step S6.

Compared with the prior art, the ARM PDN optimization design method based on SIWAVE software provided by the invention has the following beneficial effects:

(1) the optimal state of the ARM PDN capacitor design can be rapidly obtained through simulation based on SIWAVE software;

(2) in the simulation process, the design deviation can be quickly found, and then the optimization design is further carried out;

(3) the quantity of ARM capacitors can be optimized, redundant capacitors are screened out through the loop inductors of the decoupling capacitors, the application of invalid decoupling capacitors is reduced, a large number of capacitors are saved, the PCB space is vacated, and conditions are created for optimization of other power supplies;

(4) the most suitable capacitor model can be selected according to the target impedance, and the optimal ARM PDN layout design is realized, so that the power supply noise of an ARM system level can be reduced, the EMC one-time passing rate can be improved, and the project development cost is saved.

Drawings

Fig. 1 is a flowchart of an ARM PDN optimization design method based on SIWAVE software according to this embodiment;

FIG. 2 is a distribution diagram of a PAD PAD of a U13000 chip;

FIG. 3 is a diagram of the overall network capacitance distribution of the bottom DDR 3;

FIG. 4 is a schematic diagram of partial capacitance at the DDR3 end on a schematic diagram before simulation;

FIG. 5 is another schematic diagram of the capacitor at the DDR3 end on the schematic diagram before simulation;

FIG. 6 is a diagram of a distribution of capacitance at the ARM end of the PCB before emulation;

FIG. 7 is a schematic diagram of the C4100 capacitors in the SIWAVE simulation software having 6 candidate capacitors;

FIG. 8 is a schematic diagram of the setup of Wizard Threshold module in the SIWAVE simulation software;

FIG. 9 is a schematic diagram of optimizing the impedance of the front ARM terminal; wherein the abscissa Frequency represents Frequency and the ordinate Z11 represents impedance;

FIG. 10 is a schematic diagram of the impedance at DDR3 terminal before optimization; wherein the abscissa Frequency represents Frequency and the ordinate Z11 represents impedance;

FIG. 11 is a diagram of an ARM-end optimized PCB distribution;

FIG. 12 is a schematic diagram of the impedance of the optimized ARM terminal; wherein the abscissa Frequency represents Frequency and the ordinate Z11 represents impedance;

FIG. 13 is a diagram of the capacitance distribution of the ARM side high loop inductor;

FIG. 14 is a schematic diagram of the capacitance that needs to be optimized;

FIG. 15 is a schematic diagram of the impedance of the final ARM terminal; wherein the abscissa Frequency represents Frequency and the ordinate Z11 represents impedance;

FIG. 16 is an impedance diagram of the final DDR3 terminal; the abscissa Frequency represents Frequency, and the ordinate Z11 represents impedance.

Detailed Description

For automobile electronic intelligent network products, ARM has up to 13 power distribution networks PDN, such as SMPS, HMPS, etc., so that it is required to place the most suitable capacitor in a limited space, and the balancing difficulty of number, type, and packaging is large at a target cost. The embodiment realizes the optimization design of the ARM PDN through a novel effective simulation method.

Fig. 1 is a flowchart of an ARM PDN optimization design method based on SIWAVE software according to this embodiment, where the method provided by this embodiment uses a PI Advisor application function module of SIWAVE simulation software of ANSYS corporation, and the ARM PDN optimization design method based on SIWAVE software includes the following steps:

the first step is to determine the target impedance of a certain power distribution network PDN of the ARM.

In general, the target impedance is defined as: the product of the operating voltage and the percentage of the allowable ripple voltage, divided by the value of half the maximum transient current, is given by:

wherein Z is_targetFor target impedance, Voltage Rail is the operating Voltage,% Ripple is the percentage of the Ripple Voltage allowed, I_{max transient}Is the maximum transient current.

The target impedance is the basic target impedance, most of the power supply noise is distributed between 100kHz and 20MHz, and therefore, the calculated value frequency domain is applied to the frequency band. Since the current ARM power supplies provide charge for high speed signals, the rate of high speed signal transmission is high and therefore considering 100kHz to 20MHz alone is not sufficient. It is also empirically desirable to set 20MHz to 50MHz, and the impedance of this band is generally recommended to be around 3 times the basic target impedance. While the target impedance above 50MHz is used for reference only, since the impedance of this band is mainly determined by the chip itself. While the impedance below 100kHz depends mainly on the dynamic output capability of the switching power supply, non-PDN capacitance and planar impedance design.

Secondly, in a PI Advisor application function module of SIWAVE simulation software, compiling a Z parameter of the PDN by using a specified S parameter of the capacitance of the PDN, and comparing the Z parameter of the PDN with a target impedance:

if the value of the Z parameter between 100kHz and 50MHz is within 130 percent of the target impedance (including 130 percent of the target impedance), then switching to the third step;

otherwise, i.e. if the value of the Z parameter between 100kHz and 50MHz exceeds 30% of the target impedance, the L ayout design of the power distribution network PDN is optimized, or the number of capacitors is added in active positions, or the capacitor model is changed in active positions, and the Z parameter of the power distribution network PDN is compiled again until the value of the Z parameter between 100kHz and 50MHz is within 130% of the target impedance, going to the third step.

And thirdly, determining the capacitance needing to be optimized.

The capacitances that need to be optimized fall into two basic categories: one is a large capacitance value capacitor, generally a capacitor with a capacitance value exceeding 10 uF; the second type is the capacitors distributed at the bottom of ARM and DDR3 BGA (ball grid array) packages.

And fourthly, appointing a plurality of types of capacitors for the capacitors needing to be optimized, and setting the number of the capacitors of each type. The capacitor models are distributed in the range of 3 capacitance values above and below the capacitance value of the current capacitor, and the model selection accords with the application level of automobile electronics.

Fifthly, setting simulation parameters through a PI Advisor application function module of SIWAVE simulation software, then recompiling and calculating, and selecting a simulation configuration scheme; and judging whether the simulation impedance of the selected simulation configuration scheme is within the target impedance:

if the impedance is within the target impedance, namely the simulated impedance is less than or equal to the target impedance, turning to the sixth step;

otherwise, when the simulated impedance exceeds the target impedance, judging that the highest value of the simulated impedance exceeds 20 percent of the target impedance, adding a capacitor combination with a proper model aiming at the frequency points exceeding the target impedance, if the highest value of the simulated impedance is within 120 percent of the target impedance (including 120 percent of the target impedance), selecting a capacitor combination with lower ES L (equivalent inductance) relative to the current capacitor aiming at the frequency points exceeding the target impedance, recompiling and calculating until the simulated impedance is within the target impedance, and turning to the sixth step.

Sixthly, when the simulation impedance is within the target impedance, the SIWAVE simulation software can automatically remove the capacitance of the high-loop inductor.

And seventhly, determining the change of the schematic diagram according to the simulation result, updating L ayout (PDN layout design), and forming the optimal ARM PDN design to achieve the double effects of cost reduction and performance optimization.

The optimization effect of the method is verified by a specific application example.

In this embodiment, the controller U13000 is an NXP model PIMX8UX ARM chip, BGA package, and the pad distribution is as shown in fig. 2. DRAM U14200 is MICRO MT41K128M16 with the capacitance distributed at the bottom of the PCB, see FIG. 3. The clock frequency is 930 MHz. The first use of PIMX8UX, NXP recommends the use of a large number of capacitors to improve the noise and ripple of the power supply. The capacitance schematic diagrams of DDRIO power supplies at two ends of PIMX8UX and DDR before simulation are shown in fig. 4 and fig. 5, the distribution condition of a capacitor PCB is shown in fig. 6, and the capacitors are 220nF capacitors packaged in 0402 and have the model of C1005X7R1C224KT0Y 0F.

The simulation software used the PI Advisor tool from SIWAVE from ANSYS. In the PI Advisor, firstly, according to the maximum transient working current of 1.35A, the working voltage of 1.35V and the ripple wave requirement of 1%, the obtained basic target impedance is 20 milliohm (100kHz-20MHz frequency band), and the target impedance from 20MHz to 50MHz frequency band is confirmed to be 2.5 times of the basic target impedance and is 50 milliohm; then all capacitors on the power network need to be selected; then, the capacitor at the bottom layer of the ARM package is optimized, different suppliers, different packages and different series of capacitor models can be selected, and capacitors of multiple models can be simultaneously selected. As in fig. 7, the C4100 capacitor has 6 candidate capacitors, SIWAVE will select the most suitable capacitor according to the target impedance and Wizard Threshold as set forth in fig. 8 (including the total cost of the capacitors, the total number of capacitors, the number of capacitors of a single model, and the area occupied by all capacitors), while providing multiple options for selection. And (4) completing simulation, and selecting an optimal scheme to determine the final model of the capacitor and the capacitor which can be deleted.

In the embodiment, according to the requirement of NXP company on the impedance of a VDD _ DDR power supply network, the target impedance of a PCB is set, the impedance of a power supply plane is controlled within 20 milliohms at a frequency band from 100kHz to 20MHz, the impedance of the frequency band from 20MHz to 50MHz is controlled within 50 milliohms, simulation results of PI Advisor are shown in FIG. 9, the highest impedance of a frequency point near 100kHz at an IMX8DX end is 50 milliohms, and the highest impedance of a frequency point near 8MHz is 35 milliohms and exceeds 30% of the target impedance value, so that corresponding capacitors need to be added or converted, and the impedance of a L ayout DDR3 end is optimized to meet the requirement, see FIG. 10, and the impedance of a frequency point near 10MHz is far smaller than the target impedance, so that some capacitors can be reduced at a DDR3 end.

Before optimization, the DDRIO overall power supply network had 32 capacitors and the 22uF large capacitor had up to 6, as shown in table 1, which was very wasteful.

TABLE 1 model and number of capacitors before optimization

After the optimization of the method, C13058 is replaced by 0603 package 22uF, as shown in figure 11.1 MHz frequency point impedance of 23.8 mOhm and 10MHz frequency point impedance of 23.5 mOhm which exceed the standard but within 20 percent of the standard, as shown in figure 12, L ow ES L capacitance needs to be selected to optimize the impedance of high frequency, because the capacitance quantity of IMX8DX end is limited, the DDR3 chip end needs to be considered for optimization together.

The loop inductances of all DDRIO network capacitances are checked to find some capacitances to be optimized, see fig. 13, and the capacitances in the circles need to be further optimized.

For the capacitors needing to be optimized, multiple models can be selected from the same capacitor, as shown in fig. 14, and the system automatically judges according to the set target impedance.

Through twice optimization of the PI Advisor, the number of the final capacitors is reduced from 32 to 20, and the BOM cost is also reduced by a lot according to the table 3. The final scheme of capacitance is chosen from table 4.

TABLE 3 capacitance value distribution

TABLE 4 capacitance model and area distribution

Finally, the impedance of the DDR port of the PIMX8UX is shown in fig. 15, the impedance of the DDR port of the DDR3 MT is shown in fig. 16, and as can be seen from fig. 15 and 16, both the DDR port of the PIMX8UX and the DDR port of the DDR3 MT meet the target impedance requirement of NXP from 100kHz to 100 MHz. And BOM costs can be reduced significantly. After the optimization scheme is determined, the capacitor without the matched capacitor model is the optimized capacitor, and the capacitor can be deleted.

While the invention has been described with respect to a preferred embodiment, it will be understood by those skilled in the art that the foregoing and other changes, omissions and deviations in the form and detail thereof may be made without departing from the scope of this invention. Those skilled in the art can make various changes, modifications and equivalent arrangements, which are equivalent to the embodiments of the present invention, without departing from the spirit and scope of the present invention, and which may be made by utilizing the techniques disclosed above; meanwhile, any changes, modifications and variations of the above-described embodiments, which are equivalent to those of the technical spirit of the present invention, are within the scope of the technical solution of the present invention.