阅读说明：本技术 半导体器件及其制造方法 (Semiconductor device and method for manufacturing the same ) 是由 李炫姃 文浚硕 禹东秀 于 2019-10-31 设计创作，主要内容包括：一种半导体器件和制造该半导体器件的方法,该方法包括：在基板上形成器件隔离层,该器件隔离层限定多个有源区；以及形成与有源区交叉且被掩埋在基板中的多条栅极线。形成栅极线包括在基板上形成与有源区交叉的沟槽；在沟槽的侧壁和底表面上形成功函数控制层；在功函数控制层上形成导电层；在功函数控制层上和在导电层上顺序地形成阻挡层和源层,源层包括功函数控制元素；以及使功函数控制元素从源层扩散到功函数控制层的上部分中。(A semiconductor device and a method of manufacturing the semiconductor device, the method comprising: forming a device isolation layer on a substrate, the device isolation layer defining a plurality of active regions; and forming a plurality of gate lines crossing the active region and buried in the substrate. Forming the gate line includes forming a trench crossing the active region on the substrate; forming a work function control layer on sidewalls and a bottom surface of the trench; forming a conductive layer on the work function control layer; sequentially forming a barrier layer and a source layer on the work function control layer and on the conductive layer, the source layer including a work function control element; and diffusing a work function controlling element from the source layer into an upper portion of the work function controlling layer.)

1. A method of manufacturing a semiconductor device, the method comprising:

forming a device isolation layer on a substrate, the device isolation layer defining a plurality of active regions; and

forming a plurality of gate lines crossing the active regions and buried in the substrate,

wherein forming a gate line among the plurality of gate lines includes:

forming a trench on the substrate, the trench intersecting the active region,

forming a work function control layer on sidewalls and a bottom surface of the trench,

a conductive layer is formed on the work function control layer,

sequentially forming a barrier layer and a source layer on the work function control layer and on the conductive layer, the source layer including a work function control element, an

Diffusing the work function controlling element from the source layer into an upper portion of the work function controlling layer.

2. The method of claim 1, wherein the upper portion of the work function control layer containing the diffused work function control element has a lower work function than a lower portion of the work function control layer.

3. The method of claim 1, wherein the work function control element diffuses through the barrier layer into the work function control layer.

4. The method of claim 3, wherein the blocking layer comprises the workfunction controlling element.

5. The method of claim 1, further comprising forming a gate dielectric pattern on the sidewalls and the bottom surface of the trench prior to forming the work function control layer.

6. The method of claim 5, wherein the blocking layer is disposed between the gate dielectric pattern and the source layer.

7. The method of claim 6, wherein the blocking layer extends from between the gate dielectric pattern and the source layer to between the source layer and each of the work function control layer and the conductive layer.

8. The method of claim 1, wherein a thickness of the barrier layer is greater than a thickness of the work function control layer.

9. The method of claim 1, wherein the barrier layer comprises titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), a metal compound comprising titanium nitride (TiN), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum aluminum carbonitride (TaAlCN), or a metal compound comprising tantalum nitride (TaN).

10. The method of claim 1, wherein the blocking layer comprises the same material as the work function control layer.

11. The method of claim 1, further comprising etching the work function control layer and the conductive layer prior to forming the barrier layer and the source layer, and

wherein a top surface of the work function control layer is coplanar with a top surface of the conductive layer after etching the work function control layer and the conductive layer.

12. The method of claim 11, wherein the barrier layer is formed to contact the top surface of the work function control layer and the top surface of the conductive layer.

13. The method of claim 1, further comprising removing the barrier layer and the source layer on the work function control layer and the conductive layer after diffusing the work function control element.

14. The method of claim 13, wherein removing the barrier layer and the source layer comprises removing a portion of the barrier layer such that a bottom section of the barrier layer remains in contact with a top surface of the work function control layer and a top surface of the conductive layer.

15. The method of claim 14, wherein the remaining bottom section of the barrier layer and the upper portion of the work function control layer comprise the same material and are connected as a single body.

16. A semiconductor device, comprising:

a device isolation layer defining a plurality of active regions of a substrate; and

a plurality of gate lines crossing the active region and buried in the substrate,

wherein a gate line among the plurality of gate lines includes:

a work function control layer covering a sidewall of a lower portion of a trench in the substrate, the trench intersecting the active region, and

a conductive layer on the work function control layer and filling the lower portion of the trench, an

Wherein the work function control layer includes:

a first work function control portion surrounding a side surface of the conductive layer, an

A second work function control portion on the first work function control portion and covering a top surface and a portion of the side surface of the conductive layer.

17. The semiconductor device according to claim 16, wherein a work function of the first work function controlling portion is higher than a work function of the second work function controlling portion.

18. The semiconductor device of claim 16, wherein the second work function control portion of the work function control layer conformally covers an upper portion of the conductive layer.

19. The semiconductor device of claim 16, wherein an uppermost end portion of the first work function control portion is in contact with a lowermost end portion of the second work function control portion.

20. The semiconductor device of claim 16, wherein the first and second work function control portions of the work function control layer comprise a metal or a metal nitride, and

wherein the second work function control portion is doped with a work function control element.

21. The semiconductor device of claim 20, wherein the work function control element comprises one or more of lanthanum (L a), strontium (Sr), antimony (Sb), yttrium (Y), aluminum (Al), tantalum (Ta), hafnium (Hf), iridium (Ir), zirconium (Zr), and magnesium (Mg).

22. The semiconductor device of claim 16, further comprising a gate dielectric pattern in the trench and between the gate line and the substrate.

23. The semiconductor device of claim 16, further comprising a plurality of impurity regions in the active region, wherein the plurality of impurity regions comprises:

a first impurity region between the gate lines; and

a second impurity region between the gate line and the device isolation layer.

24. The semiconductor device of claim 23, further comprising:

a bit line on the substrate and connected to the first impurity region; and

a plurality of capacitors on the substrate and connected to the second impurity region.

25. A method of manufacturing a semiconductor device, the method comprising:

forming a gate dielectric pattern on a bottom surface and a side surface of a trench in a substrate;

forming a gate line on the gate dielectric pattern, the gate line filling a lower portion of the trench and including a conductive layer and a work function control layer surrounding a side surface of the conductive layer;

forming a barrier layer on the exposed inner surface of the gate dielectric pattern and on the gate line;

forming an active layer on the blocking layer, the active layer covering the gate line and including a work function control element; and

diffusing the work function control element from the source layer to an upper portion of the work function control layer such that a work function of the upper portion of the work function control layer is lower than a work function of a lower portion of the work function control layer.

Technical Field

The present inventive concept relates generally to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a buried gate line and a method of manufacturing the same.

Background

Semiconductor devices are important in the electronics industry because semiconductor devices typically have small size and versatility and/or are inexpensive to manufacture. The semiconductor device may be classified into any one of a semiconductor memory device storing logic data, a semiconductor logic device processing an operation of the logic data, and a hybrid semiconductor device having both a memory element and a logic element.

In view of the increasing demand for high-speed electronic products with low power consumption, semiconductor devices embedded in electronic products are generally designed to have high operating speeds and/or low operating voltages. As a result, the semiconductor device becomes more highly integrated, and reliability is reduced. However, with the development of the electronics industry, the demand for high-reliability semiconductor devices increases. Therefore, research efforts have been focused on improving the reliability of semiconductor devices.

Disclosure of Invention

Embodiments of the inventive concept provide a semiconductor device having improved electrical characteristics and a method of manufacturing the semiconductor device.

Some embodiments of the inventive concept provide a method of manufacturing a semiconductor device that reduces manufacturing failures.

Embodiments of the inventive concept provide a method of manufacturing a semiconductor device, the method including: forming a device isolation layer on a substrate, the device isolation layer defining a plurality of active regions; and forming a plurality of gate lines crossing the active region and buried in the substrate. Forming a gate line among the plurality of gate lines may include: forming a trench crossing the active region on the substrate; forming a work function control layer on sidewalls and a bottom surface of the trench; forming a conductive layer on the work function control layer; sequentially forming a barrier layer and a source layer on the work function control layer and on the conductive layer, the source layer including a work function control element; and diffusing a work function controlling element from the source layer into an upper portion of the work function controlling layer.

Embodiments of the inventive concept also provide a semiconductor device including: a device isolation layer defining a plurality of active regions of a substrate; and a plurality of gate lines crossing the active region and buried in the substrate. The gate line among the plurality of gate lines includes: a work function control layer covering a sidewall of a lower portion of a trench in the substrate, the trench intersecting the active region; and a conductive layer on the work function control layer and filling the lower portion of the trench. The work function control layer may include: a first work function control portion surrounding a side surface of the conductive layer; and a second work function control portion on the first work function control portion and covering a part of a side surface and a top surface of the conductive layer.

Embodiments of the inventive concept also provide a method of manufacturing a semiconductor device, the method including: forming a gate dielectric pattern on a bottom surface and a side surface of a trench in a substrate; forming a gate line on the gate dielectric pattern, the gate line filling a lower portion of the trench and including a conductive layer and a work function control layer surrounding a side surface of the conductive layer; forming a barrier layer on the exposed inner surface of the gate dielectric pattern and on the gate line; forming an active layer on the barrier layer, the active layer covering the gate line and including a work function controlling element; and diffusing a work function controlling element from the source layer to an upper portion of the work function control layer such that a work function of the upper portion of the work function control layer is lower than a work function of a lower portion of the work function control layer.

Drawings

Embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

Fig. 1 illustrates a plan view of a semiconductor device according to an embodiment of the inventive concept.

Fig. 2A and 2B illustrate cross-sectional views of the semiconductor device taken along lines I-I 'and II-II' of fig. 1, respectively, according to embodiments of the inventive concept.

Fig. 3A and 3B illustrate cross-sectional views of the semiconductor device taken along lines I-I 'and II-II' of fig. 1, respectively, according to other embodiments of the inventive concept.

Fig. 4A and 4B illustrate cross-sectional views taken along lines I-I 'and II-II' of fig. 1, respectively, illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

Fig. 5A and 5B illustrate cross-sectional views taken along lines I-I 'and II-II' of fig. 1, respectively, illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

Fig. 6A and 6B illustrate cross-sectional views taken along lines I-I 'and II-II' of fig. 1, respectively, illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

Fig. 7A and 7B illustrate cross-sectional views taken along lines I-I 'and II-II' of fig. 1, respectively, illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

Fig. 8A and 8B illustrate cross-sectional views taken along lines I-I 'and II-II' of fig. 1, respectively, illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

Fig. 9A and 9B illustrate cross-sectional views taken along lines I-I 'and II-II' of fig. 1, respectively, illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

Fig. 9C shows an enlarged cross-sectional view of the region a in fig. 9A.

Fig. 10A and 10B illustrate cross-sectional views taken along lines I-I 'and II-II' of fig. 1, respectively, illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

Fig. 11A and 11B illustrate cross-sectional views taken along lines I-I 'and II-II' of fig. 1, respectively, illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

Fig. 12A and 12B illustrate cross-sectional views taken along lines I-I 'and II-II' of fig. 1, respectively, illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

Detailed Description

A semiconductor device and a manufacturing method according to embodiments of the inventive concept will be described below with reference to the accompanying drawings. In this description, like reference numerals may denote like parts.

Fig. 1 illustrates a plan view of a semiconductor device according to an example embodiment of the inventive concepts. Fig. 2A and 2B illustrate cross-sectional views of the semiconductor device taken along lines I-I 'and II-II' of fig. 1, respectively, according to embodiments of the inventive concept. Fig. 3A and 3B illustrate cross-sectional views of the semiconductor device taken along lines I-I 'and II-II' of fig. 1, respectively, according to other embodiments of the inventive concept.

Referring to fig. 1, 2A and 2B, the semiconductor device includes a substrate 100, the substrate 100 having a device isolation layer 110 disposed therein to define an active region 105. The substrate 100 may include a semiconductor substrate. For example, the substrate 100 may be a silicon (Si) substrate, a germanium (Ge) substrate, or a silicon germanium (SiGe) substrate. The active regions 105 may each have a stripe shape having long axes arranged in a third direction S that intersects with the first direction X and the second direction Y perpendicular to each other. The fourth direction Z is perpendicular to the first direction X, the second direction Y, and the third direction S. Fig. 2A shows a cross section of the semiconductor device in the third direction S and the fourth direction Z, and fig. 2B shows a cross section of the semiconductor device in the second direction Y and the fourth direction Z.

A plurality of gate lines 200 are provided in the substrate 100, crossing the active region 105, when viewed in a plan view. The gate line 200 may be a word line. The gate lines 200 extend in the second direction Y, are arranged parallel to each other, and are spaced apart from each other in the first direction X. The gate line 200 may be a buried gate line formed in the substrate 100. For example, the gate line 200 may be disposed in a trench 120 of the substrate 100, the trench 120 extending in the second direction Y and crossing the active region 105. The gate line 200 may partially fill the trench 120. The top surface of the gate line 200 may be at a lower level than the top surface of the substrate 100. In an embodiment of the inventive concept, a lower portion of the gate line 200 has a higher work function, and an upper portion of the gate line 200 has a lower work function. This will be described in further detail below along with the configuration of the gate line 200. The gate line 200 may include a work function control layer 220 and a conductive layer 230.

A conductive layer 230 may be disposed in the trench 120. Conductive layer 230 may partially gap fill trench 120. The conductive layer 230 may include a material having a low resistance. For example, the conductive layer 230 may include a metal such as tungsten (W), titanium (Ti), or tantalum (Ta), or a conductive metal nitride such as tungsten nitride (WN). The conductive layer 230 may reduce the resistance of the gate line 200.

The work function control layer 220 may conformally cover the trench 120 of the substrate 100. For example, the work function control layer 220 may cover the sidewalls and bottom surface of the trench 120. The work function control layer 220 may be interposed between the conductive layer 230 and the inner wall of the trench 120. For example, the work function control layer 220 may separate the conductive layer 230 from the inner wall of the trench 120, and thus, the conductive layer 230 may fill the trench 120 as the conductive layer 230 is disposed on and in contact with the inner surface of the work function control layer 220. Depending on the shapes of the trench 120 and the conductive layer 230, the work function control layer 220 may have a U-shaped cross section. The work function control layer 220 may have a higher resistance than that of the conductive layer 230.

The work function control layer 220 may be a liner layer provided to control the work function of the gate line 200. The work function control layer 220 may have a work function lower than that of the conductive layer 230. As another example, in some embodiments, the work function control layer 220 may have a work function that is the same as or higher than that of the conductive layer 230, although the inventive concept is not limited thereto. The work function control layer 220 may have a first work function control portion 222 and a second work function control portion 224.

The first work function controlling portion 222 may cover a lower portion of the trench 120. The first work function controlling portion 222 may surround a lower portion of the conductive layer 230. The first work function controlling portion 222 may include a nitride of a metallic material, or a metal nitride. The metallic material may include a metal element different from the work function controlling element, as will be described below. For example, the metallic material may include a metal element such as titanium (Ti) or tantalum (Ta). For example, the metal nitride may include titanium nitride (TiN), titanium aluminum nitride (TiAlN), a metal compound including titanium nitride (TiN), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum aluminum carbonitride (TaAlCN), or a metal compound including tantalum nitride (TaN).

The second work function controlling portion 224 may be disposed on the first work function controlling portion 222. That is, the second work function control portion 224 may have a lowermost end portion in contact with an uppermost end portion of the first work function control portion 222. The second work function controlling portion 224 may partially cover an upper portion of the trench 120. The second work function controlling portion 224 may surround an upper portion of the conductive layer 230. The second work function control portion 224 may include a metallic material doped with a work function control element, or may include a metal nitride, i.e., a nitride of the metallic material doped with the work function control element. The metallic material may include a metal element different from the work function controlling element. For example, the metallic material may include a metal element such as titanium (Ti) or tantalum (Ta). For example, the metal nitride may include titanium nitride (TiN), titanium aluminum nitride (TiAlN), a metal compound including titanium nitride (TiN), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum aluminum carbonitride (TaAlCN), or a metal compound including tantalum nitride (TaN).

In this specification, a work function control element may be defined to refer to an element capable of changing a work function of a metal or a metal nitride, for example, the work function control element may include a metal such as one or more of lanthanum (L a), strontium (Sr), antimony (Sb), yttrium (Y), aluminum (Al), tantalum (Ta), hafnium (Hf), iridium (Ir), zirconium (Zr), and magnesium (Mg), however, the work function control element should not be limited to the above example.

According to some embodiments of the inventive concept, a semiconductor device may include a work function control layer 220, the work function control layer 220 having a portion with a lower work function (i.e., a second work function control part 224 on an upper portion of a gate line 200) to reduce a gate induced drain leakage (GID L) current flowing from the upper portion of the gate line 200 toward impurity regions SD1 and SD2, which will be described below.

Further, according to some embodiments of the inventive concept, the work function may be lowered at an upper portion of the gate line 200 to reduce the GID L current, and the work function at a lower portion of the gate line 200 may not be lowered, so that the semiconductor device may maintain a higher threshold voltage at a lower portion of the gate line 200 (i.e., at the first work function control part 222 under which the channel is formed).

As shown in fig. 2A and 2B, the work function control layer 220 and the conductive layer 230 may have their uppermost end portions at the same level. For example, the second work function control part 224 of the work function control layer 220 may have a top surface 224a coplanar with a top surface 230a of the conductive layer 230. A top surface 230a of the conductive layer 230 may be exposed on a top surface 224a of the second work function control part 224 of the work function control layer 220. The top surface 224a of the work function control layer 220 and the top surface 230a of the conductive layer 230 may be located at a level lower than that of the top surface of the substrate 100. Although not shown, the top surface 230a of the conductive layer 230 may be disposed at a higher level than the top surface 224a of the second work function control portion 224. In this case, an upper portion of the conductive layer 230 may protrude beyond the top surface 224a of the second work function control portion 224.

In other embodiments, as shown in fig. 3A and 3B, top surface 224a of second work function control portion 224 of work function control layer 220 may be disposed at a higher level than top surface 230a of conductive layer 230 in which case second work function control portion 224 may have an upper section 2244 extending above top surface 230a of conductive layer 230 and may cover conductive layer 230 down, for example, lower section 2242 of second work function control portion 224 may cover a side surface of conductive layer 230 and upper section 2244 of second work function control portion 224 may cover top surface 230a of conductive layer 230, top surface 230a of conductive layer 230 may not be exposed through upper section 2244 of second work function control portion 224, when lower section 2242 and upper section 2244 of second work function control portion 224 comprise the same material, lower section 2242 and upper section 2244 of second work function control portion 224 may have a continuous configuration and an interface therebetween, for example, lower section 2242 and upper section 2244 of second work function control portion 224 may be connected to lower and upper sections 2244 of gate line 2242, thus, when the lower and upper sections 2242 and upper sections 2244 of second work function control portions of gate lines 230 are connected to lower and upper sections 2242, it is possible to reduce current flow between gate lines, and gate lines, thus, when the lower and upper sections 2242, upper sections 2244 of second work function control portions of gate lines are connected to be described as a, a lower and upper section 2242, a gate line, a gate line, a.

Referring back to fig. 1, 2A, and 2B, the gate dielectric pattern 210 may be interposed between the gate line 200 and the active region 105, and also between the gate line 200 and the device isolation layer 110. The gate dielectric pattern 210 may cover sidewalls and a bottom surface of the trench 120. The gate dielectric pattern 210 may separate the gate line 200 from the substrate 100. For example, the gate dielectric pattern 210 may include one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON).

The first overlay pattern 240 may be disposed on the gate line 200. The first overlay pattern 240 may have a top surface coplanar with the top surface of the substrate 100. For example, the first capping pattern 240 may include one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). Although not shown, in some embodiments, the first capping pattern 240 may have a bottom surface contacting the top surface of the gate dielectric pattern 210 and opposite side surfaces contacting the active region 105 and/or the device isolation layer 110. In embodiments such as shown in fig. 2A, for example, the gate dielectric pattern 210 may extend between the first capping pattern 240 and the active region 105 and/or between the first capping pattern 240 and the device isolation layer 110. The gate dielectric pattern 210 between the first capping pattern 240 and the active region 105 may serve as a buffer to reduce stress between the first capping pattern 240 and the active region 105.

The first and second impurity regions SD1 and SD2 may be disposed in the active region 105 adjacent to opposite side surfaces of the gate line 200. For example, the first impurity region SD1 may be disposed between the gate lines 200, and the second impurity region SD2 may be disposed between the gate lines 200 and the device isolation layer 110. The first and second impurity regions SD1 and SD2 may extend from the top surface of the substrate 100 to the inside of the substrate 100. The first impurity region SD1 and the second impurity region SD2 have a conductivity type different from that of the substrate 100. For example, if the substrate 100 is a P-type, the first and second impurity regions SD1 and SD2 may be an N-type. The first impurity region SD1 and the second impurity region SD2 may correspond to a source region and a drain region, respectively.

The first pad 310 may be disposed on the substrate 100 to be connected to the first impurity region SD 1. The second pad 320 may also be disposed on the substrate 100 to be connected to the second impurity region SD 2. The first and second pads 310 and 320 may include a conductive material, such as a metal or doped polysilicon.

The first interlayer dielectric layer 400 may be disposed on the first and second pads 310 and 320. The first interlayer dielectric layer 400 may include one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). The bit line 510 may be disposed on the first interlayer dielectric layer 400. The bit line 510 may be disposed on the first interlayer dielectric layer 400 in the second interlayer dielectric layer 550. The second interlayer dielectric layer 550 may include one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). The bit line 510 may be connected to a direct contact 520 penetrating the first interlayer dielectric layer 400 and connected to the first pad 310. Bit line 510 and direct contact 520 may include doped semiconductor materials (e.g., doped silicon or doped germanium), conductive metal nitrides (e.g., titanium nitride (TiN) or tantalum nitride (TaN)), metals (e.g., tungsten (W), titanium (Ti), or tantalum (Ta)), and metal-semiconductor compounds (e.g., tungsten silicide (WSi)₂) Cobalt silicide (CoSi) or titanium silicide (TiSi)). A second capping pattern 530 may be disposed on the bit lines 510, and dielectric spacers 540 may cover opposite sidewalls of each bit line 510. The second capping pattern 530 and the dielectric spacer 540 may include one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON).

The buried contact 610 may be disposed on the substrate 100, and may penetrate the first interlayer dielectric layer 400 and the second interlayer dielectric layer 550 and be connected with the second pad 320. Buried contact 610 may include a conductive material, such as a metal or doped silicon. A data storage element may be disposed on the second interlayer dielectric layer 550 to be connected to the buried contact 610. For example, the data storage element may be a capacitor CA. The capacitor CA may include a first electrode 620, a second electrode 640, and a dielectric layer 630 between the first electrode 620 and the second electrode 640. The first electrode 620 may have a cylindrical shape with a closed bottom. The second electrode 640 may be a common electrode that collectively covers the first electrode 620. The first electrode 620 and the second electrode 640 may include doped silicon, metal, or metal compound. The support layer 700 may be disposed between the second electrode 640 and the second interlayer dielectric layer 550. The support layer 700 may abut the outer sidewall of the first electrode 620 to prevent the first electrode 620 from collapsing. The support layer 700 may include a dielectric material. The dielectric layer 630 may extend in one direction to be located between the support layer 700 and the second electrode 640.

The structure shown in fig. 3A and 3B is the same as the structure shown in fig. 2A and 2B, respectively, except that in fig. 3A and 3B the second work function control portion 224 includes an upper section 2244 and a lower section 2242 as previously described. For the sake of brevity, description of the same structure in fig. 3A and 3B as in fig. 2A and 2B is omitted.

Fig. 4A to 12A illustrate cross-sectional views taken along line I-I' of fig. 1, showing a method of manufacturing a semiconductor device according to an embodiment of the inventive concept. Fig. 4B to 12B illustrate cross-sectional views taken along line II-II' of fig. 1, showing a method of manufacturing a semiconductor device according to an embodiment of the inventive concept. Fig. 9C shows an enlarged cross-sectional view showing the region a in fig. 9A.

Referring to fig. 4A and 4B, a device isolation layer 110 is formed in a substrate 100, thereby defining an active region 105. For example, a Shallow Trench Isolation (STI) process may be used to form the device isolation layer 110. The device isolation layer 110 may include one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). The device isolation layer 110 may be formed to extend into the substrate 100.

The second impurity region SD2 is formed in the active region 105 of the substrate 100. An ion implantation process may be employed to form the second impurity region SD 2. For example, the second impurity region SD2 may be a region implanted with N-type dopants.

Referring to fig. 5A and 5B, a mask pattern MP is formed on the substrate 100. The mask pattern MP is formed to have an opening defining an area where a gate line (see 200 of fig. 2A and 2B) will be formed as described below. The mask pattern MP may be a hard mask pattern of silicon nitride (SiNx) or a photoresist pattern. The mask pattern MP may be used as an etch mask to etch the substrate 100 and the device isolation layer 110 to form the trenches 120 having a line shape extending in the second direction Y. The trench 120 may have a bottom surface exposing the device isolation layer 110 and the active region 105.

The gate dielectric pattern 210 may include silicon oxide (SiOx) formed on an exposed surface of the substrate 100 when thermal oxidation is performed, in which case the gate dielectric pattern 210 may be formed on an inner wall of the trench 120, for example, the gate dielectric pattern 210 may conformally cover an inner side (e.g., a sidewall and a bottom surface) of the trench 120. as another example, the gate dielectric pattern 210 may include one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON) formed by low pressure chemical vapor deposition (L PCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), ultra high vacuum chemical vapor deposition (UHV-CVD), or atomic layer deposition (a L D).

Referring to fig. 6A and 6B, a primary work function control layer 205 is formed on the substrate 100, the primary work function control layer 205 may be formed to conformally cover the inside of the trench 120 and the mask pattern MP. the primary work function control layer 205 may be formed using various deposition processes such as Chemical Vapor Deposition (CVD) or atomic layer deposition (a L D), the primary work function control layer 205 may include a nitride of a metallic material, or may include a metal nitride.

Referring to fig. 7A and 7B, a conductive layer 230 is formed in a lower portion of the trench 120 in which the primary work function control layer 205 is covered, for example, a conductive material may be deposited on the entire surface of the substrate 100 on which the primary work function control layer 205 is formed, the conductive material may fill the trench 120, the conductive material may be deposited using various deposition processes such as Chemical Vapor Deposition (CVD) or atomic layer deposition (a L D), the conductive material may be a doped semiconductor material (e.g., doped silicon or doped germanium), a conductive metal nitride (e.g., titanium nitride (TiN) or tantalum nitride (TaN)), a metal (e.g., tungsten (W), titanium (Ti) or tantalum (Ta)), and a metal-semiconductor compound (e.g., tungsten silicide (WSi) or tungsten (Ta))₂) Cobalt silicide (CoSi) or titanium silicide (TiSi)). The deposited conductive material may undergo an etching process to form the conductive layer 230. The etching process may continue until the conductive material has a desired thickness in the trench 120.

The preliminary work function control layer 205 is removed from the mask pattern MP and from the portion of the substrate 100 not covered by the conductive layer 230 to form the work function control layer 220. The work function control layer 220 may be formed to have a top surface at the same level as that of the top surface of the conductive layer 230.

Referring to fig. 8A and 8B, a barrier layer 250 may be formed on the substrate 100, the barrier layer 250 may be formed to conformally cover the gate dielectric pattern 210, the top surface of the work function control layer 220, the top surface of the conductive layer 230, and the mask pattern MP., the barrier layer 250 may be formed to have the same thickness as the work function control layer 220 or a thickness greater than the thickness of the work function control layer 220, the barrier layer 250 may be formed using various deposition processes such as Chemical Vapor Deposition (CVD) or atomic layer deposition (a L D), the barrier layer 250 may include a metallic material or a nitride thereof, the metallic material may include a metal element different from a work function control element to be described below, the work function barrier layer 250 may include the same material as the work function control layer 220, for example, the barrier layer 250 may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), a metal compound including titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (TaAlN), or a metal compound including tantalum nitride (TaAlN) may include the barrier layer 220 or a different material from the work function control layer 220.

The source layer 260 may be formed on the substrate 100, the source layer 260 may be formed to conformally cover the top surface of the barrier layer 250. for example, the barrier layer 250 may be interposed between the gate dielectric pattern 210 and the source layer 260 while extending between the source layer 260 and each of the work function control layer 220 and the conductive layer 230. the source layer 260 may be formed using various deposition processes such as Chemical Vapor Deposition (CVD) or atomic layer deposition (a L D). for example, the source layer 260 may include a work function control element or a compound thereof.

Referring to fig. 9A to 9C, a work function control element is doped in an upper portion of the work function control layer 220, thereby forming a second work function control portion 224. In this case, the first work function controlling part 222 is defined to refer to a lower portion of the work function controlling layer 220, which is not doped with the work function controlling element included in the active layer 260. The second work function control portion 224 may have an effective work function lower than that of the first work function control portion 222. For example, the second work function controlling part 224 may be formed through a diffusion process in which a work function controlling element of the source layer 260 is diffused into an upper portion of the work function controlling layer 220. The diffusion process may cause the work function control element to diffuse from the source layer 260 through the barrier layer 250 into the upper portion of the work function control layer 220 along the arrows shown in fig. 9C. Through the above processes, the gate line 200 may be formed to include the work function control layer 220 and the conductive layer 230, and formed to have a higher work function at a lower portion and a lower work function at an upper portion.

According to some embodiments of the inventive concept, the source layer 260 is separated from the gate dielectric pattern 210 by the barrier layer 250. Accordingly, when the diffusion process is performed to diffuse the work function controlling element, the barrier layer 250 may prevent the gate dielectric pattern 210 from being damaged or affected by the work function controlling element, as compared to the case where the source layer 260 and the gate dielectric pattern 210 are in direct contact.

If the barrier layer 250 is not provided, the source layer 260 will directly contact the top surface of the work function control layer 220 and the work function control element will diffuse through the interface between the source layer 260 and the work function control layer 220. However, the hetero-interface between the source layer 260 and the work function control layer 220 may have a high surface energy and a small area. Therefore, a long and/or high-energy diffusion process will be required to sufficiently diffuse the work function control element into the upper portion of the work function control layer 220, which may damage the components of the semiconductor device.

According to the inventive concept, a wide interface exists between the barrier layer 250 and the source layer 260, and the wide interface facilitates diffusion between different materials. Further, since the work function control layer 220 and the barrier layer 250 include the same or similar materials, a high diffusion rate may be achieved on the narrow top surface 224a of the work function control layer 220. In this sense, the work function control element may be easily diffused into the upper portion of the work function control layer 220.

Referring to fig. 10A and 10B, the blocking layer 250 and the source layer 260 are removed. The removal of the active layer 260 and the blocking layer 250 may expose the top surface 224a of the work function control layer 220 and the top surface 230a of the conductive layer 230. The mask pattern MP is also removed together with the barrier layer 250 and the source layer 260. The removal of the mask pattern MP may expose the top surfaces of the device isolation layer 110 and the active region 105.

In other embodiments, as shown in fig. 11A and 11B, barrier layer 250 includes a bottom section 252 that is not removed but remains. The bottom section 252 of the barrier layer 250 may cover the top surface 230a of the conductive layer 230 and contact the top surface of the work function control layer 220. The bottom section 252 of the barrier layer 250 may include a work function controlling element and have a work function lower than that of the first work function controlling portion 222. When the barrier layer 250 includes the same material as that of the work function control layer 220, or specifically, the same material as that of the second work function control portion 224, the second work function control portion 224 and the bottom section 252 of the barrier layer 250 may have a continuous configuration and an invisible interface therebetween. In this case, the bottom section 252 of the barrier layer 250 may constitute an upper section 2244 of the second work function control portion 224, and a portion of the second work function control portion 224 covering the side surface of the conductive layer 230 may constitute a lower section 2242 of the second work function control portion 224. Alternatively, when the second work function control portion 224 and the barrier layer 250 comprise different materials, a visible interface may be provided between the second work function control portion 224 and the bottom section 252 of the barrier layer 250. When the bottom section 252 of the barrier layer 250 remains without being removed, the work function control layer 220 may have a structure as described with reference to fig. 3A and 3B. An example in which barrier layer 250 does not include bottom section 252 will be described below.

Referring to fig. 12A and 12B, a first overlay pattern 240 is formed in the trench 120. For example, the first cover pattern 240 may be formed by forming a cover layer on the entire surface of the substrate 100 and then performing a planarization process. The first capping pattern 240 may include one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON).

The substrate 100 is subjected to an ion implantation process to form first impurity regions SD1 in active regions 105, each active region 105 being between two adjacent gate lines 200. The first impurity region SD1 may be doped with the same N-type impurity as that of the second impurity region SD 2. The first impurity region SD1 may extend further into the substrate 100 than the second impurity region SD 2.

Referring back to fig. 2A and 2B, the first and second pads 310 and 320 are formed by forming and patterning an impurity-doped polycrystalline silicon layer, an impurity-doped single crystal silicon layer, or a conductive layer on the substrate 100. The first pad 310 is connected to the first impurity region SD1, and the second pad 320 is connected to the second impurity region SD 2. When the first and second pads 310 and 320 include an impurity-doped polycrystalline silicon layer or an impurity-doped single crystal silicon layer, the first and second pads 310 and 320 may be doped with impurities having the same conductivity type as that of the first and second impurity regions SD1 and SD 2.

A first interlayer dielectric layer 400 is formed on the first pad 310 and the second pad 320. The first interlayer dielectric layer 400 may be formed using Chemical Vapor Deposition (CVD) or the like. The first interlayer dielectric layer 400 may include one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). The first interlayer dielectric layer 400 may be partially patterned to form a contact hole defining a region filled with a direct contact 520 to be described later. The first interlayer dielectric layer 400 may be coated with a conductive material filling the contact hole, and a capping layer may be formed on the conductive material. For example, the conductive material may include a conductive material such as a metal or a doped semiconductor. For example, the capping layer may include one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). The capping layer and the conductive material are patterned to form the bit line 510 and a second capping pattern 530 disposed on the bit line 510. A direct contact 520 is formed in the contact hole. A dielectric spacer layer may be conformally deposited on the first inter-level dielectric layer 400 and then anisotropically etched to form dielectric spacers 540 covering opposite sidewalls of each bit line 510. The dielectric spacers 540 may include one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON).

The second interlayer dielectric layer 550 is formed on the first interlayer dielectric layer 400, and then, a planarization process may be performed to expose the top surface of the second cover pattern 530, thereafter, the buried contact 610 is formed to penetrate the second interlayer dielectric layer 550 and the first interlayer dielectric layer 400 and is connected with the second pad 320, the buried contact 610 may include a conductive material such as doped silicon or metal, the support layer 700 is formed on the second interlayer dielectric layer 550, the support layer 700 may include one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), the support layer 700 may be formed using various deposition processes such as Chemical Vapor Deposition (CVD) or atomic layer deposition (a L D), the first electrode 620 is formed to penetrate the support layer 700 and is connected with the buried contact 610, the first electrode 620 is formed in a cylindrical shape having a closed bottom, the dielectric layer 630 is formed to conformally cover the first electrode 620, the second electrode 640 is formed to collectively cover the first electrode 620, the first electrode 620 and the second electrode CA. may include impurity-doped silicon, metal, or metal compounds.

These portions of the work function control layer are formed to have a lower work function, thereby reducing a gate induced drain leakage (GID L) current flowing from the upper portion of the gate line toward the impurity region.

Further, according to some embodiments of the inventive concept, the work function may be lowered at an upper portion of the gate line to reduce the GID L current, while the work function is not lowered at a lower portion of the gate line so that the semiconductor device may maintain a high threshold voltage at a lower portion under which a channel is formed.

In the method of manufacturing a semiconductor device according to some embodiments of the inventive concept, when a diffusion process is performed to diffuse a work function controlling element, the barrier layer may prevent the gate dielectric pattern from being damaged or affected by the work function controlling element, as compared to a case where the source layer directly contacts the gate dielectric pattern.

Furthermore, a wide interface may exist between the barrier layer and the source layer, which facilitates diffusion between the different materials. In addition, a high diffusion rate can be achieved on the narrow top surface of the work function control layer. In this sense, the work function control element can be easily diffused into the upper portion of the work function control layer.

Although the present inventive concept has been described with reference to a few exemplary embodiments, as shown in the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and features of the present inventive concept. Accordingly, the above disclosed embodiments should be considered illustrative and not restrictive.

This application claims priority to korean patent application No. 10-2019-0000912, filed by the korean intellectual property office on 3/1/2019, the entire contents of which are incorporated herein by reference.