阅读说明：本技术 一种集成电路版图功耗优化方法及装置 (Integrated circuit layout power consumption optimization method and device ) 是由 吴玉平 陈岚 张学连 于 2019-01-09 设计创作，主要内容包括：本发明提供一种集成电路版图功耗优化方法及装置,通过集成电路的版图数据,获得具有寄生电容与连线图形对应关系的电路网表,进而进行电路网表的仿真,通过仿真结果中寄生电容产生的功耗,确定出由于金属连线而产生的影响功耗的连线寄生电容,进而,通过电路网表可以确定出该影响功耗的寄生电容对应的金属连线,之后,可以对该金属连线进行功耗优化。该方法中,在集成电路版图设计时,从寄生电容产生的功耗方面进行功耗的优化,实现版图设计层面上的功耗优化,有助于持续降低功耗。(The invention provides an integrated circuit layout power consumption optimization method and device, which are characterized in that a circuit netlist with a corresponding relation between parasitic capacitance and a wiring diagram is obtained through layout data of an integrated circuit, the circuit netlist is simulated, the wiring parasitic capacitance influencing the power consumption due to metal wiring is determined through the power consumption generated by the parasitic capacitance in a simulation result, the metal wiring corresponding to the parasitic capacitance influencing the power consumption can be determined through a circuit netlist, and then the power consumption of the metal wiring can be optimized. In the method, during the layout design of the integrated circuit, the power consumption is optimized from the aspect of the power consumption generated by the parasitic capacitance, so that the power consumption optimization on the layout design level is realized, and the continuous reduction of the power consumption is facilitated.)

1. A method for optimizing power consumption of an integrated circuit layout is characterized by comprising the following steps:

obtaining a circuit netlist of the integrated circuit, which has a corresponding relation between parasitic capacitance and wiring diagram patterns, according to layout data of the integrated circuit;

simulating the circuit netlist, and determining parasitic capacitance which is generated by metal connecting wires and influences power consumption according to a simulation result;

determining a wiring diagram corresponding to the parasitic capacitance influencing the power consumption in the circuit netlist;

and optimizing the power consumption of the corresponding connecting line graph.

2. The method according to claim 1, wherein obtaining a circuit netlist of the integrated circuit including a correspondence between parasitic capacitances and wiring patterns according to layout data of the integrated circuit comprises:

extracting parasitic capacitance from layout data of the integrated circuit;

obtaining a circuit netlist of the integrated circuit;

and corresponding the parasitic capacitance to the position information of the corresponding wiring pattern in the circuit netlist to establish the circuit netlist with the corresponding relation of the parasitic capacitance and the wiring pattern.

3. The method of claim 1, wherein the optimizing the power consumption of the corresponding wiring diagram comprises:

increasing the width of the corresponding connection pattern; alternatively, the first and second electrodes may be,

and increasing the distance of the connecting lines in the corresponding connecting line graph.

4. The method of claim 1, wherein the optimizing the power consumption of the corresponding wiring diagram comprises:

determining an upper layer projection area according to the projection of the corresponding connecting line graph on the upper layer;

and rearranging the wiring diagram in the projection area in other areas.

5. The method of claim 4, further comprising, after said performing a re-layout:

and filling a dummy metal pattern with a non-conductive function in the projection area.

6. The method of claim 5 wherein the dummy metal pattern is a line of equally spaced lines.

7. The method as claimed in claim 6, wherein the dummy metal patterns are used to form air bridge structures, the dummy metal patterns are arranged in an array with equal width and equal spacing, and the arrangement is such that the dummy metal patterns satisfy the arrangement of the maximum air bridge structures.

8. An integrated circuit layout power consumption optimization device, comprising:

the circuit netlist obtaining unit is used for obtaining a circuit netlist of the integrated circuit, which has a corresponding relation between parasitic capacitance and wiring diagram patterns, according to layout data of the integrated circuit;

the power consumption parasitic capacitance determining unit is used for simulating the circuit netlist and determining parasitic capacitance which is generated by metal connecting wires and influences power consumption according to a simulation result;

the wiring graph determining unit is used for determining a corresponding wiring graph of the parasitic capacitance influencing the power consumption in the circuit netlist;

and the power consumption optimization unit is used for optimizing the power consumption of the corresponding connecting line graph.

9. The apparatus according to claim 8, wherein in the circuit netlist obtaining unit, obtaining a circuit netlist including a correspondence between parasitic capacitances and wiring patterns of the integrated circuit according to layout data of the integrated circuit includes:

extracting parasitic capacitance from layout data of the integrated circuit;

obtaining a circuit netlist of the integrated circuit;

and corresponding the parasitic capacitance to the position information of the corresponding wiring pattern in the circuit netlist to establish the circuit netlist with the corresponding relation of the parasitic capacitance and the wiring pattern.

10. The apparatus of claim 8, wherein the power consumption optimizing unit is configured to perform power consumption optimization on the corresponding wiring diagram, and the power consumption optimizing unit comprises: determining an upper layer projection area according to the projection of the corresponding connecting line graph on the upper layer;

re-arranging the wiring diagram in the projection area in other areas;

and filling a dummy metal pattern with a non-conductive function in the projection area.

Technical Field

The invention relates to the field of integrated circuit automatic design, in particular to a method and a device for optimizing integrated circuit layout power consumption.

Background

The power consumption of integrated circuits has always been a focus of attention in integrated circuit design, and the continuous reduction of the power consumption of integrated circuits is a goal of integrated circuit design. At present, when a circuit is designed, the power consumption of the circuit is reduced by adopting methods such as a multi-threshold, multi-voltage island, a power gating technology, a low-power-consumption circuit structure technology or a dynamic voltage and frequency adjusting technology, and the like, which are all used for reducing the power consumption on the design of devices or circuit units, the power consumption caused by parasitic effect gradually becomes a main factor of the power consumption along with the continuous reduction of the process characteristic size, the power consumption is not reduced on the devices, the circuits and the above layers, and a design method capable of further reducing the power consumption needs to be provided.

Disclosure of Invention

In view of this, the present invention provides a method and an apparatus for optimizing power consumption of an integrated circuit layout, which optimize power consumption through a parasitic capacitor to further reduce power consumption of the circuit.

In order to achieve the purpose, the invention has the following technical scheme:

a method for optimizing integrated circuit layout power consumption comprises the following steps:

obtaining a circuit netlist of the integrated circuit, which has a corresponding relation between parasitic capacitance and wiring diagram patterns, according to layout data of the integrated circuit;

simulating the circuit netlist, and determining parasitic capacitance which is generated by metal connecting wires and influences power consumption according to a simulation result;

determining a wiring diagram corresponding to the parasitic capacitance influencing the power consumption in the circuit netlist;

and optimizing the power consumption of the corresponding connecting line graph.

Optionally, the obtaining a circuit netlist including a corresponding relationship between a parasitic capacitance and a wiring diagram of the integrated circuit according to layout data of the integrated circuit includes:

extracting parasitic capacitance from layout data of the integrated circuit;

obtaining a circuit netlist of the integrated circuit;

and corresponding the parasitic capacitance to the position information of the corresponding wiring pattern in the circuit netlist to establish the circuit netlist with the corresponding relation of the parasitic capacitance and the wiring pattern.

Optionally, the optimizing the power consumption of the corresponding wiring diagram includes:

increasing the width of the corresponding connection pattern; alternatively, the first and second electrodes may be,

and increasing the distance of the connecting lines in the corresponding connecting line graph.

Optionally, the optimizing the power consumption of the corresponding wiring diagram includes:

determining an upper layer projection area according to the projection of the corresponding connecting line graph on the upper layer;

and rearranging the wiring diagram in the projection area in other areas.

Optionally, after the performing the re-layout, the method further includes:

and filling a dummy metal pattern with a non-conductive function in the projection area.

Optionally, the dummy metal patterns are lines arranged at equal intervals.

Optionally, the dummy metal patterns are used for forming an air bridge structure, and the dummy metal patterns are arranged in an array with equal width and equal spacing, and the arrangement makes the dummy metal patterns meet the arrangement of the maximum air bridge structure.

An integrated circuit layout power consumption optimization device, comprising:

the circuit netlist obtaining unit is used for obtaining a circuit netlist of the integrated circuit, which has a corresponding relation between parasitic capacitance and wiring diagram patterns, according to layout data of the integrated circuit;

the power consumption parasitic capacitance determining unit is used for simulating the circuit netlist and determining parasitic capacitance which is generated by metal connecting wires and influences power consumption according to a simulation result;

the wiring graph determining unit is used for determining a corresponding wiring graph of the parasitic capacitance influencing the power consumption in the circuit netlist;

and the power consumption optimization unit is used for optimizing the power consumption of the corresponding connecting line graph.

Optionally, in the circuit netlist obtaining unit, the obtaining a circuit netlist including a corresponding relationship between a parasitic capacitance and a wiring diagram of an integrated circuit according to layout data of the integrated circuit includes:

extracting parasitic capacitance from layout data of the integrated circuit;

obtaining a circuit netlist of the integrated circuit;

and corresponding the parasitic capacitance to the position information of the corresponding wiring pattern in the circuit netlist to establish the circuit netlist with the corresponding relation of the parasitic capacitance and the wiring pattern.

Optionally, in the power consumption optimizing unit, the optimizing the power consumption of the corresponding wiring diagram includes: determining an upper layer projection area according to the projection of the corresponding connecting line graph on the upper layer;

re-arranging the wiring diagram in the projection area in other areas;

and filling a dummy metal pattern with a non-conductive function in the projection area.

According to the method and the device for optimizing the layout power consumption of the integrated circuit, provided by the embodiment of the invention, the circuit netlist with the corresponding relation between the parasitic capacitance and the wiring diagram is obtained through the layout data of the integrated circuit, the circuit netlist is simulated, the wiring parasitic capacitance influencing the power consumption due to the metal wiring is determined through the power consumption generated by the parasitic capacitance in the simulation result, the metal wiring corresponding to the parasitic capacitance influencing the power consumption can be determined through the circuit netlist, and then the power consumption of the metal wiring can be optimized. In the method, during the layout design of the integrated circuit, the power consumption is optimized from the aspect of the power consumption generated by the parasitic capacitance, so that the power consumption optimization on the layout design level is realized, and the continuous reduction of the power consumption is facilitated.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a flow chart diagram illustrating a method for optimizing power consumption of an integrated circuit layout according to an embodiment of the invention;

fig. 2 is a schematic structural diagram of an integrated circuit layout power consumption optimization device according to an embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.

As described in the background, power consumption of integrated circuits has been a focus of attention in integrated circuit design, and the continued reduction of power consumption of integrated circuits is a goal of integrated circuit design. At present, when a circuit is designed, the power consumption of the circuit is reduced by adopting methods such as a multi-threshold, multi-voltage island, a power grid control technology, a low-power-consumption circuit structure technology or a dynamic voltage and frequency regulation technology, and the like, but the power consumption is reduced on the design of devices or circuit units, the power consumption caused by parasitic effect gradually becomes a main factor of the power consumption along with the continuous reduction of the process characteristic size, the power consumption is not reduced on the devices, the circuits and the above layers, and a design method capable of further reducing the power consumption needs to be provided.

Therefore, the application provides a method and a device for optimizing the power consumption of an integrated circuit layout, which are used for optimizing the power consumption generated by a parasitic capacitor during the design of the integrated circuit layout, so that the power consumption optimization on the layout design level is realized, and the continuous reduction of the power consumption is facilitated. In order to better understand the technical solutions and technical effects of the present application, specific embodiments will be described in detail below with reference to flowcharts.

Referring to fig. 1, in step S01, a circuit netlist of the integrated circuit having a relationship between parasitic capacitance and wiring diagram is obtained according to layout data of the integrated circuit.

The layout data of the integrated circuit is data describing the position and size of each physical layer graph of the layout, and the graph is a structural graph of devices and connecting lines in the layout on each layer. For the layout of the MOS circuit, an active region pattern, a gate pattern, a source-drain pattern, a contact pattern, a connection pattern, and the like may be included.

In the embodiment of the present application, the circuit netlist further includes, in addition to information about circuit connection, information about parasitic capacitance, where the information about parasitic capacitance corresponds to a wiring diagram, that is, the circuit netlist further includes not only description information about circuit connection, but also a correspondence between parasitic capacitance and the wiring diagram.

In a particular embodiment, the circuit netlist can be obtained by the following method.

First, in step S011, parasitic capacitance is extracted from layout data of an integrated circuit.

The extraction of the parasitic parameters may be performed by a tool, and the parasitic parameters may include parasitic resistance, parasitic capacitance, parasitic inductance, and the like.

Then, in step S012, a circuit netlist of the integrated circuit is obtained.

The circuit netlist is a description mode of the circuit connection condition described in a circuit netlist format accepted by a circuit simulator, and the format may be, for example, a SPICE format, which transmits information on the circuit connection.

Then, in step S013, the parasitic capacitances are mapped to the position information of the corresponding wiring patterns in the circuit netlist to create a circuit netlist having a corresponding relationship between the parasitic capacitances and the wiring patterns.

Because the parasitic capacitance of the wiring pattern is obtained in advance through the layout data, after the circuit netlist is obtained, the wiring pattern in the circuit netlist is mapped with the parasitic capacitance, so that the wiring pattern corresponds to the parasitic capacitance corresponding to the wiring pattern, and therefore the information of the parasitic capacitance is added in the circuit netlist, and further simulation analysis and power consumption analysis are facilitated.

In step S02, the circuit netlist is simulated, and the parasitic capacitance affecting power consumption generated by the metal connection is determined according to the simulation result.

Parasitic capacitance is the undesired electric capacity that the metal connection produced, and when the circuit normally worked, this parasitic capacitance's charge-discharge effect can produce the consumption equally to can make the circuit consumption increase, in the scheme of this application, hope optimizing this part consumption, thereby reduce the consumption of circuit at the domain design stage.

It should be noted that, in the layout data, the metal connection line is represented as a connection line pattern, and the integrated circuit finally manufactured is the metal connection line, and in the simulation process, the power consumption generated by the parasitic capacitance of the actual metal connection line can be reflected from the simulation result.

Specifically, simulation can be performed by using an EDA (electronic Design Automation) tool, a circuit netlist is selected as a simulation object during simulation, simulation excitation is input, a simulation result is output after simulation, and the simulation result contains data of influence of parasitic parameters on circuit performance.

In some embodiments, the influence of the parasitic capacitance of the metal connection line on the power consumption can be determined by comparing the power consumption with the power consumption required for driving the load on the metal connection line without the parasitic capacitance, the ratio of the power consumption without the parasitic capacitance to the power consumption with the parasitic capacitance can be calculated, and when the ratio is greater than a predetermined threshold value, the parasitic capacitance is considered as the parasitic capacitance influencing the power consumption. In other embodiments, the power consumption generated by a predetermined number of parasitic capacitances ranked in the top may be used as the parasitic capacitance affecting the power consumption by ranking the power consumption generated by the parasitic capacitances.

In step S03, a wiring diagram corresponding to the parasitic capacitance affecting the power consumption in the circuit netlist is determined.

Because the circuit netlist with the corresponding relation between the parasitic capacitance and the wiring diagram is obtained, the wiring diagram corresponding to the parasitic capacitance influencing the power consumption, namely the actual position of the physical wiring in the layout can be known through the corresponding relation between the parasitic capacitance and the wiring diagram in the circuit netlist, and the power consumption of the part can be optimized.

In step S04, power consumption optimization is performed on the corresponding wiring diagram.

Before power consumption optimization is carried out, whether the adjustable wiring graph exists can be judged based on the corresponding wiring graph, and if yes, power consumption optimization is continuously carried out on the wiring graph. It can be understood that the power consumption optimization is a process of continuously iterating modification and simulation, the power consumption judgment is carried out by modifying the connection graph, if the condition is not met, the modification is continued until the power consumption requirement is met, and the power consumption optimization of the connection graph is completed. After power consumption optimization, new layout data may be output.

Specifically, when the power consumption of the corresponding connection line pattern is optimized, in some embodiments, the power consumption can be optimized by increasing the width of the corresponding connection line pattern, so that the actual width of the metal connection line can be increased, and the purpose of reducing the power consumption is achieved.

In other embodiments, the power consumption can be optimized by increasing the distance between the corresponding connection line pattern and other connection line patterns, so that the distance between the actual metal connection line and other adjacent metal connection lines can be enlarged, and the purpose of reducing the power consumption is achieved.

In some other embodiments, the optimization may be performed by rearranging the wiring pattern, specifically, the method includes: determining an upper layer projection area according to the projection of the corresponding connecting line graph on the upper layer; and rearranging the wiring diagram in the projection area in other areas. Further, if necessary, the projection area may be filled with a dummy metal pattern having a non-conductive function.

In this embodiment, the corresponding link graphic is projected on the upper layer, and an upper layer projection area is determined, where the upper layer projection area may be greater than, less than, or equal to the area covered by the projection, and may be an area where the upper layer projection area is shrunk or enlarged, so that the upper layer link area associated with the corresponding link graphic can be determined. Furthermore, the wiring patterns in the upper projection area can be re-laid, and in a specific application, the wiring patterns in the upper projection area can be kept without being connected, and the wiring patterns can be used as constraint conditions of layout and wiring to re-lay the original wiring patterns in the area, namely, the layout and wiring of the wiring patterns realizing the same connection can be carried out in other areas. Thus, power consumption due to parasitic capacitance caused by the layout at this point is avoided by the re-layout.

Further, the projection area is filled with a dummy metal pattern having a non-conductive function as needed, and the dummy metal pattern, i.e., dummy pattern (dummy pattern), is not used as a wiring, and is usually disposed for planarization or other needs in the manufacturing process.

In specific application, the dummy metal patterns can be filled according to the space between the corresponding wiring patterns, the dummy metal patterns with the minimum line width can be selected for metal filling of the projection area, and the minimum line width is the minimum width of the metal wiring supported in the design process of the layout. In addition, when filling the dummy metal patterns, an equidistant filling mode can be adopted, that is, the dummy metal patterns are lines arranged at equal intervals.

In a more preferred embodiment, the dummy metal patterns are used for forming air bridge structures, and the dummy metal patterns are arranged in an array with equal width and equal spacing, and the arrangement enables the dummy metal patterns to meet the arrangement of the maximum air bridge structures. Thus, while ensuring the reliability of the integrated circuit, the layout of the air bridge structure as much as possible further reduces the power consumption caused by the parasitic capacitance.

Specifically, to make the dummy metal pattern satisfy the maximum arrangement of the air bridge structures, the parameters of the dummy metal pattern are determined by the following conditions:

Wair*(n+1)+n*Wmetal≤Swire_to_wire；

Wair≤Wair_max；

Wair≥Wair_min；

Wmetal≥Wmetal_min；

wherein, Wmetal is the width of the dummy metal pattern; wmetal _ min is the minimum width of the link pattern; swire _ to _ wire is the width of the projection area on the layout; wair _ max is the maximum width of the air bridge structure; wair _ min is the minimum width of the air bridge structure; n is the number of single-column dummy metal patterns in the projection area; wair is the interval of the dummy metal pattern.

Under the above conditions, the number n of single-line dummy metal patterns, the interval Wair of the dummy metal patterns, and the width Wmetal of the dummy metal patterns are determined so that (n +1) Wair becomes the maximum value. Therefore, the maximum air bridge can be introduced on the premise of ensuring the reliability, so that the power consumption required by charging and discharging of the parasitic capacitor is reduced.

In the process of optimizing power consumption by adjusting the wiring pattern, the symmetry and the matching relation of the adjusted wiring pattern can be ensured to be unchanged, namely the wiring pattern of the matched, symmetrical wire mesh or sub-wire mesh is still kept to be matched, symmetrical wire mesh or sub-wire mesh after being adjusted.

In the method, when the integrated circuit layout is designed, the power consumption is optimized from the aspect of the power consumption generated by the parasitic capacitance, so that the power consumption optimization on the layout design level is realized, and the continuous reduction of the power consumption is facilitated. In addition, the present application further provides an integrated circuit layout power consumption optimization apparatus, as shown in fig. 2, including:

a circuit netlist obtaining unit 100, configured to obtain a circuit netlist of an integrated circuit having a corresponding relationship between a parasitic capacitance and a wiring diagram according to layout data of the integrated circuit;

a power consumption parasitic capacitance determining unit 110, configured to perform simulation on the circuit netlist, and determine a parasitic capacitance affecting power consumption generated by a metal connection according to a simulation result;

a wiring diagram determining unit 120, configured to determine a wiring diagram corresponding to the parasitic capacitance affecting power consumption in the circuit netlist;

and a power consumption optimizing unit 130, configured to perform power consumption optimization on the corresponding wiring diagram.

Further, in the circuit netlist obtaining unit 100, obtaining a circuit netlist including a corresponding relationship between a parasitic capacitance and a wiring diagram of an integrated circuit according to layout data of the integrated circuit includes:

extracting parasitic capacitance from layout data of the integrated circuit;

obtaining a circuit netlist of the integrated circuit;

and corresponding the parasitic capacitance to the position information of the corresponding wiring pattern in the circuit netlist to establish the circuit netlist with the corresponding relation of the parasitic capacitance and the wiring pattern.

Further, in the power consumption optimizing unit 130, the optimizing the power consumption of the corresponding wiring diagram includes:

and increasing the width of the corresponding connecting line pattern.

Further, in the power consumption optimizing unit 130, the optimizing the power consumption of the corresponding wiring diagram includes:

and increasing the distance of the connecting lines in the corresponding connecting line graph.

Further, in the power consumption optimizing unit 130, the optimizing the power consumption of the corresponding wiring diagram includes: determining an upper layer projection area according to the projection of the corresponding connecting line graph on the upper layer;

and rearranging the wiring diagram in the projection area in other areas.

Further, the power consumption optimization unit 130, after the performing the rearrangement, further includes:

and filling a dummy metal pattern with a non-conductive function in the projection area.

Furthermore, the dummy metal patterns are lines arranged at equal intervals.

Furthermore, the dummy metal patterns are used for forming air bridge structures, the dummy metal patterns are arranged in an array with equal width and equal spacing, and the arrangement enables the dummy metal patterns to meet the arrangement of the maximum air bridge structures.

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, it is relatively simple to describe, and reference may be made to some descriptions of the method embodiment for relevant points. The above-described embodiments of the apparatus are merely illustrative, wherein the modules or units described as separate parts may or may not be physically separate, and the parts displayed as modules or units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.

The foregoing is only a preferred embodiment of the present invention, and although the present invention has been disclosed in the preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.