阅读说明：本技术 双集成硅控整流器晶体管和相关方法 (Dual integrated silicon controlled rectifier transistor and related method ) 是由 A·埃拉米库拉萨尼 M·格瑞斯伍尔德 于 2019-12-27 设计创作，主要内容包括：本发明题为“双集成硅控整流器晶体管和相关方法”。本发明提供了一种实施方案,其包括具有复合SCR保护的ESD稳健晶体管。该晶体管可以包括：半导体衬底,该半导体衬底具有第一导电类型；漏极区,该漏极区与半导体衬底耦接,该漏极区具有漏极SCR部件,该漏极SCR部件具有第一导电类型的第一漏极区和第二导电类型的第二漏极区。该晶体管还可以包括：源极,该源极与半导体衬底耦接；沟道区,该沟道区具有第二导电类型；以及栅极,该栅极与沟道区耦接,该栅极具有SCR部件,该SCR部件具有第一导电类型的第一栅极区和第二导电类型的第二栅极区。漏极SCR部件和栅极SCR部件可以沿沟道区产生低电阻放电路径,该低电阻放电路径响应于ESD而激活,使得ESD通过晶体管放电而不损坏晶体管。(The invention provides a dual integrated silicon controlled rectifier transistor and related methods. The present invention provides an embodiment comprising an ESD robust transistor with composite SCR protection. The transistor may include: a semiconductor substrate having a first conductivity type; a drain region coupled with the semiconductor substrate, the drain region having a drain SCR component having a first drain region of a first conductivity type and a second drain region of a second conductivity type. The transistor may further include: a source coupled to the semiconductor substrate; a channel region having a second conductivity type; and a gate coupled to the channel region, the gate having an SCR component with a first gate region of the first conductivity type and a second gate region of the second conductivity type. The drain SCR component and the gate SCR component can create a low resistance discharge path along the channel region that activates in response to ESD such that the ESD discharges through the transistor without damaging the transistor.)

1. An ESD robust transistor with composite SCR protection, the transistor comprising:

a semiconductor substrate having a first conductivity type;

a drain region coupled with the semiconductor substrate, the drain region comprising a drain SCR component comprising a first drain region of the first conductivity type and a second drain region of a second conductivity type;

a source coupled with the semiconductor substrate;

a channel region having the second conductivity type;

a gate coupled with the channel region, the gate including an SCR component,

the SCR component includes a first gate region of the first conductivity type and a second gate region of the second conductivity type; and is

Wherein the drain SCR component and the gate SCR component create a low resistance discharge path along the channel region that activates in response to ESD such that the ESD discharges through the transistor without damaging the transistor.

2. The transistor of claim 1, the transistor comprising a body coupled with the semiconductor substrate and comprising a body SCR component comprising a first body region of the first conductivity type, a second body region of the second conductivity type.

3. The transistor of claim 2, wherein the drain SCR component and the bulk SCR component create a low resistance discharge path along the substrate that activates in response to the ESD such that the ESD discharges through the transistor without damaging the transistor.

4. The transistor of claim 2, wherein the drain SCR component is a common anode along the low resistance discharge path of the channel region and along a low resistance discharge path of the substrate.

5. The transistor of claim 2, comprising a third body region having the first conductivity type.

6. The transistor of claim 5, comprising a metal layer atop two or more of the first, second, and third body regions.

7. The transistor of claim 1, comprising a conductive electrode over the drain region, and wherein the conductive electrode covers a portion of the first drain region and a portion of the second drain region without covering the entire second area.

8. The transistor of claim 1, comprising a conductive electrode above the gate region, and wherein the conductive electrode covers a portion of the first gate region and a portion of the second gate region without covering the entire second region.

9. The transistor of claim 1, comprising a resistor field plate located over the channel region.

10. The transistor of claim 1, wherein the transistor comprises a stadium shape, a circle shape, an oval shape, a horseshoe shape, or a rectangle shape.

11. The transistor of claim 1, wherein the transistor comprises a Junction Field Effect Transistor (JFET) having a voltage rating between 200V and 1500V.

12. The transistor of claim 1, wherein the transistor comprises an electrostatic discharge rating of greater than 4.0kV according to the human body model.

13. The transistor of claim 1, wherein the first conductivity type comprises P-type conductivity.

Background

Semiconductor transistors may experience damage or altered behavior due to electrostatic discharge (ESD). ESD causes damage when charge is accumulated on a body (e.g., a human body, a machine, a packaging container, etc.) which is then in contact with a semiconductor transistor. If the charge built up on the body is discharged into the semiconductor transistor, a large and sudden burst of current flowing into the device may be caused. This current may filar, which may melt the metal, contacts, and semiconductor material as power is dissipated in the form of thermal energy. The location of the melting may cause the device to fail.

There are a variety of models/standards for performing design and testing to prevent transistor failure due to electrostatic discharge. These models/standards include a Human Body Model (HBM), a Charged Device Model (CDM), and a Machine Model (MM). The HBM simulates ESD due to electrical discharge from a human. CDM models the discharge of a charged device as it contacts a conductor. MM simulates the discharge from a non-human source (such as from a production facility or tool) to a device. These models/standards provide a measure of the voltage that a given device is likely to withstand without damage.

The semiconductor transistor may include a shield or other dissipative component to prevent ESD-induced damage. However, these techniques often require additional steps in the manufacturing process, or require adjustments to the design of the semiconductor transistor, which complicates the design and manufacturing process.

Drawings

Fig. 1 is a top view of an embodiment of a semiconductor device on a semiconductor wafer;

FIG. 2 is a schematic diagram of an embodiment of the device of FIG. 1;

FIG. 3 is a cross-sectional side view showing an embodiment of a semiconductor transistor;

FIG. 4 is a schematic diagram showing an embodiment of an SCR circuit for discharging ESD through a semiconductor transistor;

fig. 5 is an enlarged partial cross-sectional view illustrating an embodiment of a drain region of an ESD robust semiconductor transistor;

fig. 6 is an enlarged partial cross-sectional view illustrating an embodiment of a gate region of an ESD robust semiconductor transistor; and is

Fig. 7 is an enlarged partial cross-sectional view illustrating an embodiment of a body region of an ESD robust semiconductor transistor.

Detailed Description

The present invention relates generally to electronic devices and, more particularly, to semiconductor device structures and methods of forming semiconductor devices.

For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. Moreover, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein, current carrying electrode refers to an element of a device that carries current through the device, such as a source or drain of a transistor. Although the devices are explained herein as certain N-type regions and certain P-type regions, it will be understood by those of ordinary skill in the art that the conductivity types may be reversed and are also possible in light of the present description, taking into account any necessary voltage polarity reversal, transistor type and/or current direction reversal, etc. For simplicity of the drawing, certain regions of the device structure (such as doped regions or dielectric regions) may be shown as generally having straight line edges and angularly precise corners. However, those skilled in the art understand that due to diffusion and activation of dopants or formation of layers, the edges of such regions may not typically be straight lines and the corners may not have precise angles. In addition, the term "major surface" when used in connection with a semiconductor region, wafer, or substrate refers to the surface of the semiconductor region, wafer, or substrate that forms an interface with another material, such as a dielectric, insulator, conductor, or polycrystalline semiconductor. The major surface can have topographical features that vary in the x, y, and z directions.

As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Furthermore, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises and/or comprising, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, for example, a first member, a first element, a first region, a first layer, and/or a first section discussed below could be termed a second member, a second element, a second region, a second layer, and/or a second section without departing from the teachings of the present invention.

It will be understood by those skilled in the art that the phrases "during …", "simultaneously at …", and "when …" as used herein in relation to circuit operation do not exactly refer to an action occurring immediately after the action is initiated, but rather to the possible presence of some small but reasonable delay, such as a propagation delay, between reactions initiated by the initial action. Additionally, the term "simultaneously at …" means that some action occurs at least for a period of time during the duration of the initiating action. The words "about," "approximately," or "substantially" are used to indicate that the value of an element is expected to be near the stated value or position. However, it is well known in the art that there are always some minor deviations that prevent a value or position from being exactly the stated value or position. As used herein, unless otherwise specified, the phrases "over …" or "over …" include orientations, placements, or relationships where the specified elements are in direct or indirect physical contact. As used herein, unless otherwise specified, the phrase "overlapping …" includes an orientation, placement, or relationship in which specified elements are capable of at least partial or complete coincidence or alignment in the same plane or in different planes. It should also be understood that the embodiments illustrated and described as appropriate below may lack any elements not expressly disclosed herein and/or may be practiced in the absence of any elements not expressly disclosed herein.

Silicon Controlled Rectifiers (SCRs) are layered power control devices that activate or trigger to enable current to flow along a discharge flow path. At certain (i.e., low) voltages and/or current levels, the SCR is electrically non-existent, thereby allowing current and/or voltage to flow or be applied without impact. However, at other voltages or currents, the SCR "activates," meaning that the resistance in the flow path containing the SCR will drop. The decrease in resistance of the flow path causes any build-up of charge (i.e., during an ESD event) to be rapidly dissipated through the flow path. The flow path in the embodiments described below may also be referred to as a discharge path, which is a path for the flow of current for ESD generated by the SCR.

This specification includes, among other features, a composite SCR architecture consisting of an SCR anode at a drain region of a semiconductor transistor, where a first SCR cathode and a first SCR gate are at a gate region of the semiconductor transistor, and a second alternative or additional SCR cathode and a second SCR gate are at a body region of the semiconductor transistor, or both. These SCR components are added to the structure without otherwise altering the architecture or parametric behavior of the transistors. The composite SCR includes a single architecture with two co-existing SCR devices sharing a common anode terminal. One or more of these SCR devices reduce the resistance of the semiconductor transistor during an ESD event, which reduces the risk of damage and/or defects during an ESD event.

Turning now to the drawings, fig. 1 is a top view of an embodiment of a semiconductor device 10 on a semiconductor wafer 12. The semiconductor wafer 12 may include many semiconductor devices 10 over the entire surface. The semiconductor device 10 may be a junction gate field effect transistor (JFET) having a drain region 14, a gate region 16, a source region 18, and a body region 19. As shown, the device 10 may be stadium shaped, but the device 10 may also include other closed shapes such as circular, horseshoe, oval or rectangular transistors. During an ESD event, a certain amount of energy must be dissipated through the device 10 within a short period of time. This dissipation of energy may cause the electrical behavior of the device to change. For example, the device 10 may have increased leakage current and may be characterized by microscopic damage points along the ESD surge current conduction path 20. As noted above, there are many sources of electrical charge that cause ESD, including contact with the human body, discharge of the charged device itself, or discharge of a tool or production tool in contact with the device 10. The damage point 20 may, for example, include a wire-like fault point at the surface or within the channel region 22 or deeper into the semiconductor wafer 12. As described above, the damage point 20 may cause an undesired transistor operation.

Fig. 2 is a schematic diagram of an embodiment of device 10 of fig. 1, showing internal portions of drain region 14, gate region 16, and body region 19 most relevant to certain embodiments of the present invention. Specifically, the schematic shows the individual SCR components of the architecture of the compound SCR 28: a drain component 30, a gate component 32, and a body component 34 that raise the threshold such that the device 10 is protected from ESD damage when the charge of an ESD event is below the threshold. For example, the threshold of an 800VJFET with a composite SCR 28 architecture can be raised to the HBM rating of 4.0 kV. In certain embodiments, the JFET may include a nominal operating voltage between 200V and 1500V. These embodiments may also have an HBM rating of 4.0 kV. The SCR components 30, 32, 34 of the composite SCR 28 architecture are layers located below the surface of the device 10 and are therefore not visible externally (i.e., in the top view of fig. 1). The embedded layers of the SCR components 30, 32, 34 are also located in regions that do not affect the operation of the semiconductor device 10. Furthermore, the manufacture of the SCR components 30, 32, 34 is performed by adjusting the position and/or duration of steps already present in the manufacture of the semiconductor device 10. Thus, the composite SCR 28 is protected from ESD events without increasing the cost of the design or manufacturing process.

The drain component 30 of the composite SCR 28 includes a first region 30a of a first conductivity type and a second region 30b of a second conductivity type. The ratio between the lateral extensions of the regions 30a/30b may be of such a value that an optimal SCR activation behavior and ESD protection is achieved. Similarly, the gate segment 32 of the composite SCR 28 includes a first region 32a of a first conductivity type and a second region 32b of a second conductivity type. The body section 34 of the composite SCR 28 includes a first region 34a of the second conductivity type, and a second region 34b of the first conductivity type and a third region 34c of the second conductivity type.

Fig. 3 is a cross-sectional side view of an embodiment of a transistor 300. Transistor 300 includes a semiconductor substrate 302. In the illustrated embodiment, the substrate is a P-type (P-doped) substrate, but in other embodiments, other configurations may be used, such as an N-type (N-doped) substrate. Thus, in the illustrated embodiment, the gate/channel/substrate forms a PNP configuration, but in other embodiments this may be configured such that an NPN configuration is formed.

By way of non-limiting example, any number of doping, diffusion, and/or annealing steps, etc., may be used to fabricate configurations of semiconductor substrates (P-type, N-type, etc.) from a silicon substrate. As will be described below, the transistor 300 also includes a drain region, a gate region, a source region, a substrate contact region, or other regions, each of which may have different electrical and/or other properties. The different regions may be formed by any number or combination of masking (photoresist), exposing, etching, cleaning, doping, implanting, diffusing, annealing, and/or other steps using appropriate materials, dopants, and other appropriate materials.

Transistor 300 includes a drain terminal 304, a gate terminal 305, a channel region 308, a source terminal 306, and a body terminal 310. In operation, terminals 304, 305, 306, and 310 may be connected to power contacts that supply or transmit current to transistor 300. Channel region 308 may be an N-channel region. The gate region 312, the source and drain regions 314, 316, and the body region 318 are all coupled to (and in direct contact with, in the embodiment shown) the channel region 308 so that current can flow between the source and drain terminals 306, 304 through the channel region 308 and can be controlled by the gate terminal 305. Each of the drain region 316 (including the SCR component), the gate region 312 (including the SCR component), and the body region 310 (including the SCR component) are depicted in detail in fig. 5, 6, and 7, as labeled in fig. 3, respectively.

During an ESD event, components of a compound SCR (e.g., compound SCR 28) work together as a single structure to dissipate and/or direct energy from the ESD event through transistor 300 without damage (e.g., from damage point 20 of fig. 1). Transistor 300 includes a channel flow path 320 and a substrate flow path 322 that transfer energy from an ESD event through transistor 300. That is, when an ESD event causes the voltage across the SCR device to increase substantially and sharply, the resistance along the channel flow path 320 and the substrate flow path 322 decreases, thereby quickly dissipating the ESD charge.

The ESD discharge paths (i.e., channel discharge path 320 and substrate discharge path 322) are presented schematically in fig. 4, which shows an embodiment of transistor 400. Transistor 400 has a drain terminal 404, a gate terminal 406, a channel 408, a source terminal 410, and a body terminal 430. The operation of transistor 400 causes current to flow through a channel 408 between a source 410 and a drain 404. As described above, a compound SCR (e.g., compound SCR 28) includes two cooperating sets of back-to-back SCR devices 454 that share some components. From an equivalent circuit perspective, the transistor 400 includes a first SCR device 450 that enables the first flow path 420 and a second SCR device 452 that enables the second flow path 422. When a high voltage pulse (i.e., an ESD event) is applied to transistor 400, each SCR device has a potential to "activate". That is, when the SCR devices 450, 452 are activated, the resistance along the first and second flow paths 420, 422 drops significantly. This reduction in resistance not only reduces the power dissipated in the transistor, but also facilitates faster dissipation of power from ESD events and reduces the likelihood of damage to the transistor 400 by reducing the likelihood of filamentation and local self-heating. Each direction through the flow paths 420, 422 (i.e., the radial direction out of the concentrated drain region 14) has a low resistance, and thus the ESD has no momentum to concentrate the current through a single filament. As described above, the first flow path 420 and the second flow path 422 share a common anode with the drain region located near the drain terminal 404.

Fig. 5 is a schematic cross-sectional view of an implementation of a drain region 500 (e.g., drain region 316 of fig. 3, but not necessarily limited to the implementation of fig. 3) of an ESD robust semiconductor transistor with a composite SCR (e.g., transistor 300). The drain region 500 is coupled to a channel region 504 of the first conductivity type over a substrate 502. As shown, the SCR component 506 may include a P + region (P + anode) 508 and an N + region 510. A conductive electrode 512 is placed over the two regions 508, 510 and may be fabricated as a conductive silicide, but in other embodiments it may be formed by siliciding a silicon layer, or may be formed using a metal or another conductive element. The conductive electrode 512 may not always completely cover the P + region 508. Instead, a gap remains that forms and/or becomes the resistive electrical ballast zone (separation layer) 514. The resistive electrical ballast region 514 greatly enhances the ESD robustness of the transistor. As noted above to some extent, the resistive electrical ballast region is a buffer or buffer layer between the gate/source and the drain and helps to improve the robustness of the device against damage caused by ESD.

Although the various regions in the representative example are formed of particular material types, i.e., P-type substrate, N + source regions, P + gate regions, P + substrate contact regions, P + drain regions (P + anodes), N + drain regions, N-channel regions, silicide regions, etc., one of ordinary skill can select other material types and combinations having similar or different electrical or other properties as desired (e.g., starting with an N-type substrate and selecting other material types accordingly). The P + region 508 and the N + region 510 in the drain region 500 may include materials and/or doping that are present during the fabrication of the originally completed design of the transistor. For example, the drain region 500 may be positioned adjacent to a polysilicon resistor field plate 520. The field plate 520 can be designed to have a configuration that produces a desired field with a transistor (e.g., transistor 300). In the embodiment shown in fig. 5, the field plate 520 comprises a flat spiral, which is shown in cross-section as an individualized spot. The spiral resistor field plate 520 may be connected to the drain terminal at one end and to ground at the other end. Other circuit designs may use other configurations. However, the drain SCR component 506 takes up only little space within the drain region 500, so that the design of the rest of the circuit/transistor is hardly affected at all.

Fig. 6 is a schematic cross-sectional view of an embodiment of a gate region 600 (e.g., gate region 312 of fig. 3, but not necessarily limited to the embodiment of fig. 3) of an ESD robust semiconductor transistor with a composite SCR (e.g., transistor 300). The gate region 600 is coupled to an N-channel region 604 above the substrate 602. The gate region 600 may include a shallow p-well region 607 and a deep p-well 605, which together with the channel region function as a reverse bias junction that controls current flow in the channel of the transistor during normal operation of the transistor. The deep p-well 605 may be less heavily doped than the shallow p-well 607. As shown, the SCR component may be embedded over the shallow P-well 607 and include a P + region 608 and an N + region 610. In some embodiments, a conductive electrode 612 is placed over the two P + layers 608 and N + layer 610 in the gate region 600. As with the drain conductive electrode 612, the conductive electrode 612 may include a conductive silicide region, but in other embodiments it may be formed of a metal or another conductive element. The conductive electrode 612 may be coupled to an electrical lead that is used to electrically couple the gate region 600 to an external element or some other device.

In certain embodiments, the shallow p-well 607 may extend only partially under the SCR components 608, 610. Specifically, the shallow p-well 607 may be pulled back a distance 606, which distance 606 may be adjusted to a value to create a resistance along the SCR flow path (e.g., flow path 320 in fig. 3) so that SCR triggering may occur. Additionally or alternatively, the conductive electrode 612 may not completely cover the N + region 610. The gate region 600, like the drain region 500, may be positioned adjacent to other transistor components that are shaped and positioned as part of a particular transistor design. The SCR components 608, 610 occupy only little space within the gate region 600 so that the design of the rest of the circuit/transistor is almost completely unaffected.

Fig. 7 is a schematic cross-sectional view of an implementation of a body region 700 of an ESD robust semiconductor transistor, such as transistor 300. Body region 700 includes two p-well regions 720,724 and an n-well region 704. In normal operation, the body region 700 provides a reference potential (which may be zero volts in some applications) to the substrate 702 through the p-wells 720, 724. However, during an ESD event, one or both of the p-wells (720,724) act as SCR gates, which activate the SCRs to enable ESD energy current to flow from the drain terminal of the transistor to its bulk terminal (e.g., through ESD discharge path 322). In some applications, the three P-regions and the N-region may be electrically connected together via a metal layer on top. Alternatively, either the left p-well region 724 or the right p-well region may be electrically shorted to the N region. The left p-well 724 may also prevent punch-through between the source n-region 708 of the transistor and the n-well component 704 of the SCR during normal operation of the transistor.

As described above, this combination of layers greatly enhances the ESD robustness of a transistor (e.g., transistor 300) when combined with the SCR component described in fig. 5 and 6. As described above, this combination of layers (i.e., the gate regions 607, 608, 610 and the conductive electrode 612 and the body regions 720,724, 704) enhances ESD robustness of the transistor (e.g., the transistor 300) when combined with the SCR component 506 described above. For example, an embodiment of a transistor (e.g., transistor 300) may increase the ESD rating from 1.5kV HBM to 4.0kV HBM by including a composite SCR having either a drain SCR component (e.g., 506) and a gate SCR component (e.g., gate SCR 606) or a bulk SCR component (e.g., 706).

The above components may be provided as steps in the manufacturing process. For example, the semiconductor substrate may be provided as a wafer and may be doped to include a conductivity type (i.e., P-type or N-type doping). The SCR device may be provided by layering and etching a semiconductor material, such as doped silicon. While the present subject matter has been described above in connection with specific preferred and exemplary embodiments, the foregoing drawings, and the description thereof, are intended to depict only typical embodiments of the present subject matter and are not therefore to be considered to limit the scope of the present subject matter. It is evident that many alternatives and modifications will be apparent to those skilled in the art.