阅读说明：本技术 一种基于fpga的多张vpx板卡时间同步方法和装置 (FPGA-based multi-VPX board time synchronization method and device ) 是由 卢峥 邵雨新 张自圃 徐碧辉 陈航 李中 吴昌昊 于 2021-07-23 设计创作，主要内容包括：本发明公开了一种基于FPGA的多张VPX板卡时间同步方法和装置,所述方法包括以下步骤：S1：从以太网芯片中获取时间信息,并把时间信息上传到主卡处理器；在同一时间内,进行同步计时,获得同步时钟；S2：将时间信息和同步时钟通过单端转差分芯片分别转换成差分时间信息和差分同步时钟,再将差分时间信息和差分同步时钟分别转换成第二时间信息和第二同步时钟,再通过本地总线将第二时间信息和第二同步时钟上传给从卡处理器。本发明系统由全国产化器件组成,时间信息的串行传输协议是自主设计的,能够做到传输参数可控；时间信息和同步时钟为差分传输,抗干扰性强；时间信息传输协议为串行传输,可以节约FPGA可用端口。(The invention discloses a method and a device for synchronizing time of multiple VPX board cards based on an FPGA (field programmable gate array), wherein the method comprises the following steps: s1: acquiring time information from the Ethernet chip and uploading the time information to the main card processor; in the same time, synchronous timing is carried out to obtain a synchronous clock; s2: the time information and the synchronous clock are respectively converted into differential time information and a differential synchronous clock through a single-ended-to-differential chip, the differential time information and the differential synchronous clock are respectively converted into second time information and a second synchronous clock, and the second time information and the second synchronous clock are uploaded to a slave card processor through a local bus. The system of the invention is composed of nationwide productized devices, and the serial transmission protocol of the time information is independently designed, so that the transmission parameters can be controlled; the time information and the synchronous clock are transmitted in a differential mode, and the anti-interference performance is strong; the time information transmission protocol is serial transmission, so that the available ports of the FPGA can be saved.)

1. A time synchronization method for multiple VPX board cards based on an FPGA comprises the following steps:

s1: acquiring time information from the Ethernet chip by adopting a main card FPGA chip, and uploading the time information to a main card processor; in the same time, the main card FPGA chip carries out synchronous timing to obtain a synchronous clock;

s2: the master card FPGA chip converts the time information and the synchronous clock into differential time information and a differential synchronous clock through a single-end-to-differential chip respectively, and then transmits the differential time information and the differential synchronous clock to the slave card FPGA chip;

s3: the FPGA chip of the slave card converts the differential time information and the differential synchronous clock into second time information and a second synchronous clock through the differential-to-single-ended chip respectively, and uploads the second time information and the second synchronous clock to the processor of the slave card through a local bus.

2. The FPGA-based time synchronization method for the multiple VPX board cards, according to claim 1, wherein the number of FPGA chips of the main card is 1; the number of the slave card FPGA chips is N, and N is an integer greater than or equal to 2.

3. The method for time synchronization of multiple VPX boards based on FPGA of claim 1, wherein before step S1, the method further comprises the ethernet chip obtaining the time information from the network and storing the time information in a register of the ethernet chip.

4. The method according to claim 1, wherein in step S1, the acquiring the time information from the ethernet chip by using the FPGA chip of the main card and uploading the time information to the processor of the main card specifically comprises: the time information is acquired from the Ethernet chip by adopting the FPGA chip of the main card through a pulse per second signal and an MDIO interface, and is uploaded to the processor of the main card through a local bus protocol.

5. The FPGA-based time synchronization method for multiple VPX board cards is characterized in that a master FPGA chip and a slave FPGA chip are 2V1000 programmable gate arrays.

6. The FPGA-based time synchronization method for multiple VPX board cards according to any one of claims 1 to 4, wherein the Ethernet chip is an AR8031 chip.

7. The FPGA-based time synchronization method for multiple VPX board cards is characterized in that the master card processor and the slave card processor are LSOCAM0201 dual-core ARM processors.

8. A multi-VPX board time synchronization device based on FPGA is based on any one of claims 1-4, and is characterized by comprising the following steps: a master card VPX board card and N slave card VPX board cards, wherein N is an integer greater than or equal to 2;

the main card VPX board is provided with a main card AR8031 chip, a main card FPGA chip, a main card ARM processor and a single-end-to-differential chip;

the slave card VPX board card is provided with a slave card FPGA chip, a slave card ARM processor and a differential-to-single-ended chip;

the main card AR8031 chip is used for acquiring time information from a network and storing the time information in a register of the main card AR8031 chip;

the main card FPGA chip is used for acquiring time information from a register of the main card AR8031 chip and uploading the time information to the main card ARM processor through a local bus protocol; the main card FPGA chip is also used for synchronous timing to obtain a synchronous clock;

the single-end-to-differential chip is used for converting the time information and the synchronous clock into differential time information and a differential synchronous clock respectively and transmitting the differential time information and the differential synchronous clock to the differential-to-single-end-to-differential chip;

the differential-to-single-ended chip is used for converting the differential time information and the differential synchronous clock into second time information and a second synchronous clock respectively;

and the slave card FPGA chip is used for uploading the second time information and the second synchronous clock to the slave card ARM processor through a local bus.

Technical Field

The invention relates to the field of communication, in particular to a method and a device for synchronizing time of multiple VPX board cards based on an FPGA.

Background

In the prior art, the board card time information comes from a processor, the time information is issued through some common fixed protocols, the time information and a synchronous clock are transmitted in a single-ended mode in the transmission process, a time synchronization system is not designed nationally, and the precision of the time information is generally low. The prior art has the following disadvantages: the processor acquires the time information and then issues the time information to the FPGA, so that the transmission delay is increased, and the transmission precision of the time information is reduced; the transmission of the time information and the synchronous clock between the boards is generally realized by GPIO direct connection of FPGA on each board card, and the transmission is single-ended transmission and has poor anti-interference capability; the existing system uses foreign elements to complete system design, is easy to limit, and has low time information precision of only 0.01 second.

Disclosure of Invention

The technical problem to be solved by the invention is that the existing VPX board card processor acquires time information and then sends the time information to the FPGA, so that transmission delay can be increased, transmission precision of the time information and transmission of the time information and a synchronous clock between board cards are generally realized through GPIO direct connection of the FPGA on each board card, the transmission is single-ended, and the anti-interference capability is poor.

The invention is realized by the following technical scheme:

a time synchronization method for multiple VPX board cards based on an FPGA comprises the following steps:

s1: acquiring time information from the Ethernet chip by adopting a main card FPGA chip, and uploading the time information to a main card processor; in the same time, the main card FPGA chip carries out synchronous timing to obtain a synchronous clock;

s2: the master card FPGA chip converts the time information and the synchronous clock into differential time information and a differential synchronous clock through a single-end-to-differential chip respectively, and then transmits the differential time information and the differential synchronous clock to the slave card FPGA chip;

s3: the FPGA chip of the slave card converts the differential time information and the differential synchronous clock into second time information and a second synchronous clock through the differential-to-single-ended chip respectively, and uploads the second time information and the second synchronous clock to the processor of the slave card through a local bus.

The working principle of the invention is as follows: the FPGA chip of the main card directly acquires time information from the Ethernet chip ar8031 through the management data input/output interface MDIO; the time information and the synchronous clock are converted into differential signals through a single-end to differential chip on the FPGA chip of the master card, and the differential signals reach the FPGA chips of the other slave cards and are converted into single-end signals through the differential to single-end chip to be used by the FPGA chips of the slave cards.

Further, the number of the main card FPGA chips is 1; the number of the slave card FPGA chips is N, and N is an integer greater than or equal to 2. Each VPX board card can be selected to serve as a master card or a slave card, only one master card can be arranged in the time synchronization system, and N slave cards can be arranged.

Further, before step S1, the method further includes that the ethernet chip obtains the time information from the network and stores the time information in a register of the ethernet chip.

Further, in step S1, the acquiring the time information from the ethernet chip by using the main card FPGA chip and uploading the time information to the main card processor specifically includes: the time information is acquired from the Ethernet chip by adopting the FPGA chip of the main card through a pulse per second signal and an MDIO interface, and is uploaded to the processor of the main card through a local bus protocol.

Further, the master card FPGA chip and the slave card FPGA chip are both 2V1000 programmable gate arrays.

Further, the ethernet chip is an AR8031 chip.

Further, the master card processor and the slave card processor are LSOCAM0201 dual-core ARM processors.

A time synchronization device for multiple VPX board cards based on FPGA comprises: a master card VPX board card and N slave card VPX board cards, wherein N is an integer greater than or equal to 2;

the main card VPX board is provided with a main card AR8031 chip, a main card FPGA chip, a main card ARM processor and a single-end-to-differential chip;

the slave card VPX board card is provided with a slave card FPGA chip, a slave card ARM processor and a differential-to-single-ended chip;

the main card AR8031 chip is used for acquiring time information from a network and storing the time information in a register of the main card AR8031 chip;

the main card FPGA chip is used for acquiring time information from a register of the main card AR8031 chip and uploading the time information to the main card ARM processor through a local bus protocol; the main card FPGA chip is also used for synchronous timing to obtain a synchronous clock;

the single-end-to-differential chip is used for converting the time information and the synchronous clock into differential time information and a differential synchronous clock respectively and transmitting the differential time information and the differential synchronous clock to the differential-to-single-end-to-differential chip;

the differential-to-single-ended chip is used for converting the differential time information and the differential synchronous clock into second time information and a second synchronous clock respectively;

and the slave card FPGA chip is used for uploading the second time information and the second synchronous clock to the slave card ARM processor through a local bus.

Compared with the prior art, the invention has the following advantages and beneficial effects:

1. according to the method and the device for synchronizing the time of the multiple VPX board cards based on the FPGA, the FPGA chip of the main card directly obtains the time information from the Ethernet chip ar8031 through the management data input/output interface MDIO; the time information and the synchronous clock are converted into differential signals through a single-end to differential chip on the FPGA chip of the master card, and the differential signals reach the FPGA chips of the other slave cards and are converted into single-end signals through the differential to single-end chip to be used by the FPGA chips of the slave cards.

2. According to the method and the device for synchronizing the time of the multiple VPX board cards based on the FPGA, a system is composed of nationwide devices, a serial transmission protocol of time information is designed independently, and transmission parameters can be controlled.

3. According to the method and the device for synchronizing the time of the multiple VPX board cards based on the FPGA, the time information and the synchronous clock are transmitted in a differential mode, and the anti-interference performance is high.

4. According to the method and the device for synchronizing the time of the multiple VPX board cards based on the FPGA, the time information transmission protocol is serial transmission, and the available ports of the FPGA are saved.

Drawings

In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and that for those skilled in the art, other related drawings can be obtained from these drawings without inventive effort. In the drawings:

fig. 1 is a design flow chart of the VPX board time synchronization technology based on the FPGA of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.

Examples

As shown in fig. 1, a method for synchronizing time of multiple VPX board cards based on an FPGA includes the following steps:

s1: the Ethernet chip acquires time information from the network and stores the time information in a register of the Ethernet chip; acquiring time information from an Ethernet chip by adopting a main card FPGA chip through a pulse per second signal and an MDIO interface, and uploading the time information to a main card processor through a local bus protocol; in the same time, the main card FPGA chip carries out synchronous timing to obtain a synchronous clock;

s2: the master card FPGA chip converts the time information and the synchronous clock into differential time information and a differential synchronous clock through a single-end-to-differential chip respectively, and then transmits the differential time information and the differential synchronous clock to the slave card FPGA chip;

s3: the FPGA chip of the slave card converts the differential time information and the differential synchronous clock into second time information and a second synchronous clock through the differential-to-single-ended chip respectively, and uploads the second time information and the second synchronous clock to the processor of the slave card through a local bus.

The number of the main card FPGA chips is 1; the number of the slave card FPGA chips is N, and N is an integer greater than or equal to 2.

In this embodiment, the master card FPGA chip and the slave card FPGA chip both use a 2V1000 programmable gate array. The Ethernet chip adopts an AR8031 chip of thirty-two institute of electrical science. The main card processor and the slave card processor both adopt LSOCAM0201 dual-core ARM processors of the institute of microelectronics of Western Ann.

A time synchronization device for multiple VPX board cards based on FPGA comprises: a master card VPX board card and N slave card VPX board cards, wherein N is an integer greater than or equal to 2;

the main card VPX board is provided with a main card AR8031 chip, a main card FPGA chip, a main card ARM processor and a single-end-to-differential chip;

the slave card VPX board card is provided with a slave card FPGA chip, a slave card ARM processor and a differential-to-single-ended chip;

the main card AR8031 chip is used for acquiring time information from a network and storing the time information in a register of the main card AR8031 chip;

the main card FPGA chip is used for acquiring time information from a register of the main card AR8031 chip and uploading the time information to the main card ARM processor through a local bus protocol; the main card FPGA chip is also used for synchronous timing to obtain a synchronous clock;

the single-end-to-differential chip is used for converting the time information and the synchronous clock into differential time information and a differential synchronous clock respectively and transmitting the differential time information and the differential synchronous clock to the differential-to-single-end-to-differential chip;

the differential-to-single-ended chip is used for converting the differential time information and the differential synchronous clock into second time information and a second synchronous clock respectively;

and the slave card FPGA chip is used for uploading the second time information and the second synchronous clock to the slave card ARM processor through a local bus.

The system work flow defined by the invention is as follows: the AR8031 on the master card acquires time information from a network, the time information is accurate to ns level and is stored in a register of the AR8031, the 2V1000 programmable gate array on the master card acquires the time information from the AR8031 through a Pulse Per Second (PPS) and an MDIO interface and uploads the time information to a master card ARM processor through a local bus protocol, the 2V1000 programmable gate array on the master card sends the time information to other slave cards through a time information sending protocol and carries out synchronous timing (timing precision is 10ns and the same below) locally in the same time, the time information and a synchronous clock are output through GPIO on the master card and are converted into differential transmission through a single-ended differential chip, the anti-interference performance of the transmission is improved, after the slave card receives the differential signal, the differential signal is converted into the single-ended signal through the differential single-ended chip, and after the 2V1000 programmable gate array on the slave card receives the single-ended signal, the time information is obtained through the analysis of the time information receiving protocol, synchronous timing is carried out by using a synchronous clock, and at the same time, the slave card uploads the time information to the processor through the local bus for use. The invention has only one master card, N slave cards, and each card can be used as both the master card and the slave card. The design flow chart is shown in fig. 1.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.