阅读说明：本技术 包括辅助像素的显示装置 (Display device comprising auxiliary pixels ) 是由 金彰穆 韩东垣 于 2020-02-05 设计创作，主要内容包括：提供了一种显示装置。所述显示装置包括包含传感器区域、至少部分地围绕传感器区域的第一非显示区域以及至少部分地围绕第一非显示区域的显示区域的基底。多个辅助像素设置在传感器区域中。多个辅助像素被构造为无源矩阵驱动。多个主像素设置在显示区域中,并被构造为有源矩阵驱动。(A display device is provided. The display device includes a substrate including a sensor region, a first non-display region at least partially surrounding the sensor region, and a display region at least partially surrounding the first non-display region. A plurality of auxiliary pixels are disposed in the sensor region. The plurality of auxiliary pixels are configured to be passive matrix driven. A plurality of main pixels are disposed in the display area and configured for active matrix driving.)

1. A display device, the display device comprising:

a substrate including a sensor area, a first non-display area at least partially surrounding the sensor area, and a display area at least partially surrounding the first non-display area;

a plurality of auxiliary pixels disposed in the sensor region and configured to be passive-matrix driven;

a plurality of main pixels disposed in the display area and configured to be active matrix driven; and

a plurality of auxiliary thin film transistors disposed in the first non-display region and configured to drive the plurality of auxiliary pixels.

2. The display device of claim 1, further comprising a component disposed on a lower surface of the substrate such that the component corresponds to the sensor region.

3. The display device according to claim 1, wherein each of the plurality of auxiliary pixels is located in a region in which a plurality of horizontal electrodes extending substantially in a first direction and a plurality of vertical electrodes extending substantially in a second direction crossing the first direction intersect with each other.

4. The display device according to claim 1, wherein each of the plurality of main pixels comprises at least one thin film transistor.

5. The display device according to claim 1, wherein each of the plurality of auxiliary pixels includes a horizontal electrode, a vertical electrode, and an intermediate layer arranged between the horizontal electrode and the vertical electrode, and

wherein each of the plurality of auxiliary thin film transistors includes a first auxiliary thin film transistor connected to the horizontal electrode and a second auxiliary thin film transistor connected to the vertical electrode.

6. The display device according to claim 5, wherein each of the plurality of main pixels includes a pixel electrode, an intermediate layer, and a counter electrode, and

wherein a source electrode or a drain electrode of the first auxiliary thin film transistor is connected to the counter electrode.

7. The display device according to claim 6, wherein a gate electrode of the second auxiliary thin film transistor is connected to a data line configured to transmit a data signal to the plurality of main pixels.

8. The display device according to claim 5, wherein a source electrode or a drain electrode of the second auxiliary thin film transistor is connected to a driving voltage line in the first non-display region.

9. The display device according to claim 1, further comprising a lower protective film provided on a lower surface of the substrate,

wherein the lower protective film includes an opening corresponding to the sensor region.

10. The display device according to claim 1, further comprising a plurality of lines extending from the display area, arranged in the first non-display area, and detouring along an edge of the sensor area.

11. The display device according to claim 10, wherein each of the plurality of lines includes a curved portion in the first non-display region.

12. The display device according to claim 1, wherein a size of a light-emitting region of each of the plurality of auxiliary pixels is larger than a size of a light-emitting region of each of the plurality of main pixels.

13. The display device of claim 1, wherein the resolution achieved in the sensor region is in the range of 50ppi to 400 ppi.

14. A display device, the display device comprising:

a substrate including a sensor area, a first non-display area at least partially surrounding the sensor area, and a display area at least partially surrounding the first non-display area;

a plurality of auxiliary pixels disposed in the sensor region and configured to be passive-matrix driven;

a plurality of main pixels disposed in the display area and configured to be active matrix driven; and

an assembly under the substrate to correspond to the sensor region.

15. The display device of claim 14, wherein the component is an infrared sensor.

16. The display device according to claim 14, wherein the sensor region has an infrared transmittance of 15% or more.

17. The display device according to claim 14, wherein each of the plurality of auxiliary pixels is located in a region in which a plurality of horizontal electrodes extending substantially in a first direction and a plurality of vertical electrodes extending substantially in a second direction crossing the first direction intersect with each other.

18. The display device according to claim 14, wherein a plurality of auxiliary thin film transistors configured to drive the plurality of auxiliary pixels are arranged in the first non-display region.

19. The display device according to claim 14, further comprising a plurality of lines extending from the display area, arranged in the first non-display area, and detouring along an edge of the sensor area.

20. The display device according to claim 14, further comprising a lower protective film provided on a lower surface of the substrate,

wherein the lower protective film includes an opening corresponding to the sensor region.

Technical Field

The present disclosure relates to a display device, and more particularly, to a display device including auxiliary pixels.

Background

Display devices are widely used in various electronic apparatuses as means for providing information and images to users. Although display devices are traditionally available in rectangular form, modern display devices can have many different shapes and sizes. Furthermore, although display devices have traditionally been used only to display images, modern display devices may contain other input/output devices such as sensors. These sensors are typically disposed within a bezel area of the display device where no image is displayed.

As the bezel area of modern display devices becomes smaller in size, the sensors have been moved to the display area of the display device, where the sensors may appear within cutouts or notches in the display area where no image is displayed. The cut-out or recess may be partially or completely surrounded by the display area of the display device.

Disclosure of Invention

One or more embodiments of the inventive concept may include a display device having a display area and a sensor area. The image may be displayed within a display area. One or more sensors may be disposed within the sensor region. These sensors may be configured to provide additional functionality to the display device.

According to one or more embodiments of the inventive concept, a display device includes a substrate including a sensor region. The first non-display area surrounds the sensor area. The display area at least partially surrounds the first non-display area. A plurality of auxiliary pixels are disposed within the sensor area. The auxiliary pixels are configured to be driven by passive matrix driving. A plurality of main pixels are disposed in the display area. These main pixels are configured to be driven by active matrix driving. A plurality of auxiliary thin film transistors are disposed in the first non-display region. The auxiliary thin film transistors are configured to drive a plurality of auxiliary pixels.

The display device may further include a component disposed on the lower surface of the substrate such that the component corresponds to the sensor region.

The plurality of auxiliary pixels may be located in a region in which a plurality of horizontal electrodes extending substantially in a first direction and a plurality of vertical electrodes extending substantially in a second direction crossing the first direction intersect each other.

Each of the plurality of main pixels may include at least one thin film transistor.

Each of the plurality of auxiliary pixels may include a horizontal electrode, a vertical electrode, and an intermediate layer disposed between the horizontal electrode and the vertical electrode. Each of the plurality of auxiliary thin film transistors may include a first auxiliary thin film transistor connected to the horizontal electrode and a second auxiliary thin film transistor connected to the vertical electrode.

Each of the plurality of main pixels may include a pixel electrode, an intermediate layer, and a counter electrode. The source electrode or the drain electrode of the first auxiliary thin film transistor may be connected to the counter electrode.

The gate electrode of the second auxiliary thin film transistor may be connected to a data line for transmitting a data signal to the plurality of main pixels.

The source electrode or the drain electrode of the second auxiliary thin film transistor may be connected to a driving voltage line located in the first non-display region.

The display device may further include a lower protective film disposed on a lower surface of the substrate, wherein the lower protective film may include an opening corresponding to the sensor region.

The display device may further include a plurality of lines extending from the display area, disposed in the first non-display area, and bypassing along an edge of the sensor area.

Each of the plurality of lines may include a curved portion in the first non-display area.

The size of the light emitting region of each of the plurality of auxiliary pixels may be larger than the size of the light emitting region of each of the plurality of main pixels.

The resolution achieved in the sensor region may be in the range of about 50ppi to about 400 ppi.

According to one or more embodiments of the inventive concept, a display device includes a substrate including a sensor region, a first non-display region at least partially surrounding the sensor region, and a display region at least partially surrounding the first non-display region. A plurality of auxiliary pixels are disposed in the sensor region. The auxiliary pixels are configured to be driven by passive matrix driving. A plurality of main pixels are disposed in the display area. These main pixels are configured to be driven by active matrix driving. The component is disposed under the substrate to correspond to the sensor area.

The component may be a sensor configured to output and/or sense infrared light.

The sensor region may have an infrared transmittance of about 15% or more.

The plurality of auxiliary pixels may be located in a region in which a plurality of horizontal electrodes extending substantially in a first direction and a plurality of vertical electrodes extending substantially in a second direction crossing the first direction intersect each other.

The display device may further include a plurality of auxiliary thin film transistors for driving the plurality of auxiliary pixels. A plurality of auxiliary thin film transistors may be disposed in the first non-display region.

The display device may further include a plurality of lines extending from the display area, disposed in the first non-display area, and bypassing along an edge of the sensor area.

The display device may further include a lower protective film disposed on a lower surface of the substrate, wherein the lower protective film includes an opening corresponding to the sensor region.

Drawings

A more complete understanding of the present disclosure, as well as many additional aspects of the present disclosure, will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a schematic perspective view illustrating a display apparatus according to an exemplary embodiment of the inventive concept;

fig. 2 is a schematic cross-sectional view illustrating a display apparatus according to an exemplary embodiment of the inventive concept;

fig. 3 is a schematic plan view illustrating a display apparatus according to an exemplary embodiment of the inventive concept;

fig. 4A is an equivalent circuit diagram illustrating a pixel configured to be driven by active matrix driving that may be disposed in a display region of a display device according to an exemplary embodiment of the inventive concept;

fig. 4B is an equivalent circuit diagram illustrating a pixel configured to be driven by active matrix driving that may be disposed in a display region of a display device according to an exemplary embodiment of the inventive concept;

fig. 5 is an equivalent circuit diagram illustrating a pixel configured to be driven by passive matrix driving that may be disposed in a sensor region of a display device according to an exemplary embodiment of the inventive concept;

fig. 6 is a schematic plan view illustrating a sensor region and a peripheral region of a display device according to an exemplary embodiment of the inventive concept;

FIG. 7 is a schematic cross-sectional view taken along line I-I' of FIG. 6;

FIG. 8 is a schematic cross-sectional view taken along line II-II' of FIG. 6; and is

Fig. 9 is a schematic plan view illustrating a display device according to an exemplary embodiment of the inventive concept.

Detailed Description

In describing the exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology is employed for the sake of clarity. However, the disclosure is not intended to be limited to the specific terminology so selected, and it is to be understood that each specific element includes all technical equivalents that operate in a similar manner.

Like reference numerals may refer to like elements throughout the specification and drawings. To the extent that a detailed description of some elements has been omitted, it may be assumed that these elements are at least similar to corresponding elements already described elsewhere in the patent application.

It will be understood that, although the terms "first," "second," etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another.

It will be further understood that the terms "comprises" and/or "comprising," and/or variations thereof, are used herein to specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components. However, the phrase "consisting of … …" is intended to exclude the presence of additional features or components.

It will be understood that when a layer, region or component is referred to as being "formed on" another layer, region or component, it can be directly or indirectly formed on the other layer, region or component, and intervening layers, regions or intervening components may be present therebetween.

The size of components in the drawings may be exaggerated for convenience of explanation. While the present invention is not limited to the particular dimensions and thicknesses of the components shown, it will be understood that various structures and relative dimensions and angles of the components may be considered to describe at least particular embodiments of the inventive concept.

It will be appreciated that the particular order of the process steps described herein may be varied from that described. For example, two consecutively described processes may be performed substantially simultaneously, or in reverse order to that described.

Fig. 1 is a schematic perspective view illustrating a display apparatus 1 according to an exemplary embodiment of the inventive concept.

Referring to fig. 1, the display device 1 may include a display area DA emitting light and a non-display area NDA not emitting light. The non-display area NDA may at least partially surround the display area DA, and the non-display area NDA may substantially correspond to a bezel area of the display device 1. A plurality of main pixels Pm driven by an Active Matrix (AM) method may be disposed in the display area DA. The display device 1 can display the main image by using light emitted from the plurality of main pixels Pm arranged in the display area DA.

The display device 1 may include a sensor area SA. The sensor area SA may be entirely disposed within the display area DA so as to form a cutout or hole, or may be disposed on a side edge of the display area DA so as to form a recess. Various electronic components, such as a sensor sensing visible and/or infrared light or a microphone for detecting sound, may be disposed within the sensor area SA.

For example, various electronic components may be provided in the sensor area SA, and the sensor area SA itself may be configured to allow light and/or sound to be transmitted therethrough. In this way, light and/or sound from the outside may penetrate the sensor area SA and be detected by various electronic components therein. According to exemplary embodiments of the inventive concept, when infrared light is transmitted through the sensor area SA, the light transmittance with respect to a wavelength of 940nm may be about 15% or more or 30% or more, and more preferably, 50% or more, 70% or more, 80% or more, 85% or more, or 90% or more.

According to an exemplary embodiment of the inventive concept, the sensor area SA may be configured to provide an image by using light emitted from the auxiliary pixels Pa disposed within the sensor area SA. The auxiliary pixels Pa may be driven by a Passive Matrix (PM) method. The image supplied from the sensor area SA is an auxiliary image having a lower resolution than the image supplied from the display area DA. However, it will be noted that both the display area DA and the sensor area SA may be configured to display an image, and therefore, the sensor area SA may be less conspicuous than a corresponding sensor area that does not include the auxiliary pixel Pa. In this way, the sensor area SA does not appear as a cut or notch, but rather can be difficult to observe.

The sensor area SA may be at least partially surrounded by the display area DA, and fig. 1 shows, as an example, that the sensor area SA is completely surrounded by the display area DA. The non-display area NDA may include a first non-display area NDA1 at least partially surrounding the sensor area SA and a second non-display area NDA2 at least partially surrounding the outside of the display area DA. For example, the first non-display area NDA1 may completely surround the sensor area SA, the display area DA may completely surround the first non-display area NDA1, and the second non-display area NDA2 may completely surround the display area DA. Although any of these elements need not be completely surrounded and/or completely surrounded, in a case where the sensor area SA is disposed on an outer edge of the display area DA, the first non-display area NDA1 may partially surround the sensor area SA, the display area DA may partially surround the first non-display area NDA1, and the second non-display area NDA2 may partially surround the display area DA.

In the following description, an organic light emitting display device is described as an example of the display device 1 shown in fig. 1, but the display device of the present disclosure is not limited thereto. According to exemplary embodiments of the inventive concept, various types of display devices, such as an inorganic light Emitting (EL) display device or a quantum dot light emitting display device, may be used.

Although fig. 1 shows that the sensor area SA is located at one side (upper right side) of the display area DA and that the display area DA is rectangular, the present disclosure is not limited thereto. The shape of the display area DA may be a circle, an ellipse, or a polygon such as a triangle or a pentagon, and the position of the sensor area SA may be variously changed.

Fig. 2 is a schematic cross-sectional view of the display apparatus 1 according to an exemplary embodiment of the inventive concept, which may correspond to a cross-section taken along line a-a' of fig. 1.

Referring to fig. 2, the display device 1 may include a display panel 10 including various display elements and a component 20 corresponding to the sensor area SA.

The display panel 10 may include a substrate 100, a display element layer 200 disposed on the substrate 100, and a thin film encapsulation layer 300 as a sealing member for sealing the display element layer 200. In addition, the display panel 10 may further include a lower protective film 175 disposed under the substrate 100.

The substrate 100 may include glass or polymer resin. The polymer resin may include Polyethersulfone (PES), polyacrylate, Polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, Polyimide (PI), Polycarbonate (PC), and/or Cellulose Acetate Propionate (CAP). The substrate 100 including the polymer resin may have flexible, rollable, and/or bendable characteristics. The substrate 100 may have a multi-layer structure including a layer having the polymer resin described above and an inorganic layer.

As used herein, the term "flexible" means capable of being flexed to a non-trivial degree and returned to its original configuration without cracking or breaking. Similarly, "rollable" means capable of being rolled to a nontrivial degree and returned to its original configuration without cracking or breaking. Similarly, "bendable" means capable of bending to a non-trivial degree and returning to its original configuration without splitting or breaking. By "non-trivial degree" is understood a degree of significant deformation.

The display element layer 200 may include a circuit layer including a main thin film transistor TFT and an auxiliary thin film transistor TFT ', a main organic light emitting diode OLED and an auxiliary organic light emitting diode OLED' as display elements, and an insulating layer IL disposed between the main thin film transistor TFT and the auxiliary thin film transistor TFT 'and the main organic light emitting diode OLED and the auxiliary organic light emitting diode OLED'.

The main thin film transistor TFT and the main organic light emitting diode OLED connected thereto may be disposed in the display area DA. The auxiliary thin film transistor TFT' and some word lines WL of the display element layer 200 may be disposed in the first non-display region NDA 1. The auxiliary organic light emitting diode OLED' may be disposed in the sensor area SA. The auxiliary thin film transistor TFT 'may be a Passive Matrix (PM) driven thin film transistor for the auxiliary organic light emitting diode OLED' disposed in the sensor area SA. The auxiliary thin film transistor TFT' is disposed in the first non-display area NDA1, but does not overlap the assembly 20.

The assembly 20 may be arranged in the sensor area SA. The component 20 may be an electronic component for detecting and/or projecting light and/or sound. For example, the component 20 may be a sensor for receiving and using light (such as an infrared sensor), a sensor for measuring a distance or recognizing a fingerprint by outputting and detecting light or sound, a compact lamp for outputting light, or a speaker for outputting sound. For an electronic component using light, light of various wavelength bands such as visible light, infrared light, or ultraviolet light may be used. A plurality of components may be provided as the components 20 disposed in the sensor area SA. For example, a light emitting device and a light receiving device may be provided together as the assembly 20 in the sensor region SA.

The thin film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In this regard, fig. 2 shows a first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330 with an organic encapsulation layer 320 disposed therebetween.

The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include at least one inorganic insulating material such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon nitride, and/or silicon oxynitride. The organic encapsulation layer 320 may include a polymer-based material. The polymeric material may include acrylic, epoxy, polyimide, and/or polyethylene.

The lower protective film 175 may be attached to the lower surface of the substrate 100 to support and protect the substrate 100. The lower protective film 175 may include an opening 175OP corresponding to the sensor area SA. Since the opening 175OP is provided in the lower protective film 175, the light transmittance of the sensor area SA can be increased. The lower protective film 175 may include PET or PI.

When the substrate 100 includes glass, the lower protective film 175 may be omitted.

Constituent elements such as an input detecting member for detecting a touch input, an anti-reflection member including a polarizer, a retarder or a color filter and a black matrix, and a transparent window may be further provided on the display panel 10.

According to exemplary embodiments of the inventive concept, although it is illustrated that the thin film encapsulation layer 300 is used as an encapsulation member for sealing the display element layer 200, the present disclosure is not limited thereto. For example, a sealing substrate connected to the substrate 100 by a sealant or a frit may be used as a member for sealing the display element layer 200.

Fig. 3 is a schematic plan view illustrating the display apparatus 1 according to an exemplary embodiment of the inventive concept.

Referring to fig. 3, the display panel 10 may include a plurality of main pixels Pm configured to be driven by Active Matrix (AM) driving. The main pixel Pm is disposed in the display area DA. Each of the main pixels Pm may include a display element such as an organic light emitting diode. Each main pixel Pm may emit light of, for example, red, green, blue, or white by the display element. In this specification, as described above, each of the main pixels Pm may be understood as a pixel that emits light of one color of red, green, blue, and white. The display area DA may be covered by the encapsulation member described above with respect to fig. 2, and thus may be protected from external air or moisture.

The sensor area SA may be disposed inside the display area DA, and a plurality of auxiliary pixels Pa configured for PM driving may be disposed in the sensor area SA. Each of the auxiliary pixels Pa may include a display element such as an organic light emitting diode. Each of the auxiliary pixels Pa may emit light of, for example, red, green, blue, or white through the display element. In this specification, as described above, the auxiliary pixel Pa may be understood as a pixel that emits light of one color of red, green, blue, and white.

The diameter of the sensor area SA may range from about 2mm to about 5mm, and the resolution of the sensor area SA may range from about 50 pixels per inch (ppi) to about 400 ppi. The number of auxiliary pixels (i.e., pixels including sub-pixels of RGB) Pa to be included in the sensor area SA may be about 100 of rows including 10 pixels by columns of 10 pixels.

The sensor area SA may have a transmittance of about 15% to 50% or more with respect to light such as infrared light, and components such as a sensor using infrared light may be disposed therein.

The first non-display area NDA1 in which the pixels Pm and Pa are not disposed is located between the sensor area SA and the display area DA. An auxiliary thin film transistor TFT' for driving the auxiliary pixel Pa disposed in the sensor area SA may be disposed in the first non-display area NDA 1. In addition, a line for applying a signal or power to the main pixel Pm separated with respect to the sensor region SA may be disposed in the first non-display region NDA 1. The structure thereof is presented below with reference to fig. 6.

Each of the pixels Pm and Pa may be electrically connected to an external circuit disposed in the non-display area NDA (e.g., the second non-display area NDA 2). The first scan driving circuit 110, the second scan driving circuit 120, the terminal 140, the data driving circuit 150, the first power line 160, and the second power line 170 may be disposed in the second non-display area NDA 2.

The first scan driving circuit 110 may supply a scan signal Sn to each of the main pixels Pm via the scan line SL (see fig. 4A). The first scan driving circuit 110 may supply an emission control signal to each of the main pixels Pm via an emission control line EL. The second scan driving circuit 120 may be disposed in parallel with the first scan driving circuit 110, and the display area DA is located between the second scan driving circuit 120 and the first scan driving circuit 110. Although some of the main pixels Pm disposed in the display area DA may be electrically connected to the first scan driving circuit 110, other main pixels Pm may be electrically connected to the second scan driving circuit 120. According to an exemplary embodiment of the inventive concept, the second scan driving circuit 120 may be omitted.

The terminal 140 may be disposed at one side of the substrate 100. The terminal 140 may be electrically connected to the printed circuit board PCB without being covered by the insulating layer IL. The terminals PCB-P of the PCB may be electrically connected to the terminals 140 of the display panel 10. The PCB is configured to transmit signals or power from the controller to the display panel 10. The control signal generated by the controller may be transmitted to each of the first and second scan driving circuits 110 and 120 via the PCB. The controller may supply the first power voltage ELVDD (see fig. 4A and 4B) and the second power voltage ELVSS (or common voltage ELVSS) to the first power line 160 and the second power line 170 via the first connection line 161 and the second connection line 171 (see fig. 4A and 4B). The first power voltage ELVDD may be supplied to each of the main pixels Pm via the driving voltage line PL connected to the first power line 160, and the second power voltage ELVSS may be supplied to the counter electrode of each of the main pixels Pm connected to the second power line 170.

The data driving circuit 150 may be electrically connected to the data lines DL. The data signal of the data driving circuit 150 may be supplied to each of the main pixels Pm via a connection line 151 connected to the terminal 140 and a data line DL connected to the connection line 151. Although fig. 3 shows that the data driving circuit 150 is disposed on the PCB, the data driving circuit 150 may be disposed on the substrate 100. For example, the data driving circuit 150 may be disposed between the terminal 140 and the first power line 160.

The first power line 160 may include first and second sub-lines 162 and 163 extending substantially in parallel along the x-direction, and the display area DA is disposed between the first and second sub-lines 162 and 163. The second power line 170 may have a ring shape with one side open, and may partially surround the display area DA.

The first and second scan driving circuits 110 and 120 and the data driving circuit 150 may supply signals or voltages to drive the auxiliary pixels Pa. In addition, the first power voltage ELVDD and the second power voltage ELVSS may be transmitted to the auxiliary pixels Pa. In some exemplary embodiments of the inventive concept, lines for transmitting signals of the first and second scan driving circuits 110 and 120 and the data driving circuit 150 may be connected to the auxiliary thin film transistor TFT' to drive the auxiliary pixel Pa. In some exemplary embodiments of the inventive concept, the first and second scan driving circuits 110 and 120 and the data driving circuit 150 may directly supply voltages to drive the auxiliary pixels Pa.

According to an exemplary embodiment of the inventive concept, the main pixels Pm disposed in the display area DA are configured to be driven by AM driving, and the auxiliary pixels Pa disposed in the sensor area SA are configured to be driven by Pm driving. The driving of the main pixel Pm and the driving of the auxiliary pixel Pa are described with reference to fig. 4A and 4B.

Fig. 4A and 4B are equivalent circuit diagrams of an exemplary main pixel Pm of the display panel 10 according to an exemplary embodiment of the inventive concept.

Referring to fig. 4A, each of the main pixels Pm may include a pixel circuit PC connected to the scan line SL and the data line DL and a main organic light emitting diode OLED connected to the pixel circuit PC.

The pixel circuit PC may include a driving thin film transistor T1, a switching thin film transistor T2, and a storage capacitor Cst. The switching thin film transistor T2 is connected to the scan line SL and the data line DL, and transmits a data signal Dm input through the data line DL to the driving thin film transistor T1 in response to a scan signal Sn input through the scan line SL.

The storage capacitor Cst is connected to the switching thin film transistor T2 and the driving voltage line PL, and stores a voltage corresponding to a difference between the voltage received from the switching thin film transistor T2 and the first power voltage (or driving voltage) ELVDD supplied to the driving voltage line PL.

The driving thin film transistor T1 is connected to the driving voltage line PL and the storage capacitor Cst, and may control a driving current flowing in the main organic light emitting diode OLED from the driving voltage line PL in response to a voltage value stored in the storage capacitor Cst. The main organic light emitting diode OLED may emit light having a desired luminance as controlled by the driving current.

Although fig. 4A shows that the pixel circuit PC includes two thin film transistors and one storage capacitor, the present disclosure is not limited thereto. As shown in fig. 4B, the pixel circuit PC may include seven thin film transistors and one storage capacitor.

Referring to fig. 4B, each of the main pixels Pm may include a pixel circuit PC and a main organic light emitting diode OLED connected to the pixel circuit PC. The pixel circuit PC may include a plurality of thin film transistors and a storage capacitor. The thin film transistor and the storage capacitor may be connected to the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL.

Although fig. 4B shows that each of the main pixels Pm is connected to the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL, the present disclosure is not limited thereto. According to an exemplary embodiment of the inventive concept, at least one of the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL may be shared by adjacent pixels.

The plurality of thin film transistors may include a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initialization thin film transistor T4, an operation control thin film transistor T5, an emission control thin film transistor T6, and a second initialization thin film transistor T7.

The signal lines may include a scan line SL for transmitting a scan signal Sn, a previous scan line SL-1 for transmitting a previous scan signal Sn-1 to the first and second initializing thin film transistors T4 and T7, an emission control line EL for transmitting an emission control signal En to the operation controlling thin film transistor T5 and the emission controlling thin film transistor T6, and a data line DL for transmitting a data signal Dm and crossing the scan line SL. The driving voltage line PL transfers the driving voltage ELVDD to the driving thin film transistor T1, and the initialization voltage line VL transfers an initialization voltage Vint for initializing the driving thin film transistor T1 and the pixel electrode.

The driving gate electrode G1 of the driving thin film transistor T1 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst. The driving source electrode S1 of the driving thin film transistor T1 is connected to the driving voltage line PL thereunder via the operation controlling thin film transistor T5. The driving drain electrode D1 of the driving thin film transistor T1 is electrically connected to the pixel electrode of the main organic light emitting diode OLED via the emission controlling thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm according to the switching operation of the switching thin film transistor T2 and supplies a driving current I to the main organic light emitting diode OLED_OLED。

The switching gate electrode G2 of the switching thin film transistor T2 is connected to the scan line SL. The switching source electrode S2 of the switching thin film transistor T2 is connected to the data line DL. The switching drain electrode D2 of the switching thin film transistor T2 is connected to the driving source electrode S1 of the driving thin film transistor T1 and to the driving voltage line PL via the operation control thin film transistor T5. The switching thin film transistor T2 is turned on in response to a scan signal Sn received through the scan line SL, and performs a switching operation of transmitting a data signal Dm received through the data line DL to the driving source electrode S1 of the driving thin film transistor T1.

The compensation gate electrode G3 of the compensation thin film transistor T3 is connected to the scan line SL. The compensation source electrode S3 of the compensation thin film transistor T3 is connected to the driving drain electrode D1 of the driving thin film transistor T1, and is connected to the pixel electrode of the main organic light emitting diode OLED via the emission control thin film transistor T6. The compensation drain electrode D3 of the compensation thin film transistor T3 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, and is connected to the first initialization drain electrode D4 of the first initialization thin film transistor T4 and the driving gate electrode G1 of the driving thin film transistor T1. The compensation thin film transistor T3 is turned on in response to the scan signal Sn received through the scan line SL and electrically connects the driving gate electrode G1 and the driving drain electrode D1 of the driving thin film transistor T1, thereby diode-connecting the driving thin film transistor T1.

The first initializing gate electrode G4 of the first initializing thin film transistor T4 is connected to the previous scan line SL-1. The first initializing source electrode S4 of the first initializing thin film transistor T4 is connected to the second initializing drain electrode D7 of the second initializing thin film transistor T7 and to an initializing voltage line VL. The first initializing drain electrode D4 of the first initializing thin film transistor T4 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the compensating drain electrode D3 of the compensating thin film transistor T3, and the driving gate electrode G1 of the driving thin film transistor T1. The first initializing thin film transistor T4 is turned on in response to the previous scan signal Sn-1 received through the previous scan line SL-1 and transmits an initializing voltage Vint to the driving gate electrode G1 of the driving thin film transistor T1, thereby performing an initializing operation to initialize the voltage of the driving gate electrode G1 of the driving thin film transistor T1.

The operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the emission control line EL. The operation control source electrode S5 of the operation control thin film transistor T5 is connected to the driving voltage line PL thereunder. The operation control drain electrode D5 of the operation control thin film transistor T5 is connected to the driving source electrode S1 of the driving thin film transistor T1 and the switching drain electrode D2 of the switching thin film transistor T2.

The emission control gate electrode G6 of the emission control thin film transistor T6 is connected to the emission control line EL. The emission control source electrode S6 of the emission control thin film transistor T6 is connected to the driving drain electrode D1 of the driving thin film transistor T1 and the compensation source electrode S3 of the compensation thin film transistor T3. The emission control drain electrode D6 of the emission control thin film transistor T6 is electrically connected to the second initialization source electrode S7 of the second initialization thin film transistor T7 and to the pixel electrode of the main organic light emitting diode OLED.

When the operation control thin film transistor T5 and the emission control thin film transistor T6 are simultaneously turned on in response to the emission control signal En received through the emission control line EL, the operation control thin film transistor T5 and the emission control thin film transistor T6 transmit the driving voltage ELVDD to the main organic light emitting diode OLED, thereby allowing the driving current I to flow_OLEDFlows in the main organic light emitting diode OLED.

The second initializing gate electrode G7 of the second initializing thin film transistor T7 is connected to the previous scanning line SL-1. The second initializing source electrode S7 of the second initializing thin film transistor T7 is connected to the emission controlling drain electrode D6 of the emission controlling thin film transistor T6 and to the pixel electrode of the main organic light emitting diode OLED. The second initializing drain electrode D7 of the second initializing thin film transistor T7 is connected to the first initializing source electrode S4 and the initializing voltage line VL of the first initializing thin film transistor T4. The second initializing thin film transistor T7 is turned on in response to the previous scan signal Sn-1 received through the previous scan line SL-1 and initializes the pixel electrode of the main organic light emitting diode OLED.

Although fig. 4B illustrates that the first and second initializing thin film transistors T4 and T7 are connected to the previous scan line SL-1, the present disclosure is not limited thereto. According to an exemplary embodiment of the inventive concept, the first initializing thin film transistor T4 is connected to the previous scan line SL-1 and driven by the previous scan signal Sn-1, and the second initializing thin film transistor T7 is connected to a separate signal line (e.g., a next scan line) and driven by a signal transmitted through the signal line.

The second storage capacitor plate Cst2 of the storage capacitor Cst is connected to the driving voltage line PL. The counter electrode of the main organic light emitting diode OLED is connected to a voltage line transmitting the common voltage ELVSS. Accordingly, the main organic light emitting diode OLED may receive the driving current I from the driving thin film transistor T1_OLEDAnd emits light accordingly to display an image.

Although fig. 4B shows that the compensation thin film transistor T3 and the first initialization thin film transistor T4 have double gate electrodes, the compensation thin film transistor T3 and the first initialization thin film transistor T4 may have one gate electrode.

As such, each of the main pixels Pm configured for the AM driving includes at least one thin film transistor, so that each of the main pixels Pm can be controlled by at least one thin film transistor. The main pixel Pm driven by the AM driving method can realize high resolution with low power consumption.

Fig. 5 illustrates an arrangement of the auxiliary pixels Pa according to an exemplary embodiment of the inventive concept.

Referring to fig. 5, the auxiliary pixels Pa configured to be driven by PM driving do not include a thin film transistor driving each of the auxiliary pixels Pa. The auxiliary pixel Pa for the PM drive configuration may be formed by a plurality of vertical electrodes V1, …, Vn extending substantially in the y direction and a plurality of horizontal electrodes H1, …, Hn extending substantially in the x direction intersecting each other. The vertical electrodes V1, …, Vn may constitute a portion of the pixel electrode of each of the auxiliary organic light emitting diodes OLED'. The horizontal electrodes H1, …, Hn may constitute a part of the counter electrode of each of the auxiliary organic light emitting diodes OLED'. An intermediate layer including an organic light emitting layer is disposed between the vertical electrodes V1, …, Vn and the horizontal electrodes H1, …, Hn. The auxiliary pixel Pa may emit light based on a voltage difference between the vertical electrodes V1, …, Vn and the horizontal electrodes H1, …, Hn.

The horizontal electrodes H1, …, Hn and the vertical electrodes V1, …, Vn may be connected to the auxiliary thin film transistor TFT' or the driving circuit unit to drive the auxiliary pixel Pa. Accordingly, after sequentially selecting the horizontal electrodes H1, …, Hn, an image may be realized by supplying voltages to the vertical electrodes V1, …, Vn included in the auxiliary pixels Pa that emit light.

According to an exemplary embodiment of the inventive concept, components such as sensors may be disposed under the substrate 100 to correspond to the sensor areas SA. The assembly may include a transmitting unit that emits light (e.g., infrared light at a wavelength of 940 nm). When the thin film transistor is disposed in the sensor region SA, the performance of the thin film transistor may become unstable, for example, a photocurrent flows or a driving range is changed by light emitted from the component.

According to an exemplary embodiment of the inventive concept, the auxiliary pixels Pa constructed for PM driving are disposed in the sensor area SA in which the thin film transistor is not disposed. The sensor area SA in which the sensor can be disposed can simultaneously provide an image.

Fig. 6 is a schematic plan view illustrating a sensor region SA and a peripheral region thereof according to an exemplary embodiment of the inventive concept. Fig. 7 is a schematic sectional view taken along line I-I' of fig. 6. Fig. 8 is a schematic sectional view taken along line II-II' of fig. 6.

Referring to fig. 6, horizontal electrodes H1, …, Hn extending substantially in the x direction and vertical electrodes V1, …, Vn extending substantially in the y direction are disposed in the sensor region SA and intersect each other. A plurality of intersection points at which the horizontal electrodes H1, …, Hn and the vertical electrodes V1, …, Vn intersect with each other may be implemented as the auxiliary pixels Pa.

Although fig. 6 illustrates that the area of one of the auxiliary pixels Pa is greater than the area of one of the main pixels Pm, the present disclosure is not limited thereto. When the horizontal electrodes H1, …, Hn and the vertical electrodes V1, …, Vn are relatively small, as a result, the area of one of the auxiliary pixels Pa may be smaller than the area of one of the main pixels Pm. When the width of the horizontal electrodes H1, …, Hn and/or the width of the vertical electrodes V1, …, Vn is decreased, such a decrease may increase the light transmittance of the sensor area SA.

An auxiliary thin film transistor TFT' for assisting the driving of the pixel Pa may be disposed in the first non-display area NDA1 surrounding the sensor area SA. The auxiliary thin film transistor TFT' may include a plurality of first auxiliary thin film transistors TFTa connected to the horizontal electrodes H1, …, Hn and a plurality of second auxiliary thin film transistors TFTb connected to the vertical electrodes V1, …, Vn. Although fig. 6 illustrates that the first auxiliary thin film transistor TFTa is located at the left side of the sensor area SA and the second auxiliary thin film transistor TFTb is located at the lower side of the sensor area SA, the present disclosure is not limited thereto. For example, various modifications are possible such that the first auxiliary thin film transistor TFTa may be located at the right side of the sensor area SA and the second auxiliary thin film transistor TFTb may be located at the upper side of the sensor area SA.

The first auxiliary thin film transistor TFTa may be connected to the scan line SL extending from the display area DA to receive a scan signal. The second power voltage ELVSS may be supplied to the horizontal electrodes H1, …, Hn in response to the scan signal. In some exemplary embodiments of the inventive concept, the scan line SL may be connected to the main pixels Pm disposed in the display area DA. In some exemplary embodiments of the inventive concept, the scan line SL may correspond to any one of the scan line SL connected to the main pixel Pm, the previous scan line SL-1, and the emission control line EL. However, the present disclosure is not limited thereto. The scan line SL connected to the first auxiliary thin film transistor TFTa may be a line which is not connected to the main pixel Pm and is directly connected to the first scan driving circuit 110 (see fig. 3) and the second scan driving circuit 120 (see fig. 3).

A gate electrode of the first auxiliary thin film transistor TFTa is connected to a scan line SL for transmitting a scan signal. A source electrode or a drain electrode of the first auxiliary thin film transistor TFTa may be connected to a counter electrode included in the main pixel Pm, and the other electrode may be connected to the horizontal electrodes H1, …, Hn. In response to the scan signal, the first auxiliary thin film transistor TFTa is turned on, and thus the second power voltage ELVSS applied to the counter electrode included in the main pixel Pm may be transmitted to the horizontal electrodes H1, …, Hn.

The second auxiliary thin film transistor TFTb may be connected to the data line DL extending from the display area DA to receive a data signal. In response to the data signal, the first power voltage ELVDD may be supplied to the vertical electrodes V1, …, Vn. In some exemplary embodiments of the inventive concept, the data line DL may be connected to the main pixel Pm disposed in the display area DA. However, the present disclosure is not limited thereto. The data line DL connected to the second auxiliary thin film transistor TFTb may be a line that is not connected to the main pixel Pm and is directly connected to the data driving circuit 150 (see fig. 3).

The gate electrode of the second auxiliary thin film transistor TFTb may be connected to the data line DL for transmitting a data signal. A source electrode or a drain electrode of the second auxiliary thin film transistor TFTb may be connected to the driving voltage line PL, and the other electrode may be connected to the vertical electrodes V1, …, Vn. In response to the data signal, the second auxiliary thin film transistor TFTb is turned on, and thus the first power voltage ELVDD supplied through the driving voltage line PL may be transferred to the vertical electrodes V1, …, Vn.

A plurality of lines may be disposed in the first non-display area NDA 1. The data line DL may extend substantially in the y direction, and the driving voltage line PL may also extend substantially in the y direction. The driving voltage line PL around the sensor area SA may be short-circuited with respect to the sensor area SA. The shorted driving voltage line PL at the upper side of the sensor region SA may be connected to the second sub line 163 described above with reference to fig. 3, and the shorted driving voltage line PL at the lower side of the sensor region SA may be connected to the first sub line 162. Some of the driving voltage lines PL may be connected to the second auxiliary thin film transistor TFTb.

Some of the data lines DL may bypass the sensor area SA. For example, each of the data lines DL may include a portion extending substantially in the y-direction and a portion detouring along an edge of the sensor area SA by detouring around the sensor area SA. The detour portion of each of the data lines DL may be located in the first non-display area NDA 1. Some of the data lines DL disposed at the lower side of the sensor area SA may be connected to the second auxiliary thin film transistor TFTb. Some of the data lines DL may be disposed between the data lines DL connected to the second auxiliary thin film transistor TFTb without being connected to the second auxiliary thin film transistor TFTb. This may be because the resolution of the display area DA and the resolution of the sensor area SA are implemented to be different from each other. For example, the resolution of the display area DA may be implemented to be higher than that of the sensor area SA.

The main pixels Pm disposed at the upper and lower sides of the sensor area SA may be electrically connected to the data lines DL bypassing the sensor area SA, and may receive signals from the data lines DL corresponding thereto. Some of the data lines DL may be bent along a left edge of the sensor area SA, and other data lines DL may be bent along a right edge of the sensor area SA.

The scan lines SL may extend in an x direction intersecting the data lines DL. Some of the scan lines SL may bypass the sensor area SA. For example, some of the scan lines SL may be bent along an upper edge of the sensor area SA, and other scan lines SL may be bent along a lower edge of the sensor area SA. Each of the scan lines SL may include a portion extending from the display area DA substantially in the x-direction and a portion or a bent portion that bypasses the sensor area SA by bypassing the sensor area SA in the first non-display area NDA 1. The main pixels Pm located at the left and right sides of the sensor area SA may be electrically connected to the scan lines SL bypassing the sensor area SA.

Some of the scan lines SL disposed at the left side of the sensor area SA may be connected to the first auxiliary thin film transistor TFTa. Some of the scan lines SL may be disposed between the scan lines SL connected to the first auxiliary thin film transistors TFTa without being connected to the first auxiliary thin film transistors TFTa. This may be because the resolution of the display area DA and the resolution of the sensor area SA are implemented to be different from each other. For example, the resolution of the display area DA may be implemented to be higher than that of the sensor area SA.

A stack structure of the display device 1 according to an exemplary embodiment of the inventive concept is described with reference to fig. 7 and 8.

The substrate 100 may include a glass material, a ceramic material, a metal material, and/or a material having flexible or bendable characteristics. When the substrate 100 has flexible or bendable characteristics, the substrate 100 may include a polymer resin such as PES, PAR, PEI, PEN, PET, PPS, polyarylate, PI, PC, and/or CAP. The substrate 100 may have a single-layer structure or a multi-layer structure of the material. For multilayer structures, the substrate 100 may also include inorganic layers. In some exemplary embodiments of the inventive concept, the substrate 100 may have a structure of organic material/inorganic material/organic material.

The buffer layer 111 may be disposed on the substrate 100, and may reduce or prevent intrusion of foreign substances, moisture, or external air from a lower portion of the substrate 100 and provide a planarized surface on the substrate 100. The buffer layer 111 may include an inorganic material such as an oxide or a nitride, an organic material, or an organic/inorganic composite, and may have a single-layer structure or a multi-layer structure of the inorganic material and the organic material.

A barrier layer may also be disposed between the substrate 100 and the buffer layer 111. The barrier layer may prevent or reduce intrusion of impurities from the substrate 100 into the semiconductor layers a1, AA2, and AA 3. The barrier layer may include an inorganic material such as an oxide or a nitride, an organic material, or an organic/inorganic composite, and may have a single-layer structure or a multi-layer structure of an inorganic material and an organic material.

The substrate 100 may be divided into a display area DA, a first non-display area NDA1, and a sensor area SA. A main thin film transistor TFT for driving the main pixel Pm may be disposed in the display area DA. An auxiliary thin film transistor TFT' for driving the auxiliary pixel Pa may be disposed in the first non-display area NDA 1.

The semiconductor layers a1, AA2, and AA3 may be disposed on the buffer layer 111. The semiconductor layers a1, AA2, and AA3 may include amorphous silicon or polycrystalline silicon. According to example embodiments of the inventive concepts, the semiconductor layers a1, AA2, and AA3 may include oxides of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and/or zinc (Zn). In some exemplary embodiments of the inventive concept, the semiconductor layers a1, AA2, and AA3 may include a Zn oxide-based material (e.g., Zn oxide, In-Zn oxide, or Ga-In-Zn oxide). According to example embodiments of the inventive concept, the semiconductor layers a1, AA2, and AA3 may each include an IGZO (In-Ga-Zn-O), ITZO (In-Sn-Zn-O), and/or IGTZO (In-Ga-Sn-Zn-O) semiconductor In which a metal such as In, Ga, and/or Sn is included In ZnO. The semiconductor layers a1, AA2, and AA3 may include a channel region, a source region, and a drain region. The source region and the drain region are disposed at opposite sides of the channel region. The semiconductor layers a1, AA2, and AA3 may be configured as a single layer or a multilayer.

Gate electrodes G1, GG2, and GG3 are disposed on the semiconductor layers a1, AA2, and AA3, at least partially overlapping the semiconductor layers a1, AA2, and AA3, and the first gate insulating layer 112 is interposed between the gate electrodes G1, GG2, and GG3 and the semiconductor layers a1, AA2, and AA 3. The gate electrodes G1, GG2, and GG3 may each include molybdenum (Mo), aluminum (Al), copper (Cu), and/or titanium (Ti), and may be formed in a single layer or a multilayer. As an example, the gate electrodes G1, GG2, and GG3 may each be formed in a single layer of Mo. The scan line SL may include the same material as that of the gate electrodes G1, GG2, and GG3 and be on the same layer as the gate electrodes G1, GG2, and GG 3.

The first gate insulating layer 112 may include silicon oxide (SiO)₂) Silicon nitride (SiN)_x) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Titanium oxide (TiO)₂) Tantalum oxide (Ta)₂O₅) Hafnium oxide (HfO)₂) Or zinc oxide (ZnO)₂)。

The second gate insulating layer 113 may cover the gate electrodes G1, GG2, and GG3 and the scan line SL. The second gate insulating layer 113 may include SiO₂、SiN_x、SiON、Al₂O₃、TiO₂、Ta₂O₅、HfO₂Or ZnO₂。

The first storage capacitor plate Cst1 of the storage capacitor Cst disposed in the display area DA may at least partially overlap the TFT. For example, the gate electrode G1 of the TFT may perform a function of the first storage capacitor plate Cst1 as the storage capacitor Cst.

The second storage capacitor plate Cst2 of the storage capacitor Cst overlaps at least partially with the first storage capacitor plate Cst1, and the second gate insulating layer 113 is located between the second storage capacitor plate Cst2 and the first storage capacitor plate Cst 1. In this case, the second gate insulating layer 113 may function as a dielectric layer of the storage capacitor Cst. The second storage capacitor plate Cst2 may include a conductive material including Mo, Al, Cu, and/or Ti, and may be formed to include multiple layers or a single layer of the above materials. As an example, the second storage capacitor plate Cst2 may be a single layer of Mo or a multilayer of Mo/Al/Mo.

Although fig. 7 illustrates that the storage capacitor Cst overlaps the TFT, the present disclosure is not limited thereto. In this regard, various modifications may be available, for example, the storage capacitor Cst may be disposed not to overlap with the TFT.

The interlayer insulating layer 115 may cover the second storage capacitor plate Cst2 of the storage capacitor Cst. The interlayer insulating layer 115 may include SiO₂、SiN_x、SiON、Al₂O₃、TiO₂、Ta₂O₅、HfO₂And/or ZnO₂。

The source electrodes S1, SS2, and SS3, the drain electrodes D1, DD2, and DD3, the data line DL, and the driving voltage line PL may be disposed on the interlayer insulating layer 115. The source electrodes S1, SS2, and SS3, the drain electrodes D1, DD2, and DD3, the data line DL, and the driving voltage line PL may include a conductive material including Mo, Al, Cu, and/or Ti, and may be a multi-layer or a single layer including the above materials. As an example, the source electrodes S1, SS2, and SS3 and the drain electrodes D1, DD2, and DD3 may have a multilayer structure of Ti/Al/Ti.

The via layer 117 may be disposed on the source electrodes S1, SS2, and SS3, the drain electrodes D1, DD2, and DD3, the data lines DL, and the driving voltage lines PL. The main organic light emitting diode OLED and the auxiliary organic light emitting diode OLED' may be disposed on the via hole layer 117.

The via layer 117 may have a flat upper surface so that the pixel electrode 210 is flat. The via layer 117 may be a film formed of an organic material as a single layer or a plurality of layers. The via layer 117 may include general-purpose polymers for general purposes, such as benzocyclobutene (BCB), polyimide, Hexamethyldisiloxane (HMDSO), Polymethylmethacrylate (PMMA), or Polystyrene (PS), polymer derivatives having a phenol group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluoropolymers, p-xylene polymers, vinyl alcohol polymers, or blends thereof. The via layer 117 may comprise an inorganic material. The via layer 117 may comprise SiO₂、SiN_x、SiON、Al₂O₃、TiO₂、Ta₂O₅、HfO₂Or ZnO₂. When the via layer 117 includes an inorganic material, chemical planarization polishing may be performed in some cases. The via layer 117 may include both organic and inorganic materials.

In the display area DA of the substrate 100, the main organic light emitting diode OLED is disposed on the via layer 117. The main organic light emitting diode OLED may include a pixel electrode 210, an intermediate layer 220 including an organic light emitting layer, and a counter electrode 230.

In the sensor region SA of the substrate 100, the auxiliary organic light emitting diode OLED' is disposed on the via layer 117. The auxiliary organic light emitting diode OLED' may include a vertical electrode V1, an intermediate layer 220 including an organic light emitting layer, and a horizontal electrode H1.

The pixel electrode 210 and the vertical electrodes V1 and V2 may be disposed on the same layer and may include the same material. The pixel electrode 210 and the vertical electrodes V1 and V2 may be (semi-) transmissive electrodes or reflective electrodes. In some embodiments, the pixel electrode 210 and the vertical electrodes V1 and V2 may include a conductive layer includingAg. A reflective film of Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr and/or mixtures thereof, and a transparent or translucent electrode layer formed on the reflective film. The transparent or semitransparent electrode layer may include materials such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), zinc oxide (ZnO), indium oxide (In)₂O₃) Oxides of Indium Gallium Oxide (IGO) and/or Aluminum Zinc Oxide (AZO). In some embodiments, the pixel electrode 210 and the vertical electrodes V1 and V2 may have a stacked structure of ITO/Ag/ITO. However, the present disclosure is not limited thereto.

In another exemplary embodiment, the vertical electrodes V1 and V2 may be disposed on a different layer from the pixel electrode 210 and may include different materials. In this regard, various modifications may be available, for example, the vertical electrodes V1 and V2 may include only a transparent electrode layer to improve translucency compared to the pixel electrode 210.

The pixel defining film 119 may be disposed on the via layer 117. The pixel defining film 119 may have a main opening portion (e.g., a main opening portion 119OPm exposing at least a central portion of the pixel electrode 210) corresponding to each of the pixel electrodes 210 in the display area DA, thereby defining a light emitting area of the main pixel Pm. The pixel defining film 119 may have an auxiliary opening portion 119OPa exposing a portion of the vertical electrode V1 corresponding to each of the auxiliary pixels Pa in the sensor area SA, thereby defining a light emitting area of the auxiliary pixel Pa.

The width Wm of the main opening portion 119OPm may be smaller than the width Wa of the auxiliary opening portion 119OPa (Wm < Wa). This is because the resolution of the main pixels Pm disposed in the display area DA is greater than the resolution of the auxiliary pixels Pa disposed in the sensor area SA.

In addition, the pixel defining film 119 may prevent an arc from being formed at the edge of the pixel electrode 210 by increasing a distance between the edge of the pixel electrode 210 and the counter electrode 230 above the pixel electrode 210. The pixel defining film 119 may include an organic insulating material such as polyimide, polyamide, acrylic resin, BCB, HMDSO, and/or phenol resin by a method such as spin coating.

The intermediate layer 220 of the main and auxiliary organic light emitting diodes OLED and OLED' may include an organic light emitting layer. The organic light emitting layer may include an organic material including a fluorescent material or a phosphorescent material emitting light of red, green, blue, or white. The organic light emitting layer may include a low molecular organic material or a polymer organic material. Functional layers such as a Hole Transport Layer (HTL), a Hole Injection Layer (HIL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL) may also be selectively disposed under and over the organic light emitting layer. The intermediate layer 220 may be disposed to correspond to each of the main opening portion 119OPm and the auxiliary opening portion 119OPa of the pixel defining film 119. However, the present disclosure is not limited thereto. In this regard, various modifications may be available, for example, the intermediate layer 220 may comprise an integral layer across the substrate 100.

The counter electrode 230 and the horizontal electrodes H1, Hn-1, and Hn may include the same material as each other and may be disposed on the same layer. The counter electrode 230 and the horizontal electrodes H1, Hn-1, and Hn may be transmissive electrodes or reflective electrodes. In some exemplary embodiments of the inventive concept, the counter electrode 230 and the horizontal electrodes H1, Hn-1, and Hn may each be a transparent or semi-transparent electrode, and may be formed as a metal thin film having a low work function and including Li, Ca, LiF/Al, Ag, Mg, and/or a mixture thereof. Further, such as ITO, IZO, ZnO and/or In₂O₃The Transparent Conductive Oxide (TCO) film of (a) may also be disposed on the metal thin film.

The counter electrode 230 may be disposed across the display area DA and on the intermediate layer 220 and the pixel defining film 119. The counter electrode 230 may be integrally formed with respect to the main organic light emitting diode OLED to correspond to the pixel electrode 210. Horizontal electrodes H1, Hn-1, and Hn may be spaced apart from each other in sensor region SA and may also be spaced apart from counter electrode 230.

When the pixel electrode 210 is set as a reflective electrode and the counter electrode 230 is set as a transmissive electrode, light emitted from the intermediate layer 220 is emitted toward the counter electrode 230, and thus the display apparatus 1 may be implemented as a top emission type. When the pixel electrode 210 is provided as a transparent or semi-transparent electrode and the counter electrode 230 is provided as a reflective electrode, light emitted from the intermediate layer 220 is emitted toward the substrate 100, and thus the display apparatus 1 may be implemented as a bottom emission type. However, the present disclosure is not limited thereto, and the display device 1 according to the present embodiment may be implemented as a dual emission type that emits light in both directions of the top surface and the bottom surface.

The first auxiliary thin film transistor TFTa may include a semiconductor layer AA2, a gate electrode GG2, a source electrode SS2, and a drain electrode DD 2. The gate electrode GG2 of the first auxiliary thin film transistor TFTa may be electrically connected to the scan line SL and may receive application of a scan signal.

The source electrode SS2 of the first auxiliary thin film transistor TFTa may be electrically connected to the counter electrode 230. For example, the source electrode SS2 of the first auxiliary thin film transistor TFTa may be connected to the counter electrode 230 via a via hole penetrating the pixel defining film 119 and the via hole layer 117. In this state, the first connection electrode CM1 may be provided as an intermediate element. For example, the counter electrode 230 may be connected to the first connection electrode CM1 via a via hole defined in the pixel defining film 119, and the first connection electrode CM1 may be connected to the source electrode SS2 via a via hole defined in the via layer 117.

The drain electrode DD2 of the first auxiliary thin film transistor TFTa may be electrically connected to the horizontal electrode H1. For example, the drain electrode DD2 of the first auxiliary thin film transistor TFTa may be connected to the horizontal electrode H1 via a via hole penetrating the pixel defining film 119 and the via hole layer 117. In this state, the second connection electrode CM2 may be provided as an intermediate element. For example, the counter electrode 230 may be connected to the second connection electrode CM2 via a via hole defined in the pixel defining film 119, and the second connection electrode CM2 may be connected to the drain electrode DD2 via a via hole defined in the via layer 117.

The first auxiliary thin film transistor TFTa may transmit the second power voltage ELVSS applied to the counter electrode 230 to the horizontal electrode H1 in response to a scan signal applied to the gate electrode GG 2.

The second auxiliary thin film transistor TFTb may include a semiconductor layer AA3, a gate electrode GG3, a source electrode SS3, and a drain electrode DD 3. The gate electrode GG3 of the second auxiliary thin film transistor TFTb may be electrically connected to the data line DL, and may receive application of a data signal.

The source electrode SS3 of the second auxiliary thin film transistor TFTb may be connected to the driving voltage line PL. The source electrode SS3 may be provided as part of the driving voltage line PL.

The drain electrode DD3 of the second auxiliary thin film transistor TFTb may be electrically connected to the vertical electrode V1. For example, the drain electrode DD3 of the second auxiliary thin film transistor TFTb may be connected to the vertical electrode V1 via a via hole penetrating through the orifice layer 117.

The second auxiliary thin film transistor TFTb may transfer the first power voltage ELVDD transferred through the driving voltage line PL to the vertical electrode V1 in response to the data signal applied to the gate electrode GG 3.

The lower protective film 175 may be disposed on the lower surface of the substrate 100. The lower protective film 175 may include a protective film base 173 and an adhesive layer 180. The protective film base 173 may be attached to the lower surface of the substrate 100 by an adhesive layer 180.

The protective film substrate 173 may include PET and/or PI. The adhesive layer 180 may include a Pressure Sensitive Adhesive (PSA).

The lower protective film 175 may include an opening 175OP corresponding to the sensor area SA, and components arranged to correspond to the sensor area SA may be at least partially disposed in the opening 175 OP.

A sealing member for sealing the main and auxiliary organic light emitting diodes OLED and OLED 'may also be disposed above the main and auxiliary organic light emitting diodes OLED and OLED', and components such as a touch sensor layer, a polarizing layer, a color filter layer, or a window may also be disposed on the sealing member.

Although the auxiliary thin film transistor TFT' for driving the auxiliary pixel Pa disposed in the sensor region SA is disposed in the first non-display region NDA1 in fig. 6 to 8, the present disclosure is not limited thereto. The auxiliary thin film transistor TFT' may not be disposed in the first non-display area NDA 1.

For example, as in another embodiment shown in fig. 9, the auxiliary scan driving circuit 120 'and the auxiliary data driving circuit 150' are disposed in the second non-display area NDA2 outside the display area DA, and the driving voltage and signal may be transmitted to the sensor area SA.

According to an exemplary embodiment of the inventive concept, the auxiliary pixels Pa constructed for PM driving are disposed in the sensor area SA, and the auxiliary pixels Pa are located in an area in which a plurality of horizontal electrodes extending substantially in a first direction and a plurality of vertical electrodes extending substantially in a second direction crossing the first direction cross each other.

The auxiliary scan lines SL 'of the auxiliary scan driving circuit 120' may be directly connected to the horizontal electrodes disposed in the sensor area SA. The auxiliary data lines DL 'of the auxiliary data driving circuit 150' may be directly connected to the vertical electrodes disposed in the sensor area SA.

According to an exemplary embodiment of the inventive concept, lines for transmitting voltages and/or signals to the main pixels disposed in the display area DA may be disposed in the first non-display area NDA1 by bypassing along the sensor area SA.

As described above, according to the above-described embodiments, since the auxiliary pixels configured for PM driving are disposed in the sensor region corresponding to the component such as the sensor, it is possible to establish an environment for the operation of the sensor and, at the same time, to realize an image in the region overlapping with the sensor.

Accordingly, a display device capable of implementing various functions and providing enhanced quality can be provided.

The description of features or aspects within each embodiment may be considered applicable to other similar features or aspects in other embodiments, and thus the inventive concept contemplates any possible combination of elements and features of several exemplary embodiments described throughout this document.

While one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept.