阅读说明：本技术 用于检测存储器阵列层面的检测电路 (Detection circuit for detecting memory array level ) 是由 B·A·约翰逊 V·J·万卡雅拉 于 2021-03-30 设计创作，主要内容包括：本申请涉及用于检测存储器阵列的层面的检测电路。如所描述,装置可包含检测电路以检测存储器阵列的层面。所述层面可包含：耦合在逻辑高电压节点与所述检测电路之间的导电标识符；耦合到所述检测电路的控制电路。所述控制电路可执行操作,包含将测试启用信号传输到所述检测电路。所述检测电路可响应于所述测试启用信号而生成指示存在所述层面的所述导电标识符的有效信号。所述操作还可包含所述控制电路从所述检测电路接收所述有效信号,及至少部分地基于所述有效信号调整与所述存储器阵列相关联的存储器操作。(The application relates to a detection circuit for detecting a level of a memory array. As described, a device may include detection circuitry to detect a level of a memory array. The deck may include: a conductive identifier coupled between a logic high voltage node and the detection circuit; a control circuit coupled to the detection circuit. The control circuit may perform operations including transmitting a test enable signal to the detection circuit. The detection circuit may generate a valid signal indicating the presence of the conductive identifier of the deck in response to the test enable signal. The operations may also include the control circuitry receiving the valid signal from the detection circuitry and adjusting a memory operation associated with the memory array based at least in part on the valid signal.)

1. An apparatus, comprising:

a detection circuit including a latch circuit; and

a deck of a memory array, wherein the deck includes a conductive identifier arranged to be coupled between a logic high voltage node and the latch circuit; and

a control circuit coupled to the detection circuit, wherein the control circuit is configured to perform operations comprising:

transmitting a test enable signal to the detection circuit, wherein the detection circuit is configured to generate a valid signal indicating the presence of the conductive identifier of the tier in response to the test enable signal;

receiving the valid signal from the latch circuit; and

adjusting a memory operation associated with the memory array based at least in part on the valid signal.

2. The device of claim 1, wherein the control circuitry is configured to adjust the memory operation based at least in part on a number of levels of the memory array, wherein the control circuitry is configured to use the valid signal to determine the number of levels of the memory array.

3. The device of claim 1, wherein the deck comprises a plurality of memory cells disposed in the same plane, wherein a subset of the plurality of memory cells share at least one word line and at least one bit line.

4. The device of claim 1, wherein the control circuit is configured to generate the test enable signal in response to a power-up of at least the detection circuit.

5. The device of claim 1, wherein the detection circuit comprises a plurality of inverters, wherein the detection circuit is configured to detect the presence of the deck and a presence of an additional deck of the memory array based at least in part on a logic gate that outputs a logic low signal when the memory array comprises the deck and the additional deck.

6. The device of claim 1, wherein the detection circuit comprises a logic gate that switches an output in response to a combination of the test enable signal and a reset signal, wherein the operation comprises generating the reset signal in response to the control circuit determining to reset a state held by the latch circuit.

7. The device of claim 1, wherein the detection circuit comprises a feedback path coupling an output of the latch circuit to an input of the latch circuit, wherein the feedback path is configurable to store a value corresponding to the valid signal.

8. The device of claim 7, wherein the operations comprise disabling the test enable signal when the feedback path stores the value corresponding to the valid signal.

9. The apparatus of claim 1, comprising a plurality of detection circuits, wherein the memory array comprises a plurality of levels other than the organization, wherein each respective level of the plurality of levels comprises a respective conductive identifier coupled between the logic high voltage node and a respective detection circuit of the plurality of detection circuits.

10. A method, comprising:

transmitting, by a control circuit, a test enable signal to a detection circuit, wherein the detection circuit is configured to generate a valid signal indicating the presence of a deck of a memory array in response to the test enable signal, wherein the deck comprises a conductive identifier coupled between a logic high voltage node and the detection circuit;

receiving, by the control circuit, the valid signal from the detection circuit; and

adjusting, by the control circuitry, a memory operation associated with the memory array based at least in part on the valid signal.

11. The method of claim 10, wherein adjusting the memory operation comprises:

determining, by the control circuitry, a total number of levels of the memory array based at least in part on the valid signal; and

adjusting, by the control circuitry, the memory operation based at least in part on a number of levels of the memory array.

12. The method of claim 11, wherein adjusting the memory operation based at least in part on the number of levels of the memory array comprises adjusting a memory address defined as a maximum memory address of the memory array.

13. The method of claim 10, wherein receiving, by the control circuit, the valid signal from the detection circuit comprises:

transmitting a timing signal to a latch circuit through the control circuit; and

receiving, by the control circuit, the valid signal from the detection circuit in response to the latch circuit receiving the timing signal.

14. The method of claim 10, comprising disabling, by the control circuit, the test enable signal after receiving the valid signal from the detection circuit.

15. The method of claim 10, comprising:

determining, by the control circuit, to reset an output from the latch circuit; and

in response to determining to reset the output from the latch circuit, a reset signal and an additional test enable signal are transmitted by the control circuit to the detection circuit.

16. An apparatus, comprising:

a detection circuit configured to be electrically coupled to a conductive identifier arranged to be coupled between a voltage node and the detection circuit, wherein the conductive identifier is associated with a level of a memory array; and

a control circuit coupled to the detection circuit, wherein the control circuit is configured to perform operations comprising:

transmitting a test enable signal to the detection circuit, wherein the detection circuit is configured to generate a valid signal indicating the presence of the conductive identifier in response to the test enable signal;

receiving the valid signal from the detection circuit; and

adjusting a memory operation associated with the memory array based at least in part on the valid signal.

17. The device of claim 16, wherein the detection circuit comprises a plurality of logic gates configured to operate in combination to generate the valid signal in response to the conductive identifier coupling the detection circuit to the logic high voltage node.

18. The apparatus of claim 17, and wherein the plurality of logic gates comprises and gates, or gates, nand gates, nor gates, xor gates, inverting gates, or any combination thereof.

19. The device of claim 16, wherein the memory operation is associated with a write memory command, a read memory command, a refresh memory command, or any combination thereof.

20. The device of claim 16, wherein the control circuit is configured to receive the valid signal from the detection circuit based at least in part on an output generated by cross-coupled inverters.

Technical Field

The present disclosure relates to memory, and in particular, to detection circuitry for detecting a level of a memory array.

Background

This section is intended to introduce the reader to various aspects of art, which may be related to various aspects of the present technology that are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.

In general, a computing system includes processing circuitry, such as one or more processors or other suitable components; and a memory device, such as a chip or an integrated circuit. One or more memory devices may be used on a memory module, such as a dual in-line memory module (DIMM), to store data accessible by the processing circuit. For example, based on user input to the computing system, the processing circuit may request the memory module to retrieve data corresponding to the user input from its memory device. In some examples, the retrieved data may include firmware, or instructions executable by processing circuitry to perform operations, and/or may include data to be used as input for the operations. Additionally, in some cases, data output from the operation may be stored in memory, e.g., so that the data can be subsequently retrieved from the memory.

Some of the memory devices include memory cells that can be accessed by turning on transistors that couple the memory cells (e.g., capacitors) with word lines or bit lines. In contrast, threshold type memory devices include memory devices that are accessed by providing a voltage across a memory cell, where a data value is stored based on the threshold voltage of the memory cell. For example, the data value may be based on whether a threshold voltage of the memory cell is exceeded, and in response to the voltage provided across the memory cell, the memory cell conducts current. The stored data value can be changed, for example, by applying a voltage sufficient to change the threshold voltage of the memory cell. One example of a threshold type memory cell may be a cross-point memory cell.

For threshold type memories, word lines and bit lines are used to transmit select signals to the respective memory cells. The select signal may include a signal characterized by a voltage level used to save data into or retrieve data from the memory cell. The word lines and bit lines may be coupled to a selection signal source through a decoding circuit (e.g., a decoder). The memory cells may be organized into one or more layers of memory cells, such as a layer defined between overlapping word lines and bit lines. These layers may be referred to as levels (e.g., memory levels). Various combinations of word lines, bit lines, and/or decoders may be referenced for a particular memory operation using an address (e.g., a memory address). The address may indicate which memory cell is to be selected using a combination of signals from word lines, bit lines, and/or decoders, and the particular value of the address may be based on the address range of the memory device. The maximum address (e.g., an upper limit for the address) may be based on the number of memory cells formed in a single level and the number of levels the memory array includes. When manufacturing memory devices, various memory arrays having different numbers of levels can be produced in the same production line. Since the number of levels of the respective memory array is used to determine the maximum address of the memory device, methods of improving the determination of the number of levels (e.g., improving the consistency of the determination) may be desired.

Disclosure of Invention

Aspects of the present disclosure provide an apparatus, wherein the apparatus comprises: a detection circuit including a latch circuit; and a deck of a memory array, wherein the deck includes a conductive identifier arranged to be coupled between a logic high voltage node and the latch circuit; and a control circuit coupled to the detection circuit, wherein the control circuit is configured to perform operations comprising: transmitting a test enable signal to the detection circuit, wherein the detection circuit is configured to generate a valid signal indicating the presence of the conductive identifier of the tier in response to the test enable signal; receiving the valid signal from the latch circuit; and adjusting a memory operation associated with the memory array based at least in part on the valid signal.

Another aspect of the present disclosure provides a method, wherein the method comprises: transmitting, by a control circuit, a test enable signal to a detection circuit, wherein the detection circuit is configured to generate a valid signal indicating the presence of a deck of a memory array in response to the test enable signal, wherein the deck comprises a conductive identifier coupled between a logic high voltage node and the detection circuit; receiving, by the control circuit, the valid signal from the detection circuit; and adjusting, by the control circuitry, a memory operation associated with the memory array based at least in part on the valid signal.

Another aspect of the present disclosure provides an apparatus, wherein the apparatus comprises: a detection circuit configured to be electrically coupled to a conductive identifier arranged to be coupled between a voltage node and the detection circuit, wherein the conductive identifier is associated with a level of a memory array; and a control circuit coupled to the detection circuit, wherein the control circuit is configured to perform operations comprising: transmitting a test enable signal to the detection circuit, wherein the detection circuit is configured to generate a valid signal indicating the presence of the conductive identifier in response to the test enable signal; receiving the valid signal from the detection circuit; and adjusting a memory operation associated with the memory array based at least in part on the valid signal.

Drawings

Various aspects of this disclosure may be better understood upon reading the following detailed description and upon reference to the drawings in which:

FIG. 1 is a simplified block diagram illustrating certain features of a memory device, according to an embodiment of the present disclosure;

FIG. 2 is a circuit diagram illustrating the memory array of FIG. 1 in accordance with an embodiment of the present disclosure;

FIG. 3 is a side view illustrating a drawing of a portion of the memory array of FIG. 2, in accordance with an embodiment of the present disclosure;

FIG. 4 is a circuit diagram of a detection circuit for detecting the memory array level of FIG. 2, according to an embodiment of the present disclosure;

figure 5 is a flow diagram of a process for operating detection circuitry for detecting the level of figure 4, according to an embodiment of the present disclosure;

FIG. 6 is a circuit diagram of a second detection circuit for detecting the memory array level of FIG. 2, according to an embodiment of the present disclosure;

FIG. 7 is a circuit diagram of a third detection circuit for detecting the memory array level of FIG. 2, according to an embodiment of the present disclosure;

FIG. 8 is a circuit diagram of a fourth detection circuit for detecting the memory array level of FIG. 2, according to an embodiment of the present disclosure;

FIG. 9 is a circuit diagram of fifth detection circuitry for detecting the memory array level of FIG. 2, according to an embodiment of the present disclosure; and

figure 10 is a circuit diagram of a sixth detection circuit for detecting the memory array level of figure 2, according to an embodiment of the present disclosure.

Detailed Description

One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, all features of an actual implementation may not be described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

The memory generally includes an array of memory cells, with each memory cell coupled between at least two access lines. For example, the memory cells may be coupled to access lines, such as bit lines and word lines. Each access line may be coupled to a large number of memory cells. To select a memory cell, one or more decoder circuits may provide a selection signal (e.g., a voltage and/or current) on an access line to access the storage capacity of the memory cell. By applying voltages and/or currents to the respective access lines, the memory cells can be accessed in order to write data to and/or read data from the memory cells.

In some memories, the memory cells in the array may be organized into a memory cell level. The memory cell level may be a single plane of memory cells disposed between a word line layer and a bit line layer. The array may be a level stack including any number of memory cell levels (e.g., 0 level, 1 level, 2 level, 4 level, any number of levels) as different array levels. The number of levels may change the total memory capacity of the array. Since the total number of levels changes the number of memory cells included in the array, the maximum address of the array can thereby be based at least in part on the total number of levels in the array. Thus, memory operations and addressing used in memory operations may vary based on the number of levels.

In some cases, the number of levels may be identified at the time of manufacture. The number of levels may be stored in registers and/or fuses of the memory device so that the memory controller can determine the number of levels during operation of the memory device. Identifying the number of levels may be performed at the time of manufacture by counting levels and/or tracking manufacturing operations to form the memory device. However, this approach of identifying the number of levels may be susceptible to human and/or manufacturing errors, as the number of levels may be misidentified and unable to be corrected in the registers and/or fuses used to store the indication of the number of levels. Furthermore, even if the correct number of levels is identified, the number of levels may be mis-entered into registers and/or fuses.

One method of detecting the number of levels of mis-inputs may be to identify when to read nonsense data and/or incorrect data from the memory array. However, during operation, it may be relatively difficult to identify when a memory device is misbehaving (e.g., behaving according to an undesired operation) or when a memory device addresses memory units that are not present (such as may occur when the number of levels is incorrect and used by a memory controller during a memory operation), because incorrect data is only output as incorrect data and does not indicate the root cause of the incorrect data.

However, in some cases, at least a subset of the layers (e.g., each layer) may include connections (e.g., layer-specific conductive identifiers) that enable identification of the number of layers within the array. In this way, the memory controller may determine the number of levels without using the above-described level determinations stored in registers and/or fuses. The deck-specific conductive identifiers may each be a metal element associated with the deck (e.g., integrated into the deck, associated with coupling of the deck). The memory controller may detect each tier-specific conductive identifier to determine the number of tiers of a tier within the array. By reducing the likelihood that an incorrect number of levels are used to generate memory addresses, the operation of the memory device may be improved using a hardwired connection detection level to include a closed circuit connection.

The memory controller may repeatedly identify the number of levels each time the memory device is powered on. However, in some cases, the number of levels may be stored in the feedback path, making it relatively more complex to perform repeatedly identifying the number of levels. For example, the repeated identification of the number of levels may be performed in response to the detection circuit receiving multiple operational enable signals as compared to a single signal transmitted in response to power-up of the memory device. Using at least these described systems and methods, a memory controller may determine addresses for a memory array using a subset of the levels (e.g., level 0, level 1, level 2, rather than level 3).

With the foregoing description in mind, FIG. 1 is a block diagram of a portion of a memory 100. Memory 100 may be any suitable form of memory, such as non-volatile memory (e.g., cross-point memory) and/or volatile memory. The memory 100 may include one or more memory cells 102, one or more bit lines 104 (e.g., 104-0, 104-1, 104-2, 104-3), one or more word lines 106 (e.g., 106-0, 106-1, 106-2, 106-3), one or more word line decoders 108 (e.g., word line decoding circuitry), and one or more bit line decoders 110 (e.g., bit line decoding circuitry). The memory cells 102, bit lines 104, word lines 106, word line decoders 108, and bit line decoders 110 may form a memory array 112.

Each of the memory cells 102 may include a selector and/or a storage element. When the voltage across the selector of the respective memory cell reaches a threshold value, the storage element can be accessed to read and/or write a data value from/to the storage element. In some embodiments, each of the memory cells 102 may not include a separate selector and storage element, and have a configuration such that the memory cells still function as having a selector and a storage element (e.g., may include using materials that behave similarly to both the selector material and the storage element material). For ease of discussion, FIG. 1 may be discussed with respect to bit line 104, word line 106, word line decoder 108, and bit line decoder 110, but these designations are non-limiting. The scope of the present disclosure should be understood to cover memory cells 102 coupled to multiple access lines and accessed by respective decoders, where the access lines may be used to store data into and read data from the memory cells.

The bit line decoders 110 may be organized in groups of decoders. For example, the memory 100 may include a first set of bit line decoders 114 (e.g., a plurality of bit line decoders 110) and/or a second set of bit line decoders 116 (e.g., a different set of a plurality of bit line decoders 110). Similarly, the word line decoders 108 may also be arranged in groups of word line decoders 108, such as a first set of word line decoders 118 and/or a second set of word line decoders 120. When selecting a target memory cell 102A from the memory cells 102, the decoders may be used in combination with each other to drive the memory cells 102 (e.g., paired and/or paired on either side of the word lines 106 and/or bit lines 104). For example, bit line decoder 110-4 may operate in conjunction with bit line decoder 110'-4 and/or in conjunction with word line decoders 108-0, 108' -0 to select memory cell 102A. As can be appreciated herein, the decoder circuitry on either end of the word line 106 and/or bit line 104 may be different.

Each of the bit lines 104 and/or word lines 106 may be a metal trace disposed in the memory array 112 and formed of a metal such as copper, aluminum, silver, tungsten, and the like. Accordingly, the bit lines 104 and word lines 106 may have a uniform resistance per length and a uniform parasitic capacitance per length, such that the resulting parasitic load may increase uniformly per length. It should be noted that the depicted components of memory 100 may include additional circuitry not specifically depicted and/or may be disposed in any suitable arrangement. For example, subsets of word line decoders 108 and/or bit line decoders 110 may be disposed on different sides of memory array 112 and/or on different physical sides of any plane that includes circuitry.

The memory 100 may also include control circuitry 122. The control circuit 122 is communicatively coupled to respective ones of the word line decoder 108 and/or the bit line decoder 110 to perform memory operations, such as by having decoding circuitry (e.g., a subset of the word line decoder 108 and/or the bit line decoder 110) generate selection signals (e.g., selection voltages and/or selection currents) for selecting a target of a memory cell. In some embodiments, positive and negative voltages may be provided to the targets of the memory cells 102 on one or more of the bit lines 104 and/or word lines 106, respectively. In some embodiments, the decoder circuit can provide electrical pulses (e.g., voltages and/or currents) to access lines that access the memory cells. The electrical pulse may be a rectangular pulse, or in other embodiments, other shaped pulses may be used. In some embodiments, the voltage provided to the access lines may be a constant voltage.

Activating the decoder circuit can achieve the goal of delivering the electrical pulse to the memory cell 102 so that the control circuit 122 can access the data storage device of the target memory cell in order to read from or write to the data storage device. After accessing the target of memory cell 102, the data stored in the storage medium of the target memory cell may be read or written. Writing to the target memory cell may include changing a data value stored by the target memory cell. As previously discussed, the data value stored by a memory cell may be based on the threshold voltage of the memory cell. In some embodiments, a memory cell may be "set" to have a first threshold voltage, or may be "reset" to have a second threshold voltage. The set memory cell may have a lower threshold voltage than the reset memory cell. By setting or resetting the memory cells, different data values may be stored by the memory cells. Reading the target of memory cell 102 may include determining whether the target memory cell is characterized by a first threshold voltage and/or by a second threshold voltage. In this manner, the threshold voltage window may be analyzed to determine the value stored by the target of memory cell 102. The threshold voltage window may be generated by applying programming pulses of opposite polarity to the memory cells 102 (e.g., specifically to the Selector Device (SD) material of the memory cells) and reading the memory cells 102 (e.g., specifically to read the voltage stored by the SD material of the memory cells) using a signal of a given (e.g., known) fixed polarity.

Figure 2 is a diagram illustrating a portion of a memory array 130 in accordance with an embodiment of the present disclosure. The memory array 130 may be a cross-point array including word lines 106 (e.g., 106-0, 106-1,.., 106-N) and bit lines 104 (e.g., 104-0, 104-1,.., 104-M). A memory cell 102 may be located at each of the intersections of a word line 106 and a bit line 104. The memory cells 102 may function in a two-terminal architecture, e.g., where particular ones of the word lines 106 and bit lines 104 serve as electrodes for particular ones of the memory cells 102.

Each of the memory cells 102 may be a resistance variable memory cell, such as a Resistive Random Access Memory (RRAM) cell, a Conductive Bridging Random Access Memory (CBRAM) cell, a Phase Change Memory (PCM) cell, and/or a spin transfer torque magnetic random access memory (STT-RAM) cell, among other types of memory cells. Each of the memory cells 102 may include memory elements (e.g., memory material) and selector elements (e.g., Selector Device (SD) material) and/or material layers that functionally replace the separate memory element layers and selector element layers. The selector elements (e.g., SD material) may be disposed between word line contacts (e.g., layer interfaces between respective ones of the word lines 106 and the memory material) and bit line contacts associated with word lines or bit lines forming the memory cells (e.g., layer interfaces between respective ones of the bit lines 104 and the selector elements). When a read or write operation is performed on a memory cell, an electrical signal may be transmitted between a word line contact and a bit line contact.

The selector element may be a diode, a non-ohmic device (NOD), or a chalcogenide switching device, etc., or formed similarly to the underlying cell structure. In some examples, the selector element may include a selector material, a first electrode material, and a second electrode material. The memory elements of memory cell 102 may include memory portions (e.g., portions that are programmable to different states) of memory cell 102. For example, in a resistance variable memory cell 102, a memory element may include a portion of a memory cell having a resistance that is programmable to a particular level corresponding to a particular state in response to an applied programming voltage and/or current pulse. In some embodiments, memory cells 102 can be characterized as threshold type memory cells that are selected (e.g., activated) based on a voltage and/or current that crosses a threshold associated with a selector element and/or a memory element. Embodiments are not limited to the particular resistance variable material or materials associated with the storage elements of memory cell 102. For example, the resistance variable material may be a chalcogenide formed from various doped or undoped chalcogenide-based materials. Other examples of resistance variable materials that can be used to form a storage element include, among others, a two-state metal oxide material, a giant magnetoresistive material, and/or various polymer-based resistance variable materials.

In operation, the memory cell 102 may be programmed by applying a voltage (e.g., a write voltage) across the memory cell 102 via the selected word line 106 and bit line 104. A sensing (e.g., read) operation may be performed to determine the state of one or more memory cells 102 by sensing a current. For example, in response to a particular voltage applied to a selected one of the word lines 106 forming a respective memory cell 102, a current may be sensed on one or more bit lines 104 corresponding to the respective memory cell 102.

As illustrated, the memory array 130 may be arranged in a cross-point memory array architecture (e.g., a three-dimensional (3D) cross-point memory array architecture) that extends in any direction (e.g., x-axis, y-axis, z-axis). The multi-level cross-point memory array 130 can include a plurality of consecutive memory cells (e.g., 102B, 102C, 102D) disposed between alternating (e.g., staggered) levels of word lines 106 and bit lines 104. The number of levels may be increased or decreased and should not be limited to the depicted volumes or arrangements. Each of the memory cells 102 may be formed between a word line 106 and a bit line 104 (e.g., between two access lines), such that a respective one of the memory cells 102 may be directly electrically coupled (e.g., electrically coupled in series) with its respective pair of bit line 104 and word line 106, and/or formed from electrodes (e.g., contacts) made from respective portions of metal in the respective pair of bit line 104 and word line 106. For example, the memory array 130 may include a three-dimensional matrix of individually addressable (e.g., randomly accessible) memory cells 102 that may be accessed at a granularity as small as a single storage element and/or multiple storage elements for data operations (e.g., sensing and writing). In some cases, the memory array 130 may include more or fewer bit lines 104, word lines 106, and/or memory cells 102 than shown in the example of fig. 2. Each level may include one or more memory cells 102 aligned in the same plane.

Fig. 3 is a side view illustrating a diagram of a portion of the memory array 130 of fig. 2. Specifically, the memory array 130 of FIG. 3 includes the word lines 106, bit lines 104, and memory cells 102 previously discussed. Each of the memory cells 102 may be disposed in a particular plane between a bit line and a word line. The level of planes may be referred to as a "level," and thus the depicted example includes memory cells 102E, 102F, and 102G disposed in the same level, and a total of four levels of memory cells 102. Each of the memory cells 102 may include a phase change material (PM)134 and a selector device material (SD) 136. It should be noted that in some memory arrays 130, the PMs 134 and SDs 136 may be combined or functionally provided by one layer of material rather than two layers of material. In this manner, some memory arrays 130 may be based on a single channel (e.g., SD only) process architecture that reduces cross-contamination between PM 134 and SD 136 layers.

The memory array 130 may also include a socket 138. Each socket 138 may include a decoder coupled to each of the bit lines 104 and/or word lines 106. Socket 138 may be used when signals (e.g., signals 140A, 140B) read from and/or written to memory cells 102 are transmitted from other circuits of memory 100. It should be noted that the arrows corresponding to signals 140A and/or 140B may generally represent communication between word line 106 and/or bit line 104 and the decoder of socket 140. It should be noted that the negative spaces 142 depicted between the word lines 106 and/or bit lines 104 (and other circuitry of the memory array 130) may correspond to the air or ambient atmosphere of the memory 100, although the negative spaces 142 may also be filled with insulating materials and/or other suitable materials for computing devices. It should be noted that the distance between the word lines 106 and/or bit lines 104 may be exaggerated for clarity, and may be reduced in a practical implementation to reduce the volume of the negative space 142 within the final article. It should also be noted that an additional layer of isolation material 144 may be disposed over the socket 138 (e.g., between the socket 138 layer and the first level of the word line 106 or bit line 104).

Respective ones of the memory cells 102 are accessible based on a memory address, which defines at which intersection of the word line 106 and the bit line 104 and on which level the respective ones of the memory cells 102 are formed. Since the total number of levels changes the number of memory cells 102 included in the memory array 130, the maximum memory address of the memory array 130 can thus be based on the total number of levels. Thus, the memory operation and the range used for memory addressing in the memory operation may vary based on the number of levels.

In some cases, the number of levels may be identified at the time of manufacture. In these cases, the number of levels may be stored in a write-once register and/or fuses, such that control circuitry 122 or other suitable memory controller may determine the number of levels for reference purposes during operation and/or for reference purposes when determining memory addresses. Identifying the number of levels may be accomplished by substantially physically counting the levels at the time of manufacture and/or by tracking the manufacturing operations performed in forming memory array 130. However, this method of identifying the number of levels may be susceptible to human and/or manufacturing errors, as the number of levels may be misidentified and not capable of correction in a write-once register and/or fuse.

To improve the operation for identifying multiple levels in the memory array 130, conductive identifiers may be associated with one or more levels of the memory array 130. Control circuitry 122 may test the connections associated with the conductive identifiers as a way of testing whether a level is present in memory array 130. The conductive identifiers may be included on each level of the memory array 130 and/or on a subset of the levels of the memory array 130. When a subset of the levels of memory array 130 is used to identify the number of levels in the memory array, a first output from the detection circuitry may correspond to a first number of levels (e.g., 4 levels), a second output from the detection circuitry may correspond to a second number of levels (e.g., 2 levels), and a lack of output (e.g., no output, logic low output) corresponds to a third number of levels (e.g., 1 level). As described herein, various combinations of logic gates may be coupled together to detect the number of levels. It should be understood that the logic gates discussed herein may be suitably replaced with equivalent combinations of logic gates, such as any suitable combination of one or more and gates, or gates, nand gates, nor gates, xor gates, inverting gates, flip-flops (of any kind), and the like.

For purposes of elaboration, FIG. 4 is a circuit diagram of detection circuit 150A for detection level 152. The layer 152 may include a conductive identifier 154 coupled between a switch 156 and a system high voltage supply VCC (e.g., voltage node, logic high voltage node). During fabrication of the memory array 130, the conductive identifiers 154 may be disposed in a physical area of a memory core of the memory array 130 and/or in a peripheral circuit area of the memory array 130. Each level 152 may be formed by a series of material layer forming operations and patterning operations. When layer 152 is not present, the layers of layer 152 are not present and, therefore, may not include conductive identifier 154. Because conductive identifier 154 uses one of the levels of hierarchy 152, a connection will not be present (e.g., be an open circuit) when hierarchy 152 is not present, and conductive identifier 154 is present when hierarchy 152 is present, even if physically disposed outside of the memory core of memory array 130 (e.g., within memory array 112). It should be noted that the conductive identifier 154 may additionally or alternatively be coupled to a voltage supply (e.g., a voltage node), with a different voltage supply serving as the system voltage supply. Detection circuit 150A may be disposed within control circuit 122, within another suitable controller, external to level 152 (as depicted), on level 152, or any combination thereof. Control circuitry 122 may identify the presence of deck 152 based on the generation of deck valid signal 158.

To identify whether deck 152 is present, control circuitry 122 may transmit a control signal, i.e., test enable signal 160. The test enable signal 160 may include a voltage and/or current of sufficient amplitude to activate the switch 156. When the conductive identifier 154 is included on the layer 152, the transmission path between the flip-flop 162 and the system high voltage supply is completed. This causes the input received at the DATA terminal of flip-flop 162 to be a logic high signal.

Although the input at the DATA terminal of flip-flop 162 is a logic high signal, control circuit 122 may generate a timing signal 164 (e.g., a signal received at a Clock (CLK) terminal of flip-flop 162 that operates flip-flop 162 to lock and/or clock the input at the DATA terminal or other suitable terminal). When clocked, the output of flip-flop 162 becomes a logic high signal and control circuit 122 reads layer valid signal 158 as a logic high signal. It should be noted that the timing signal 164 need not be a clock signal, and may thus be any suitable signal capable of operating the flip-flop 162 to change its output.

If the deck 152 is not to be included in the memory array 130, but the control circuitry 122 is to attempt to identify the deck 152, then the transmission path between the flip-flop 162 and the system high voltage supply may not exist, and only the transmission path between the flip-flop 162 and the system low voltage supply VSS (e.g., ground voltage, logic low reference voltage) may be shut down. The transmission path may include resistance 166 and/or be characterized by resistance 166. This arrangement may cause the input received at the DATA terminal of flip-flop 162 to be a logic low signal. When a logic low signal is received at the DATA terminal of flip-flop 162, and when timing signal 164 causes the timing of a logic low signal, the output of flip-flop 162 may change to a logic low signal that is read by control circuit 122 as indicating that level 152 is not present.

In some cases, control circuit 122 may determine to reset the output from flip-flop 162. To do so, the control circuit 122 may generate the reset signal 168 and transmit the reset signal 168 to the flip-flop 162 (e.g., at the Rf terminal). In the case depicted here, the reset signal 168 may be transmitted as having a logic low value because the Rf terminal of the flip-flop 162 may be activated at logic low (e.g., the "f" indicator of the "Rf" terminal tag indicates a logic low activation for the pin). It should be noted, however, that for the case where the flip-flop receives the reset signal 168 at the non-inverting pin, the reset signal 168 may have a logic high value to reset the output from the flip-flop.

Each deck 152 of the memory array 130 may include a respective conductive identifier 154. In this manner, the memory array 130 may include one or more conductive identifiers, one conductive identifier for each level 152. That is, in the absence of conductive identifier 154, layer 152 may be said to be absent. And thus, the control circuitry 122 is said to generally detect the number of respective conductive identifiers included by the memory array 130 to determine the total number of levels of the memory array.

The control circuitry 122 may receive one or more respective layer valid signals (e.g., a respective one of which is the layer valid signal 158). Bits (e.g., a logic high bit or "1", a logic low bit or "0") corresponding to the value of the layer valid signal 158 and any other layer valid signals or other state identifying information may be stored in one or more registers or other suitable data storage. Control circuitry 122 may interpret the information stored in the register as indicating the presence of level 152 or additional levels. In some cases, the control circuitry 122 may receive the layer valid signal 158 and any other layer valid signals directly for controlling operations.

To help clarify the operation of control circuitry 122, FIG. 5 is a flow chart of a process 170 for detecting level 152. Control circuitry 122 is described below as performing process 170, but it should be understood that any suitable processing circuitry may additionally or alternatively perform process 170. Further, while the process 170 is described below as being performed in a particular order, it should be understood that another suitable order may be used to perform the individual operations of the process 170.

At block 172, the control circuit 122 may transmit the test enable signal 160. The control circuitry 122 may transmit the test enable signal 160 in response to the memory array 130 being powered on, such as in response to the memory device and/or the electronic device as a whole being powered on. In some cases, the test enable signal 160 is a signal derived from a power signal such that, upon power up, the test enable signal 160 is automatically transmitted to the detection circuit 150A. In this manner, the control circuit 122 may generate and transmit the test enable signal 160 in response to the energization of at least the detection circuit 150A.

At block 174, the control circuitry 122 may transmit the timing signal 164. As discussed, the timing signal 164 may operate the flip-flop 162 to latch and/or store an input received at its DATA terminal. The control circuit 122 may wait a certain duration after transmitting the test enable signal 160 to permit the input at the DATA terminal to properly indicate the presence level 152. The timing signal 164 may be a single pulse designed to operate the flip-flop 162 to lock on a value associated with the conductive identifier 154. As discussed, when the conductive identifier 154 is included on the layer 152, the transmission path between the flip-flop 162 and the system high voltage supply is completed. This may cause the input received at the DATA terminal of flip-flop 162 to be a logic high signal that is ready to be stored in flip-flop 162 at the transition of timing signal 164.

After clocking and/or latching the input of the DATA terminal into the flip-flop 162, the control circuit 122 may receive the layer valid signal 158 from the detection circuit 150A at block 176. It should be noted that when multiple levels (e.g., levels other than level 152) are being detected, control circuitry 122 may receive multiple valid signals (e.g., additional signals similar to layer valid signal 158) corresponding to each level. The control circuit 122 may determine the multiple levels using the level valid signal 158 from the detection circuit 150A and any additional valid signals.

At block 178, the control circuitry 122 may adjust one or more of the memory operations and/or their control operations based at least in part on the number of levels determined using the level valid signal 158. For example, the control circuitry 122 may mask additional address reference levels that are not present in the memory array 130 so that memory operations do not involve absent levels. As a second example, control circuitry 122 may change an indication of a maximum address value used in memory operations (e.g., a parameter referenced when generating a read command, a write command, a refresh command, etc.). In some cases, the layer valid signal 158 may be transmitted directly to a circuit that uses information associated with the number of layers in its operation.

Fig. 4 and 5 may describe how control circuitry 122 may generally operate to detect level 152. It should be noted that other variations of detection circuit 150A may also permit control circuit 122 to detect level 152. These other changes may adjust what signals are received at the DATA terminal, the Clock (CLK) terminal of flip-flop 162, the Rf terminal of flip-flop 162, and/or what circuits adjust the signals transmitted within the various detection circuits 150. It should be noted that some of the features described with reference to the detection circuit 150 may be applied as appropriate to one or more of the examples of the detection circuit 150. For example, the description of detection circuit 150A may also apply to detection circuit 150B and/or any other detection circuit described herein.

For purposes of elaboration, FIG. 6 is a circuit diagram of detection circuit 150B for detection level 152. Detection circuit 150B includes additional circuitry relative to detection circuit 150A of fig. 4, and thus is operable to prevent multiple resampling of conductive identifier 154 by blocking the path of the CLK input to flip-flop 162 (e.g., the storage element represented by flip-flop 162). This may be desirable when the transmission of the timing signal 164 may be repeated during operation of the memory 100. The layer 152 includes a conductive identifier 154 coupled between a switch 156 and the system high voltage supply VCC. The detection circuit 150B may be disposed within the control circuit 122, within another suitable controller, external to the level 152 (as depicted), on the level 152, or any combination thereof. Control circuitry 122 may identify that deck 152 is present by reading a deck valid signal 158.

Control circuitry 122 may initially test for the presence of deck 152 by transmitting reset signal 168 through logic gates 190(190A, 190B, 190C). When control circuit 122 also transmits timing signal 164 to logic gate 190, logic gate 190A may output a logic low signal to inverting gate 192A to generate control signal 194. Control signal 194 may activate switch 156.

Control signal 194 may include a voltage and/or current of sufficient value to activate switch 156. When the conductive identifier 154 is included on the layer 152, the transmission path between the flip-flop 162 and the system high voltage supply is completed. This causes the input received at the DATA terminal of flip-flop 162 to be a logic high signal.

Control signal 194 may also cause flip-flop 162 to store a logic high signal received at the DATA terminal. Flip-flop 162, storing a logic high signal value, may cause layer valid signal 158 to be output to control circuitry 122, thereby indicating that there is a level 152. It should be noted that to reset the output from flip-flop 162, for example, for performance of duplicate detection, control circuit 122 may transmit a reset signal 168 to flip-flop 162 (e.g., at the Rf terminal).

As another example, fig. 7 is a circuit diagram of a detection circuit 150C for detecting a level 152. The detection circuit 150C includes additional circuitry relative to the detection circuit 150A of FIG. 4, and thus is operable to prevent multiple resampling of the conductive identifier 154 by blocking the path of the DATA input to the flip-flop 162 (e.g., the storage element represented by the flip-flop 162), which may be required after deactivating the test enable signal 160. This may be desirable when the transmission of the timing signal 164 may be repeated during operation of the memory 100. The layer 152 includes a conductive identifier 154 coupled between a switch 156 and the system high voltage supply VCC. The detection circuit 150C may be disposed within the control circuit 122, within another suitable controller, external to the level 152 (as depicted), on the level 152, or any combination thereof. Control circuitry 122 may identify that deck 152 is present by reading a deck valid signal 158.

Control circuit 122 may initially test for the presence of deck 152 by transmitting test enable signal 160 directly to switch 156. When deck 152 is present, a logic high signal is transmitted to logic gate 190D. When control circuit 122 performs the detect operation for the first time, logic gate 190D may receive a logic high signal via path 200 and a logic low signal via path 202. In response to these inputs on paths 200 and 202, logic gate 190D may output a logic low signal to inverter 192B, which generates a logic high signal for transmission to the DATA terminal of flip-flop 162. When the control circuit 122 transmits the timing signal 164 to the flip-flop 162, the flip-flop 162 may generate the layer valid signal 158 comprising a logic high signal. The control circuitry 122 may receive the layer valid signal 158 and use the value of the layer valid signal 158 to determine the number of levels in the memory array 130.

The detection circuit 150C may also include a feedback path (e.g., path 202). Path 202 may feed back the value of layer valid signal 158 to logic gate 190D. This feedback path helps detect the presence of circuit 150C "memory" or memory level 152. Thus, logic gate 190D may continue to generate a logic low signal output using the remembered initial output of layer valid signal 158 even though flip-flop 162 receives a logic high signal at the CLK terminal as timing signal 164 and/or a logic low signal at the Rf terminal as reset signal 168. To reset the output of flip-flop 162, control circuit 122 may receive a logic high signal at the CLK terminal as timing signal 164 and a logic low signal at the Rf terminal as reset signal 168, followed by a logic high signal as test enable signal 160 to repeatedly activate switch 156. Reducing the likelihood of multiple detection operations by retaining the initial detection result (e.g., the first state change of layer valid signal 158 to indicate the presence of level 152) may improve the operation of the memory device by reducing the power consumed by the memory device identification level 152.

In yet another example, fig. 8 is a circuit diagram of detection circuitry 150D for detecting deck 152 and additional deck 210. Both level 152 and level 210 include respective ones of conductive identifiers 154 coupled between respective ones of switches 156 and a system high voltage supply VCC. Level 152 may correspond to a fourth level and level 210 may correspond to a second level. The detection circuit 150D may be disposed within the control circuit 122, within another suitable controller, external to the level 152 (as depicted), on the level 152, or any combination thereof. Based on which, if any, of the layer valid signals 212(212A, 212B) or, in some embodiments, which, if any, of the layer valid signals 214(214A, 214B) is detected, the control circuitry 122 may identify that the memory array 130 includes one deck, two decks, or four decks. It should be noted that in some cases, three levels may not be used in the memory array 130, e.g., due to binary arithmetic criteria, so the control circuit 122 may not specifically test for whether there are three levels.

For example, when the control circuitry 122 detects the layer valid signal 212A and/or the layer valid signal 214A, the control circuitry 122 may determine that the memory array 130 includes four levels. However, when control circuitry 122 detects layer valid signal 212B and/or layer valid signal 214B, control circuitry 122 may determine that memory array 130 includes two levels. When control circuitry 122 does not detect any of layer valid signal 212 and/or layer valid signal 214, control circuitry 122 may determine that memory array 130 includes one level. The control circuit 122 may use inference-based determinations with the detection circuit 150D to determine the number of layers by interpreting the missing layer valid signals 212 and 214 to mean a particular number of layers.

To clarify operation, in some cases control circuit 122 receives layer valid signal 212 directly from path 216 and/or path 218. When deck 210 includes conductive identifier 154 and deck 152 does not include conductive identifier 154 (e.g., when logic gate 190E receives a logic low signal from inverter 192D and a logic low signal from path 216), logic gate 190F may output a logic high signal. As depicted, path 216 may transmit a logic high signal as layer valid signal 212A when layer 152 includes conductive identifier 154.

In some cases, detection circuit 150D may include logic gates 190F, 190G, and 190H to further control the output of layer valid signal 212 to control circuit 122 (e.g., as layer valid signal 214). The control circuit 122 may transmit the logic low signal as the test enable signal 160 to permit the logic gates 190F, 190G, and 190H to selectively output at most one of the layer valid signals 214 to the control circuit 122.

Heretofore, in each example, the detection circuit 150 includes a latch circuit (e.g., flip-flop 162). However, in some cases, the control circuit 122 may use other circuits to generate the layer valid signal 158, such as cross-coupled inverters. For example, fig. 9 is a circuit diagram of detection circuitry 150E for detection level 152. The layer 152 includes a conductive identifier 154 coupled between the switch 230 and the system high voltage supply VCC. Switch 230 may be coupled to switch 232, the switch 232 being coupled to the system low voltage supply VSS. The detection circuit 150E may be disposed within the control circuit 122, within another suitable controller, external to the layer 152 (as depicted), on the layer 152, or any combination thereof. Control circuitry 122 may identify that deck 152 is present by reading a deck valid signal 158.

For elaboration, control circuit 122 may receive layer valid signal 158 from inverter 192H. In some cases, the inverter 192H may transmit the layer valid signal 158 into a register and/or data storage for access by the control circuit 122. The control circuit 122 may transmit a reset signal 168 adapted to cause the switch 232 to activate. When activated, a logic low signal is stored by the cross-coupled inverters 192F and 192G, such that the cross-coupled inverters 192F and 192G continuously input and output logic low signals to each other.

When control circuitry 122 is ready to detect the presence of deck 152, control circuitry 122 may transmit combined enable and clock signal 234 as the inverse of reset signal 168. The combined enable and clock signal 234 may activate a logic high signal and permit transmission of the logic high signal to the cross-coupled inverters 192F and 192G to overwrite storage of the logic low signal. The timing signal 164 and/or the test enable signal 160 may be functionally provided by the combined enable and clock signal 234. The combined enable and clock signal 234 and switch 230 may have appropriate strength to account for the feedback of the cross-coupled inverters 192F and 192G. In some cases, the voltage values of the combined enable and clock signal 234 and/or the test enable signal 160 may be used to control the feedback of the cross-coupled inverters 192F and 192G (e.g., affect the gain from the respective outputs of the inverters 192F and/or 192G). When cross-coupled inverters 192F and 192G store a logic high output from deck 152, deck valid signal 158 may change state to indicate the presence of deck 152 to control circuitry 122. Further, once the cross-coupled inverters 192F and 192G store a logic high output from the deck 152, the combined enable and clock signal 234 may be disabled to prevent the detection circuit 150E from consuming additional power (e.g., because the cross-coupled inverters 192F and 192G hold the detection results in memory).

In some cases, additional circuitry may be added to detection circuit 150B. Fig. 10 is a circuit diagram of detection circuit 150F for detecting deck 152, with additional circuitry 250 added to detection circuit 150B. The additional circuitry 250 includes a logic gate 252 (e.g., an or gate) that receives an input from the logic gate 190A and a resampled signal 254. Detection circuit 150F is operable to prevent multiple resampling of conductive identifier 154 by preventing a path of the CLK input to flip-flop 162 (e.g., the storage element represented by flip-flop 162). This may be desirable when the transmission of the timing signal 164 may be repeated during operation of the memory 100. The assertion/de-assertion of resample signal 254 may potentially reset, re-enable, and re-measure the conductive paths of conductive identifier 154. This may increase flexibility in the use of the detection circuit 150F and may permit the memory 100 to be retested after the initial use of the detection circuit 150F.

Technical effects of the present disclosure include systems and methods that allow a control circuit to determine a number of levels included within a corresponding memory array based on a number of detected level valid signals. This can replace the method associated with reading a write-once fuse that burns during manufacturing and is subject to operator-based or interpretation-based errors. Many detection circuits are described herein that include variations in signals used for timing, signals used to generate layer valid signals, and the like. Further, in some cases, some detection circuits may use latch circuits, while some detection circuits may transmit the layer valid signal directly to a circuit that interprets the layer valid signal, such as a control circuit. It should be noted that some of the described detection circuit examples may use relatively fewer components and, thus, may be relatively less expensive (e.g., smaller footprint, lower manufacturing cost) than other detection circuit examples having relatively more components. Additionally or alternatively, a detection circuit that receives relatively fewer input signals to generate a layer valid signal may be considered an improvement over a detection circuit that receives relatively more input signals. For example, the detection circuit of fig. 6 may operate in response to two input signals (e.g., a test enable and reset signal), while the detection circuit of fig. 4 may operate in response to three input signals (e.g., a test enable, a timing, and a reset signal), and thus may be considered an improved and/or more efficient design of the detection circuit.

While the disclosure may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the disclosure is not intended to be limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure as defined by the following appended claims.

The technology presented and claimed herein is referenced and applied to material objects and embodiments of a practical nature that arguably improve upon the art and are therefore not abstract, intangible, or purely theoretical. Furthermore, if any claim appended to the end of this specification contains one or more elements denoted as "means for [ performing ] [ function ] … …" or "step for [ performing ] [ function ] … …", it is intended that such elements be construed in accordance with 35u.s.c.112 (f). However, for any claim containing elements specified in any other way, it is not intended that such elements be construed in accordance with 35u.s.c.112 (f).