阅读说明：本技术 存储单元读取电路 (Memory cell reading circuit ) 是由 简红 蒋信 熊保玉 于 2018-08-22 设计创作，主要内容包括：本发明提供一种存储单元读取电路,包括：存储单元、NMOS晶体管及PMOS晶体管,其中,所述存储单元一端与位线连接,所述位线连接至一电流源,所述电流源用于产生读电流,所述存储单元另一端与字线控制电路连接；所述NMOS晶体管的栅极与所述位线连接,所述NMOS晶体管的源极接地,所述NMOS晶体管的漏极与所述PMOS晶体管的漏极连接,作为数据输出端；所述PMOS晶体管的栅极输入预充电控制信号,所述PMOS晶体管的源极输入预充电电压信号。本发明能够提高存储单元的数据读取速度。(The invention provides a memory cell reading circuit, comprising: the memory comprises a memory unit, an NMOS transistor and a PMOS transistor, wherein one end of the memory unit is connected with a bit line, the bit line is connected to a current source, the current source is used for generating reading current, and the other end of the memory unit is connected with a word line control circuit; the grid electrode of the NMOS transistor is connected with the bit line, the source electrode of the NMOS transistor is grounded, and the drain electrode of the NMOS transistor is connected with the drain electrode of the PMOS transistor and serves as a data output end; the grid electrode of the PMOS transistor is input with a pre-charge control signal, and the source electrode of the PMOS transistor is input with a pre-charge voltage signal. The invention can improve the data reading speed of the storage unit.)

1. A memory cell read circuit, comprising: a memory cell, an NMOS transistor, and a PMOS transistor, wherein,

one end of the storage unit is connected with a bit line, the bit line is connected with a current source, the current source is used for generating reading current, and the other end of the storage unit is connected with a word line control circuit;

the grid electrode of the NMOS transistor is connected with the bit line, the source electrode of the NMOS transistor is grounded, and the drain electrode of the NMOS transistor is connected with the drain electrode of the PMOS transistor and serves as a data output end;

the grid electrode of the PMOS transistor is input with a pre-charge control signal, and the source electrode of the PMOS transistor is input with a pre-charge voltage signal.

2. The memory cell reading circuit of claim 1, wherein the body voltage of the NMOS transistor is adjustable with a variable turn-on threshold voltage.

3. The memory cell reading circuit of claim 2, further comprising a temperature compensation circuit, an output of the temperature compensation circuit being coupled to the substrate of the NMOS transistor, the temperature compensation circuit being configured to adjust a bulk voltage of the NMOS transistor to change a turn-on threshold voltage of the NMOS transistor.

4. The memory cell reading circuit of claim 1, wherein the NMOS transistor is a long channel device.

5. The memory cell reading circuit of claim 1, wherein the structure of the NMOS transistor is a planar MOSFET structure or a FINFET structure.

6. The memory cell read circuit of claim 1, further comprising a filter capacitor connected between the data output and ground.

7. The memory cell reading circuit according to claim 1, wherein the memory cell is an MRAM memory cell, a resistive memory cell, or a phase change memory cell.

Technical Field

The invention relates to the technical field of memories, in particular to a memory cell reading circuit.

Background

The core of a Memory cell of a conventional Magnetic Memory (MRAM) is a Magnetic tunnel junction MTJ (MTJ), which is a two-port structure device composed of a multilayer film, the core is mainly composed of three films, two ferromagnetic layers are separated by a tunneling barrier layer, the magnetization direction of one of the ferromagnetic layers is fixed and is called a fixed layer or a reference layer, the magnetization direction of the other ferromagnetic layer can be changed and is called a free layer, and the magnetization direction of the free layer can be Parallel to the magnetization direction of the reference layer (Parallel, P for short) or Anti-Parallel to the magnetization direction of the reference layer (Anti-Parallel, AP for short). When the magnetization directions of the two ferromagnetic layers are parallel, the MTJ assumes a low resistance state, denoted Rp, whereas when the magnetization directions of the two ferromagnetic layers are anti-parallel, the MTJ assumes a high resistance state, denoted Rap. These two distinct resistance states can be used to characterize binary data "0" and "1" respectively at the time of information storage.

In a conventional MRAM memory cell reading circuit, as shown in fig. 1, a dashed box represents an MRAM memory cell, and the same reading voltage Vr is usually applied to a memory cell to be read and a reference cell (the resistance of the reference cell is 1/2 × (Rp + Rap)), and the reading currents output from the two cells are respectively input to two input terminals of a sense amplifier SA, and are compared by the sense amplifier SA to identify a high resistance state or a low resistance state of the MRAM memory cell.

In the process of implementing the invention, the inventor finds that at least the following technical problems exist in the prior art:

because the resistance of the MTJ is high, the read current is relatively small, and the read speed is slow when the resistance state is read by the sense amplifier.

Disclosure of Invention

To solve the above problems, the present invention provides a memory cell reading circuit, which can increase the data reading speed of a memory cell.

The invention provides a memory cell reading circuit, comprising: a memory cell, an NMOS transistor, and a PMOS transistor, wherein,

one end of the storage unit is connected with a bit line, the bit line is connected with a current source, the current source is used for generating reading current, and the other end of the storage unit is connected with a word line control circuit;

the grid electrode of the NMOS transistor is connected with the bit line, the source electrode of the NMOS transistor is grounded, and the drain electrode of the NMOS transistor is connected with the drain electrode of the PMOS transistor and serves as a data output end;

the grid electrode of the PMOS transistor is input with a pre-charge control signal, and the source electrode of the PMOS transistor is input with a pre-charge voltage signal.

Optionally, the body voltage of the NMOS transistor is adjustable with a variable turn-on threshold voltage.

Optionally, the transistor further comprises a temperature compensation circuit, an output end of the temperature compensation circuit is connected to the substrate of the NMOS transistor, and the temperature compensation circuit is used for adjusting the bulk voltage of the NMOS transistor so as to change the turn-on threshold voltage of the NMOS transistor.

Optionally, the NMOS transistor is a long channel device.

Optionally, the structure of the NMOS transistor adopts a planar MOSFET structure or a FINFET structure.

Optionally, the data output terminal further comprises a filter capacitor, and the filter capacitor is connected between the data output terminal and the ground.

Optionally, the memory cell is an MRAM memory cell, a resistance change memory cell, or a phase change memory cell.

The memory cell reading circuit provided by the invention can read the resistance value of the memory cell only by using the NMOS transistor and the PMOS transistor, can improve the data reading speed, saves a sensitive amplifier and a reference unit, simplifies the circuit structure and avoids the reading operation error caused by the distribution of the reference unit.

Drawings

FIG. 1 is a schematic diagram of a conventional reading circuit for a memory cell;

FIG. 2 is a schematic diagram of a memory cell reading circuit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a memory cell reading circuit according to another embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

An embodiment of the present invention provides a memory cell reading circuit, as shown in fig. 2, the circuit includes: the memory comprises a memory unit, an NMOS transistor NM1 and a PMOS transistor PM1, wherein one end of the memory unit is connected with a bit line BL, the bit line BL is connected to a current source, the current source is used for generating a read current Iread required by read operation, the other end of the memory unit is connected with a word line control circuit, the word line control circuit generally selects the NMOS transistor, the grid electrode of the NMOS transistor is connected with a word line, the drain electrode of the NMOS transistor is connected with the memory unit, and the source electrode of the NMOS transistor is grounded; the gate of NM1 is connected to bit line BL, the source of NM1 is grounded, the drain of NM1 is connected to the drain of PM1, and as a data output terminal, the output signal Vout, the gate of PM1 is inputted with precharge control signal PRE _ N, and the source of PM1 is inputted with precharge voltage signal VPRE.

With the memory cell read circuit, before a read operation, the input precharge control signal PRE _ N is at a low level, so that the PMOS transistor PM1 is turned on, and the data output terminal Vout is charged to the precharge voltage VPRE; at this time, the word line control circuit is turned off, the read current Iread is zero, the voltage Vin on the bit line BL is zero, and the NMOS transistor NM1 is turned off. In a read operation, the precharge control signal PRE _ N is first pulled high to turn off the PMOS transistor PM1, and then the word line control circuit is turned on to make the read current Iread flow through the memory cell, where the voltage of Vin only depends on the resistance of the memory cell. The NMOS transistor NM1 is turned on or off by Vin, so that Vout output is high or low. Whether the memory cell is in the low resistance state or the high resistance state can be reversely deduced according to the level state of Vout.

Specifically, when the memory cell is in the high-impedance state, Vin is a high voltage and is greater than the turn-on threshold voltage Vth of NM1, NM1 is turned on, and Vout output is at a low level, which is denoted as logic "0";

when the memory cell is in the low-resistance state, Vin is low and smaller than the on-threshold voltage Vth of NM1, NM1 is turned off, and Vout output is at a high level, which is recorded as logic "1".

The correspondence between the resistance state of the memory cell and the level state of Vout is seen in the following table:

resistance state of memory cell	Vout level
		High resistance state	Low level of electricity
Low resistance state	High level

Therefore, the memory cell reading circuit provided by the embodiment of the invention can read the resistance value of the memory cell only by using the NMOS transistor and the PMOS transistor, the on-off speed of the NMOS transistor and the PMOS transistor is very high, the data reading speed can be improved, a sensitive amplifier and a reference unit are omitted, the circuit structure is simplified, and meanwhile, the reading operation error caused by the distribution of the reference unit is avoided.

Further, since the on threshold voltage Vth of the NMOS transistor is greatly affected by temperature, the accuracy of reading data is affected. In order to reduce the influence of temperature on the turn-on threshold voltage Vth of the NMOS transistor, as shown in fig. 3, NM1 employs an NMOS transistor with an adjustable body voltage, which has a variable turn-on threshold voltage, adjusted by adjusting the body voltage. Correspondingly, a temperature compensation circuit is added in the memory cell reading circuit, and the output end of the temperature compensation circuit is connected to the substrate of NM1 and used for adjusting the bulk voltage Vbb of NM1, so that the on-threshold voltage Vth of NM1 is adjusted through the substrate bias effect of NMOS transistor, and the influence of temperature on Vth is reduced.

Further, the NMOS transistor in the embodiment of the present invention employs a deep well process device, so that the bulk voltage can be adjusted. Meanwhile, the NMOS transistor is a long-channel device, and the change of the breakover threshold voltage Vth along with the process can be smaller by adopting the long-channel device. The structure of the NMOS transistor can adopt a planar MOSFET structure or a FINFET structure.

As shown in fig. 3, to reduce the fluctuation of Vout, the memory cell read circuit may add a filter capacitor C1 between Vout and ground to make Vout smoother. It should be noted that the memory cell in fig. 3 is an MRAM memory cell, including a magnetic tunnel junction MTJ, and the magnetic moment of the free layer of the MTJ does not flip during the read operation. However, the memory cell is not limited to the MRAM memory cell, and any memory cell having two resistance values of a high resistance state and a low resistance state can be read by the memory cell reading circuit of the present invention, for example, the memory cell can also be a resistance change memory cell or a phase change memory cell.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.