阅读说明：本技术 存储器单元、存储器件及其形成方法 (Memory cell, memory device and forming method thereof ) 是由 蒋国璋 孙宏彰 赖昇志 杨子庆 江昱维 于 2021-03-04 设计创作，主要内容包括：存储器单元包括位于半导体衬底上方的薄膜晶体管。薄膜晶体管包括接触字线的存储器膜；以及接触源极线和位线的氧化物半导体(OS)层,其中,存储器膜设置在OS层和字线之间；以及将源极线和位线分隔开的介电材料。介电材料与OS层形成界面。介电材料包括氢,并且在介电材料和OS层之间的界面处的氢浓度不超过3原子百分比(at％)。本申请的实施例提供了存储器单元、存储器件及其形成方法。(The memory cell includes a thin film transistor located over a semiconductor substrate. The thin film transistor includes a memory film contacting the word line; and an Oxide Semiconductor (OS) layer contacting the source line and the bit line, wherein the memory film is disposed between the OS layer and the word line; and a dielectric material separating the source line and the bit line. The dielectric material forms an interface with the OS layer. The dielectric material includes hydrogen, and a concentration of hydrogen at an interface between the dielectric material and the OS layer is no more than 3 atomic percent (at%). Embodiments of the present application provide memory cells, memory devices, and methods of forming the same.)

1. A memory cell, comprising:

a thin film transistor over a semiconductor substrate, the thin film transistor comprising:

a memory film contacting the word line; and

an Oxide Semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line; and

a dielectric material separating the source line and the bit line, wherein the dielectric material forms an interface with the OS layer; wherein the dielectric material comprises hydrogen, and wherein a concentration of hydrogen at the interface between the dielectric material and the OS layer is no more than 3 atomic percent (at%).

2. The memory cell of claim 1, wherein the dielectric material comprises:

a first dielectric material contacting the OS layer, the first dielectric material extending continuously from the source line to the bit line; and

a second dielectric material on a side of the first dielectric material opposite the OS layer, the second dielectric material extending continuously from the source line to the bit line, a hydrogen concentration of the second dielectric material being greater than a hydrogen concentration of the first dielectric material.

3. The memory cell of claim 1, wherein the dielectric material comprises silicon oxide and a total hydrogen concentration of the dielectric material is greater than 0 at% and less than 5 at%.

4. The memory cell of claim 1, wherein the dielectric material comprises silicon nitride and a total hydrogen concentration of the dielectric material is greater than 0 at% and less than 10 at%.

5. The memory cell of claim 1, wherein the OS layer comprises hydrogen.

6. The memory cell of claim 1, wherein the OS layer has a hydrogen concentration of 10²⁰Atoms per cubic centimeter to 10²²Atoms per cubic centimeter.

7. The memory cell of claim 1, a longitudinal axis of the word line extending parallel to a major surface of a semiconductor substrate, a longitudinal axis of the source line extending perpendicular to the major surface of the semiconductor substrate, and a longitudinal axis of the bit line extending perpendicular to the major surface of the semiconductor substrate.

8. A memory device, comprising:

a semiconductor substrate;

a first memory cell over the semiconductor substrate, the first memory cell comprising a first thin film transistor, wherein the first thin film transistor comprises:

a gate electrode including a portion of the first word line;

a first portion of ferroelectric material located on sidewalls of the first word line; and

a first channel region on sidewalls of the ferroelectric material, the first channel region comprising hydrogen and having a hydrogen concentration of 10²⁰Atoms per cubic centimeter to 10²²Atoms per cubic centimeter;

a source line, wherein a first portion of the source line provides a first source/drain electrode for the first thin film transistor;

a bit line, wherein a first portion of the bit line provides a second source/drain electrode for the first thin film transistor;

a first dielectric material separating the source line and the bit line, wherein the first dielectric material physically contacts the first channel region; and

a second memory cell located above the first memory cell.

9. The memory device of claim 8, wherein the second memory cell comprises a second thin film transistor, wherein a second portion of the source line provides a first source/drain electrode for the second thin film transistor, and wherein a second portion of the bit line provides a second source/drain electrode for the second thin film transistor.

10. A method of forming a memory device, comprising:

patterning a first trench extending through the first conductive line;

depositing a memory film along a bottom surface and sidewalls of the first trench;

depositing an Oxide Semiconductor (OS) layer over the memory film, the OS layer extending along a bottom surface and sidewalls of the first trench;

depositing a first dielectric material over and in contact with the OS layer, wherein depositing the first dielectric material comprises simultaneously applying a first hydrogen-containing precursor at a first flow rate and a second hydrogen-free precursor at a second flow rate of a second flow, and wherein a ratio of the second flow rate of the second hydrogen-free precursor to the first flow rate of the first hydrogen-containing precursor is at least 60; and

a second dielectric material is deposited over the first dielectric material to fill remaining portions of the first trench.

Technical Field

Embodiments of the present application relate to memory cells, memory devices, and methods of forming the same.

Background

Semiconductor memory is used in integrated circuits for electronic applications including radios, televisions, cell phones, and personal computing devices, as examples. Semiconductor memories include two main categories. One is a volatile memory; the other is a non-volatile memory. Volatile memory includes Random Access Memory (RAM), which can be further divided into two subcategories, Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM). Both SRAM and DRAM are volatile because they lose their stored information when power is removed.

On the other hand, nonvolatile memories may hold stored data on them. One type of non-volatile semiconductor memory is ferroelectric random access memory (FeRAM or FRAM). Advantages of FeRAM include fast read/write speed and compact size.

Disclosure of Invention

An embodiment of the present application provides a memory cell comprising: a thin film transistor over a semiconductor substrate, the thin film transistor comprising: a memory film contacting the word line; and an Oxide Semiconductor (OS) layer contacting the source line and the bit line, wherein the memory film is disposed between the OS layer and the word line; and a dielectric material separating the source line and the bit line, wherein the dielectric material forms an interface with the OS layer; wherein the dielectric material comprises hydrogen, and wherein a concentration of hydrogen at the interface between the dielectric material and the OS layer is no more than 3 atomic percent (at%).

Embodiments of the present application also provide a device, comprising: a semiconductor substrate; a first memory cell over the semiconductor substrate, the first memory cell comprising a first thin film transistor, wherein the first thin film transistorThe transistor includes: a gate electrode including a portion of the first word line; a first portion of ferroelectric material located on sidewalls of the first word line; and a first channel region on a sidewall of the ferroelectric material, the first channel region including hydrogen, and a hydrogen concentration of the first channel region being 10²⁰Atoms per cubic centimeter to 10²²Atoms per cubic centimeter; a source line, wherein a first portion of the source line provides a first source/drain electrode for the first thin film transistor; a bit line, wherein a first portion of the bit line provides a second source/drain electrode for the first thin film transistor; a first dielectric material separating the source line and the bit line, wherein the first dielectric material physically contacts the first channel region; and a second memory cell located above the first memory cell.

Embodiments of the present application further provide a method, comprising: patterning a first trench extending through the first conductive line; depositing a memory film along a bottom surface and sidewalls of the first trench; depositing an Oxide Semiconductor (OS) layer over the memory film, the OS layer extending along a bottom surface and sidewalls of the first trench; depositing a first dielectric material over and in contact with the OS layer, wherein depositing the first dielectric material comprises simultaneously applying a first hydrogen-containing precursor at a first flow rate and a second hydrogen-free precursor at a second flow rate of a second flow, and wherein a ratio of the second flow rate of the second hydrogen-free precursor to the first flow rate of the first hydrogen-containing precursor is at least 60; and depositing a second dielectric material over the first dielectric material to fill a remaining portion of the first trench.

Embodiments of the present application provide memory array isolation structures.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

FIGS. 1A, 1B, and 1C illustrate perspective, electrical schematic, and top views of a memory array according to some embodiments.

Fig. 2, 3A, 3B, 4, 5, 6, 7, 8, 9, 10, 11, 12A, 12B, 13, 14, 15, 16, 17A, 17B, 18A, 18B, 19A, 19B, 20, 21, 22A, 22B, 23A, 23B, 23C, 24A, 24B, 24C, 25A, 25B, 25C, 26A, 26B, 26C, 27A, 27B, 27C, 28A, 28B, 28C, and 28D illustrate various diagrams of fabricating memory arrays according to some embodiments.

FIGS. 29, 30 and 31 illustrate various diagrams of a memory array according to some embodiments.

Fig. 32A and 32B illustrate features of a device according to some embodiments.

33A, 33B, 33C, and 33D illustrate embodiments of memory arrays according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Various embodiments provide a 3D memory array having a plurality of vertically stacked memory cells. Each memory cell includes a Thin Film Transistor (TFT) having a word line region as a gate electrode, a bit line region as a first source/drain electrode, and a source line region as a second source/drain electrode. Each TFT also includes an insulating memory film (e.g., as a gate dielectric) and an Oxide Semiconductor (OS) channel region.

1A, 1B, and 1C illustrate examples of memory arrays according to some embodiments. FIG. 1A shows an example of a portion of a memory array 200 in three views; FIG. 1B shows a circuit diagram of memory array 200; FIG. 1C illustrates a top view of the memory array 200 according to some embodiments. The memory array 200 includes a plurality of memory cells 202 that may be arranged in a grid of rows and columns. Memory cells 202 may further be vertically stacked to provide a three-dimensional memory array, thereby increasing device density. The memory array 200 may be disposed in a back end of line (BEOL) of a semiconductor die. For example, the memory array may be disposed in an interconnect layer of a semiconductor die, such as over one or more active devices (e.g., transistors) formed on a semiconductor substrate.

In some embodiments, memory array 200 is a flash memory array, such as a NOR flash memory array or the like. Each memory cell 202 may include a Thin Film Transistor (TFT)204 having the insulated memory film 90 as a gate dielectric. In some embodiments, the gate of each TFT204 is electrically coupled to a respective word line (e.g., lead 72), the first source/drain region of each TFT204 is electrically coupled to a respective bit line (e.g., lead 106), and the second source/drain region of each TFT204 is electrically coupled to a respective source line (e.g., lead 108), which electrically couples the second source/drain region to ground. Memory cells 202 in the same horizontal row of memory array 200 may share a common word line, while memory cells 202 in the same vertical column of memory array 200 may share a common source line and a common bit line.

The memory array 200 includes a plurality of vertically stacked conductive lines 72 (e.g., word lines), and the dielectric layer 52 is disposed between adjacent conductive lines 72. The wires 72 extend in a direction parallel to the major surface of the underlying substrate (not explicitly shown in fig. 1A and 1B). The wires 72 may have a stepped configuration such that the lower wire 72 is longer than the upper wire 72 and extends laterally beyond the end points of the upper wire 72. For example, in fig. 1A, multiple stacked layers of wires 72 are shown, with the topmost wire 72 being the shortest and the bottommost wire 72 being the longest. The respective lengths of the wires 72 may increase in a direction toward the underlying substrate. In this manner, portions of each conductive line 72 may be accessed from above the memory array 200, and conductive contacts may be made to the exposed portions of each conductive line 72.

Memory array 200 also includes a plurality of conductive lines 106 (e.g., bit lines) and conductive lines 108 (e.g., source lines). Wires 106 and 108 may each extend in a direction perpendicular to wire 72. Dielectric material 98 is disposed between and isolates adjacent conductive lines 106 and 108. In some embodiments, at least a portion of the dielectric material 98 is a low hydrogen material formed using a hydrogen-containing precursor introduced at a reduced flow rate. For example, at least a portion of dielectric material 98 (e.g., dielectric material 98A) that physically contacts Oxide Semiconductor (OS) layer 92 (described below) may have a relatively low hydrogen concentration, such as less than 3 atomic percent (at%). A low hydrogen concentration (e.g., within the above range) may reduce hydrogen diffusion into the OS layer 92, thereby reducing defects and improving device stability. For example, by reducing hydrogen diffusion with the dielectric material 98 of an embodiment, the threshold voltage (Vth) curve of the TFT204 may be shifted in the positive bias direction, enhancing the stability of the TFT 204. A relatively low hydrogen concentration may be achieved in the dielectric material 98 by, for example, reducing the flow rate of the hydrogen-containing precursor used to deposit the dielectric material 98. For example, in embodiments where dielectric material 98 comprises silicon oxide, silicon nitride, or the likeMay be prepared by having a relatively low SiH₄The precursor flow rate process deposits material 98 to suppress H^oOr H⁺Into dielectric material 98 and OS layer 92.

Pairs of conductive lines 106 and 108 and intersecting conductive lines 72 define the boundaries of each memory cell 202, and dielectric material 102 is disposed between and separates adjacent pairs of conductive lines 106 and 108. In some embodiments, the conductive line 108 is electrically coupled to ground. Although fig. 1A shows a particular arrangement of wires 106 relative to wires 108, it should be understood that in other embodiments, the arrangement of wires 106 and 108 may be reversed.

As described above, the memory array 200 may also include an Oxide Semiconductor (OS) layer 92. The OS layer 92 may provide a channel region for the memory cell 202 of the TFT 204. For example, the region of the OS layer 92 that intersects a conductive line 72 may allow current to flow from conductive line 106 to conductive line 108 (e.g., in the direction shown by arrow 206) when an appropriate voltage is applied through the respective conductive line 72 (e.g., above the respective threshold voltage (Vth) of the respective TFT 204). The OS layer 92 may have a relatively low hydrogen concentration, such as measured by time-of-flight secondary ion mass spectrometry (ToF-SIMS) analysis, at about 10²⁰To about 10²²Atoms per cubic centimeter. As a result, the stability of the TFT204 can be improved as compared with a TFT having an OS layer with a higher hydrogen concentration.

Memory film 90 is disposed between conductive line 72 and OS layer 92, and memory film 90 may provide a gate dielectric for TFT 204. In some embodiments, memory film 90 comprises a ferroelectric material such as hafnium oxide, hafnium zirconium oxide, silicon doped hafnium oxide, and the like. Accordingly, memory array 200 may also be referred to as a ferroelectric random access memory (FERAM) array. Alternatively, the memory film 90 may be a film including two SiO layers_xSiN between layers (e.g., ONO structure)_xA multilayer structure of layers, different ferroelectric materials, different types of memory layers (e.g., capable of storing bits), etc.

In embodiments where memory film 90 comprises a ferroelectric material, memory film 90 may be polarized in one of two different directions, and the polarization direction may be changed by applying an appropriate voltage difference across memory film 90 and generating an appropriate electric field. The polarization may be relatively local (e.g., typically contained within each boundary of the memory cell 202), and a continuous region of the memory film 90 may extend across multiple memory cells 202. Depending on the polarization direction of a specific region of the memory film 90, the threshold voltage of the corresponding TFT204 changes, and a digital value (e.g., 0 or 1) may be stored. For example, when a region of the memory film 90 has a first electrical polarization direction, the corresponding TFT204 may have a relatively low threshold voltage, and when a region of the memory film 90 has a second electrical polarization direction, the corresponding TFT204 may have a relatively high threshold voltage. The difference between the two threshold voltages may be referred to as a threshold voltage shift. A larger threshold voltage shift makes it easier (e.g., less error prone) to read the digital value stored in the corresponding memory cell 202.

In such an embodiment, in order to perform a write operation on the memory cell 202, a write voltage may be applied on the entire portion of the memory film 90 corresponding to the memory cell 202. The write voltages may be applied, for example, by applying appropriate voltages to respective conductive lines 72 (e.g., word lines) and respective conductive lines 106/108 (e.g., bit/source lines). By applying a write voltage over the entire portion of the memory film 90, the polarization direction of a region of the memory film 90 can be changed. As a result, the respective threshold voltage of the respective TFT204 may also be switched from a low threshold voltage to a high threshold voltage, or vice versa, and a digital value may be stored in the memory cell 202. Because conductive line 72 intersects conductive lines 106 and 108, individual memory cells 202 may be selected for write operations.

In such an embodiment, to perform a read operation on memory cell 202, a read voltage (a voltage between a low threshold voltage and a high threshold voltage) is applied to a respective conductive line 72 (e.g., a word line). The TFT204 of the memory cell 202 may be conductive or non-conductive depending on the polarization direction of the corresponding region of the memory film 90. As a result, conductive line 106 may or may not discharge through conductive line 108 (e.g., a source line electrically coupled to ground), and a digital value stored in memory cell 202 may be determined. Because conductive line 72 intersects conductive lines 106 and 108, individual memory cells 202 may be selected for read operations.

FIG. 1A further illustrates a reference cross section of a memory array 200 used in subsequent figures. The section B-B' is along the longitudinal axis of the conductive line 72 and in a direction, for example, parallel to the current flow direction of the TFT 204. Section C-C 'is perpendicular to section B-B' and perpendicular to the longitudinal axis of wire 72. Section C-C' extends through the wire 106. Section D-D 'is parallel to section C-C' and extends through dielectric material 102. For clarity, the subsequent figures refer to these reference sections.

In fig. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, and the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. Substrate 50 may be a wafer such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. An insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates such as multilayer substrates or gradient substrates may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide, an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium phosphide, and/or indium gallium arsenide phosphide, or a combination thereof.

Fig. 2 further illustrates circuitry that may be formed over substrate 50. The circuit includes active devices (e.g., transistors) at the top surface of the substrate 50. The transistor may include a gate dielectric layer 202 over the top surface of the substrate 50 and a gate electrode 204 over the gate dielectric layer 202. Source/drain regions 206 are disposed in substrate 50 on opposite sides of gate dielectric layer 202 and gate electrode 204. Gate spacers 208 are formed along sidewalls of the gate dielectric layer 202 and separate the source/drain regions 206 from the gate electrode 204 by an appropriate lateral distance. In some embodiments, the transistor may be a planar Field Effect Transistor (FET), a fin field effect transistor (finFET), a nano field effect transistor (nanoFET), or the like.

The first ILD 210 surrounds and isolates the source/drain regions 206, the gate dielectric layer 202 and the gate electrode 204, and the second ILD212 is positioned above the first ILD 210. A source/drain contact 214 extends through the second ILD212 and the first ILD 210 and is electrically coupled to the source/drain region 206, and a gate contact 216 extends through the second ILD212 and is electrically coupled to the gate electrode 204. An interconnect structure 220, including one or more stacked dielectric layers 224 and conductive features 222 formed in the one or more dielectric layers 224, is located over the second ILD212, source/drain contacts 214 and gate contacts 216. Although fig. 2 illustrates two stacked dielectric layers 224, it should be understood that the interconnect structure 200 may include any number of dielectric layers 224 having conductive features 222 disposed therein. Interconnect structure 220 may be electrically connected to gate contact 216 and source/drain contact 214 to form a functional circuit. In some embodiments, the functional circuitry formed by interconnect structure 220 may include logic circuitry, memory circuitry, sense amplifiers, controllers, input/output circuitry, image sensor circuitry, and the like, or combinations thereof. Although fig. 2 discusses transistors formed over substrate 50, other active devices (e.g., diodes, etc.) and/or passive devices (e.g., capacitors, resistors, etc.) may be formed as part of the functional circuitry.

In fig. 3A and 3B, a multilayer stack 58 is formed over the structure of fig. 2. The substrate 50, transistors, ILD, and interconnect structures 120 may be omitted from subsequent figures for simplicity and clarity. Although multi-layer stack 58 is shown contacting dielectric layer 224 of interconnect structure 220, any number of intervening layers may be disposed between substrate 50 and the multi-layer stack 58. For example, one or more additional interconnect layers including conductive features in an insulating layer (e.g., a low-k dielectric layer) may be disposed between the substrate 50 and the multilayer stack 58. In some embodiments, the conductive features may be patterned to provide power, ground, and/or signal lines for active devices on the substrate 50 and/or the memory array 200 (see fig. 1A and 1B).

Multilayer stack 58 includes alternating layers of conductive lines 72A-D (collectively referred to as conductive layers 54) and dielectric layers 52A-C (collectively referred to as dielectric layers 52). The conductive layer 54 may be patterned in a subsequent step to define conductive lines 72 (e.g., word lines). Conductive layer 54 may comprise a conductive material such as copper, titanium nitride, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, and the like, and dielectric layer 52 may comprise an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, and the like. Conductive layer 54 and dielectric layer 52 may each be formed using, for example, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), plasma enhanced CVD (pecvd), or the like. Although fig. 3A and 3B show a particular number of conductive layers 54 and dielectric layers 52, other embodiments may include a different number of conductive layers 54 and dielectric layers 52.

Fig. 4-12B are diagrams of intermediate stages in fabricating a staircase structure of memory array 200, according to some embodiments. Fig. 4 to 11 and 12B are shown along a reference section B-B' shown in fig. 1. Fig. 12A is shown in a three-dimensional view.

In fig. 4, a photoresist 56 is formed over the multilayer stack 58. As described above, multilayer stack 58 may include alternating layers of conductive layers 54 (labeled 54A, 54B, 54C, and 54D) and dielectric layers 52 (labeled 52A, 52B, and 52C). The photoresist 56 may be formed by using a spin coating technique.

In fig. 5, photoresist 56 is patterned to expose multilayer stack 58 in region 60 while masking the remaining portions of multilayer stack 58. For example, the topmost layer of multilayer stack 58 (e.g., conductive layer 54D) may be exposed in region 60. The photoresist 56 may be patterned using acceptable photolithography techniques.

In fig. 6, the exposed portions of multilayer stack 58 in region 60 are etched using photoresist 56 as a mask. The etching may be any acceptable etching process, such as by wet or dry etching, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), and the like, or combinations thereof. The etching may be anisotropic. The etch may remove portions of conductive layer 54D and dielectric layer 52C in region 60 and define opening 61. Because conductive layer 54D and dielectric layer 52C have different material compositions, the etchant used to remove the exposed portions of these layers may be different. In some embodiments, dielectric layer 52C acts as an etch stop while conductive layer 54D is etched, and conductive layer 54C acts as an etch stop while dielectric layer 52C is etched. As a result, portions of conductive layer 54D and dielectric layer 52C may be selectively removed without removing the remaining layers of multilayer stack 58, and opening 61 may extend to a desired depth. Alternatively, a timed etch process may be used to stop etching of openings 61 after openings 61 reach a desired depth. In the resulting structure, conductive layer 54C is exposed in region 60.

In fig. 7, the photoresist 56 is trimmed to expose additional portions of the multilayer stack 58. The photoresist may be trimmed using acceptable photolithography techniques. As a result of trimming, the width of photoresist 56 is reduced and portions of multilayer stack 58 in regions 60 and 62 may be exposed. For example, a top surface of conductive layer 54C may be exposed in region 60 and a top surface of conductive layer 54D may be exposed in region 62.

In fig. 8, portions of conductive layer 54D, dielectric layer 52C, conductive layer 54C, and dielectric layer 52B in regions 60 and 62 are removed by an acceptable etch process using photoresist 56 as a mask. The etching may be any acceptable etching process, such as by wet or dry etching, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), and the like, or combinations thereof. The etching may be anisotropic. The etch may extend opening 61 further into multilayer stack 58. Because conductive layers 54D/54C and dielectric layers 52C/52B have different material compositions, the etchant used to remove the exposed portions of these layers may be different. In some embodiments, dielectric layer 52C acts as an etch stop while conductive layer 54D is etched, and conductive layer 54C acts as an etch stop while dielectric layer 52C is etched; dielectric layer 52B acts as an etch stop while conductive layer 54C is etched; and conductive layer 54B acts as an etch stop while dielectric layer 52B is etched. As a result, portions of conductive layers 54D/54C and dielectric layers 52C/52B may be selectively removed without removing the remaining layers of multilayer stack 58, and opening 61 may extend to a desired depth. Further, during the etching process, the unetched portions of conductive layer 54 and dielectric layer 52 act as a mask for the underlying layers, and as a result, the previous pattern of conductive layer 54D and dielectric layer 52C can be transferred to underlying conductive layer 54C and dielectric layer 52B. In the resulting structure, conductive layer 54B is exposed in region 60 and conductive layer 54C is exposed in region 62.

In fig. 9, the photoresist 56 is trimmed to expose additional portions of the multilayer stack 58. The photoresist may be trimmed using acceptable photolithography techniques. As a result of trimming, the width of photoresist 56 is reduced and portions of multilayer stack 58 in regions 60, 62, and 64 may be exposed. For example, a top surface of conductive layer 54B may be exposed in region 60; a top surface of conductive layer 54C may be exposed in region 62; and a top surface of conductive layer 54D may be exposed in region 64.

In fig. 10, portions of conductive layers 54D, 54C, and 54B in regions 60, 62, and 64 are removed by an acceptable etch process using photoresist 56 as a mask. The etching may be any acceptable etching process, such as by wet or dry etching, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), and the like, or combinations thereof. The etching may be anisotropic. The etch may extend opening 61 further into multilayer stack 58. In some embodiments, dielectric layer 52C acts as an etch stop while conductive layer 54D is etched; dielectric layer 52B acts as an etch stop while conductive layer 54C is etched; and dielectric layer 52A acts as an etch stop while conductive layer 54B is etched. As a result, portions of conductive layers 54D, 54C, and 54B may be selectively removed without removing the remaining layers of multilayer stack 58, and opening 61 may extend to a desired depth. Further, during the etching process, each dielectric layer 52 acts as a mask for the underlying layers, and as a result, previous patterns of dielectric layers 52C/52B (see fig. 9) may be transferred to the underlying conductive layers 54C/54B. In the resulting structure, dielectric layer 52A is exposed in region 60; dielectric layer 52B is exposed in region 62; and dielectric layer 52C is exposed in region 64.

In fig. 11, the photoresist 56 may be removed, such as by an acceptable ashing or wet strip process. Thus, the stepped structure 68 is formed. The stair-step structure comprises a stack of alternating conductive layers 54 and dielectric layers 52. Lower conductive layer 54 is wider and extends laterally beyond upper conductive layer 54, and the width of each conductive layer 54 increases in the direction toward substrate 50. For example, conductive layer 54A may be longer than conductive layer 54B; conductive layer 54B may be longer than conductive layer 54C; and conductive layer 54C may be longer than conductive layer 54D. As a result, conductive contacts to each conductive layer 54 may be made from above the stair-step structure 68 in subsequent process steps.

In fig. 12, an inter-metal dielectric (IMD)70 is deposited over multilayer stack 58. IMD70 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (pecvd), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), Undoped Silicate Glass (USG), and the like. Other insulating materials formed by any acceptable process may be used. IMD70 extends along the sidewalls of conductive layer 54 and the sidewalls of dielectric layer 52. Further, IMD70 may contact the top surface of each dielectric layer 52.

As further shown in fig. 12, a removal process is then applied to IMD70 to remove excess dielectric material located over multilayer stack 58. In some embodiments, a planarization process such as Chemical Mechanical Polishing (CMP), an etch back process, combinations thereof, and the like may be utilized. The planarization process exposes multilayer stack 58 such that the top surfaces of IMD70 and multilayer stack 58 are horizontal after the planarization process is complete.

Fig. 13-17B are diagrams of intermediate stages in the manufacture of memory array 200 according to some embodiments. In fig. 13 to 17B, the multilayer stack 58 is formed, and a groove is formed in the multilayer stack 58, thereby defining the wire 72. Conductive lines 72 may correspond to word lines in memory array 200, and conductive lines 72 may further provide gate electrodes for the resulting TFTs of memory array 200. Fig. 17A is shown in a three-dimensional view. Fig. 13 to 16 and 17B are shown along the reference section C-C' shown in fig. 1A.

In fig. 13, a hard mask 80 and photoresist 82 are deposited over multilayer stack 58. The hard mask layer 80 may comprise, for example, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. For example, the photoresist 82 may be formed by using a spin coating technique.

In fig. 14, photoresist 82 is patterned to form trenches 86. The photoresist may be patterned using acceptable photolithography techniques. For example, the photoresist 82 is exposed to light for patterning. After the exposure process, the photoresist 82 is developed to remove either the exposed or unexposed portions of the photoresist, depending on whether a negative or positive resist is used, to define the pattern that forms the trenches 86.

In fig. 15, the pattern of photoresist 82 is transferred to hard mask 80 using an acceptable etch process, such as by wet or dry etching, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), or the like, or combinations thereof. The etching may be anisotropic. Thus, trenches 86 are formed that extend through hard mask 80. For example, the photoresist 82 may be removed by an ashing process.

In fig. 16, the pattern of hard mask 80 is transferred to multilayer stack 58 using one or more acceptable etching processes, such as by wet or dry etching, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), or the like, or combinations thereof. The etching may be anisotropic. Accordingly, trenches 86 extend through multilayer stack 58, and conductive lines 72 (e.g., word lines) are formed from conductive layer 54. Adjacent conductive lines 72 may be spaced apart from one another by etching trenches 86 through conductive layer 54. Subsequently, in fig. 17A and 17B, the hard mask 80 may then be removed by an acceptable process such as a wet etching process, a dry etching process, a planarization process, a combination thereof, and the like. Due to the stepped shape of the multilayer stack 58 (see, e.g., fig. 12), the wires 72 may have varying lengths that increase in a direction toward the substrate 50. For example, wire 72A may be longer than wire 72B; wire 72B may be longer than wire 72C; and wire 72C may be longer than wire 72D.

Fig. 18A to 23C illustrate the formation and patterning of a channel region for the TFT204 (see fig. 1A) located in the trench 86. Fig. 18A, 19A, and 23A are shown in three-dimensional views. Cross-sectional views along line C-C of fig. 1A are provided in fig. 18B, fig. 19B, fig. 20, fig. 21, fig. 22A, fig. 22B, and fig. 23B. Fig. 23C shows a corresponding top view of the TFT structure.

In fig. 18A and 18B, a memory film 90 is conformally deposited in the trenches 86. The memory film 90 may be of a material capable of storing bits, such as a material capable of switching between two different polarization directions by applying an appropriate voltage difference across the memory film 90. For example, the polarization of the memory film 90 may change due to an electric field generated by the applied voltage difference.

For example, the memory film 90 may be a high-k dielectric material, such as a hafnium-based (Hf) dielectric material. In some embodiments, memory film 90 comprises a ferroelectric material such as hafnium oxide, hafnium zirconium oxide, silicon doped hafnium oxide, and the like. In other embodiments, memory 90 may be a multi-layer structure (e.g., an ONO structure) including a SiN x layer disposed between two SiOx layers. In other embodiments, memory film 90 may include different ferroelectric materials or different types of memory materials. The memory film 90 may be deposited by CVD, PVD, ALD, PECVD, etc. to extend along the sidewalls and bottom surfaces of the trench 86. After deposition of the memory film 90, an annealing step (e.g., in a temperature range of about 300 ℃ to 600 ℃) may be performed to achieve the desired crystalline phase, improve film quality and reduce film-related defects/impurities for the memory film 90. In some embodiments, the annealing step may be further below 400 ℃ to meet the BEOL thermal budget and reduce defects that may result from high temperature annealing processes leading to other components.

In fig. 19A and 19B, an OS layer 92 is conformally deposited in the trench 86 over the memory film 90. The OS layer 92 comprises a material suitable for providing a channel region for a TFT (e.g., TFT204, see fig. 1A). In some embodiments, the OS layer 92 comprises an indium-containing material, such as In_xGa_yZn_zMO, wherein M may be Ti, Al, Ag, Si, Sn, etc. X, Y and Z can each be any value between 0 and 1. In other embodiments, different semiconductor materials may be used for the OS layer 92. Can be formed by CVD, PVD,ALD, PECVD, etc. deposit OS layer 92. The OS layer 92 may extend along the sidewalls and bottom of the trench 86 above the FE layer 90. After deposition of OS layer 92, an annealing step may be performed in an oxygen-related ambient (e.g., at a temperature in a range of about 300 ℃ to about 450 ℃ or in a range of about 300 ℃ to about 400 ℃) to activate charge carriers of OS layer 92.

In fig. 20, a dielectric material 98A is deposited on the sidewalls and floor of the trench 86 and over the OS layer 92. The dielectric material 98A may include, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. In some embodiments, depositing the dielectric material 98A may include reducing the flow rate of the hydrogen-containing precursor, thereby resulting in the formation of a dielectric material 98A having a relatively low hydrogen concentration. For example, in embodiments in which the dielectric material 98A is a silicon-containing insulating material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.), a first hydrogen-containing precursor (e.g., Silane (SiH) may be simultaneously applied during the deposition process₄) Tetraethyl silicate (TEOS), etc.) and a second hydrogen-free precursor. Because the first hydrogen-containing precursor is used. When the dielectric material 98A comprises silicon oxide, the second hydrogen-free precursor can be, for example, N₂O, and when the dielectric material 98A comprises silicon nitride, the second hydrogen-free precursor may be, for example, NH₃. Using a first flow rate of a hydrogen-containing precursor, hydrogen ions (e.g., H)⁺) And/or hydrogen species (H)^o) May diffuse through dielectric material 98A into OS layer 92, causing instability in the resulting transistor. Accordingly, various embodiments improve the stability of the transistor by reducing the flow rate of the first hydrogen-containing precursor. For example, the ratio of the flow rate of the second hydrogen-free precursor to the flow rate of the first hydrogen-containing precursor can be at least 60. It has been observed that maintaining the precursor flow rate within the above ratio, hydrogen diffusion into OS layer 92 can be reduced to a desired level and device stability can be improved.

In some embodiments, after depositing the dielectric material 98A, the OS layer 92 may have a hydrogen concentration of about 10 as measured by time-of-flight secondary ion mass spectrometry (ToF-SIMS)²⁰Atoms per cubic centimeter to about 10²²Atoms per cubic centimeter. FIG. 32A illustrates an OS layer 92 and dielectric material according to some embodimentsGraph 300 of hydrogen concentration (e.g., curve 302) in 98A. In the graph 300, the x-axis represents the sputtering time corresponding to the detection time (e.g., distance) during the TOF-SIMs analysis. By maintaining the hydrogen concentration of the OS layer 92 within this range, the threshold voltage characteristic curve of the resulting transistor 204 can be shifted in the forward bias direction, enhancing the stability of the transistor. For example, fig. 32B shows a graph 304 depicting a threshold voltage characteristic 306 of a first transistor and a threshold voltage characteristic 308 of a second transistor. The first transistor (e.g., corresponding to curve 306) has a channel region (e.g., an OS layer) having a hydrogen concentration exceeding the above range, and the second transistor (e.g., corresponding to curve 308) has a channel region having a hydrogen concentration within the above range. Arrow 310 represents a positive bias direction shift of threshold voltage characteristic 308 as compared to threshold voltage characteristic 306.

As a result of the example deposition process, the hydrogen concentration in the dielectric material 98A may be relatively low. For example, when the dielectric material 98A comprises silicon oxide (e.g., SiO)_x) When the hydrogen concentration of the dielectric material 98A may be more than 0 and less than 5 at%. As another example, when dielectric material 98A comprises silicon nitride (e.g., SiN)_x) When desired, the total hydrogen concentration of the dielectric material 98A may be greater than 0 and less than 10 at%. The total hydrogen concentration at the interface 96 between the OS layer 92 and the dielectric material 98A may be less than about 3 at%. Maintaining the hydrogen concentration of the dielectric material 98A within these ranges may achieve advantages such as reduced diffusion into the OS layer 92 and improved transistor stability.

In fig. 21, the bottom of dielectric material 98A in trench 86 is removed, for example, using a combination of lithography and etching. The etching may be any acceptable etching process, such as by wet or dry etching, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), and the like, or combinations thereof. The etching may be anisotropic.

Subsequently, as also shown in fig. 21, the dielectric material 98A may be used as an etch mask to etch through the bottom of the OS layer 92 in the trench 86. The etching may be any acceptable etching process, such as by wet or dry etching, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), and the like, or combinations thereof. The etching may be anisotropic. Etching the OS layer 92 may expose a portion of the memory film 90 located on the bottom surface of the trench 86. Accordingly, the portions of OS layer 92 located on opposing sidewalls of trench 86 may be spaced apart from each other, which improves isolation between memory cells 202 of memory array 200 (see fig. 1A).

In fig. 22A and 22B, additional dielectric material 98B or dielectric material 98C may be deposited to fill the remaining portion of trench 86. In the embodiment of fig. 22A, dielectric material 98B may have the same material composition and be formed using a similar process as dielectric material 98A. For example, the dielectric material 98B may be formed using a deposition process with a relatively low flow rate of a hydrogen-containing precursor. In some embodiments, the dielectric material 98B may be formed using a deposition process in which there is no hydrogen precursor (e.g., N)₂O) flow rate with a hydrogen-containing precursor (e.g., SiH)₄) Is at least 60. In some embodiments, the respective ratios of the flow rate of the hydrogen-free precursor to the flow rate of the hydrogen-containing precursor for depositing the dielectric material 98B and depositing the dielectric material 98A may be the same. As a result, the hydrogen concentration of the dielectric material 98B is relatively low. For example, when the dielectric material 98B comprises silicon oxide (e.g., SiO)_x) When desired, the total hydrogen concentration of the dielectric material 98B may be greater than 0 and less than 5 at%. As another example, when dielectric material 98B comprises silicon nitride (e.g., SiN)_x) When desired, the total hydrogen concentration of the dielectric material 98B may be greater than 0 and less than 10 at%.

Fig. 22B shows an alternative embodiment of memory array 200' in which dielectric material 98C is deposited to fill the remaining portions of trenches 86 instead of dielectric material 98B. Dielectric material 98C may have a different material composition than dielectric material 98A and may be formed using a different process than dielectric material 98A. The dielectric material 98C may include, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. However, depositing the dielectric material 98C may include increasing the inflow of the hydrogen-containing precursor as compared to the dielectric material 98A. As a result, the dielectric material 98C is formed with a relatively high hydrogen concentration. For example, in embodiments where dielectric material 98C is a silicon-containing insulating material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.)A third hydrogen-containing precursor (e.g., SiH) may be flowed simultaneously during the deposition process₄TEOS, etc.) and a fourth hydrogen-free precursor. When the dielectric material 98C comprises silicon oxide, the fourth hydrogen-free precursor can be, for example, N₂O, and when the dielectric material 98C comprises silicon nitride, the fourth hydrogen-free precursor may be, for example, NH₃. For example, the ratio of the flow rate of the second hydrogen-free precursor to the flow rate of the first hydrogen-containing precursor may be greater than 60, such as up to 70. It has been observed that maintaining the precursor flow rates at the above ratios, the hydrogen concentration of dielectric material 98C may be greater than the hydrogen concentration of dielectric material 98A. For example, when the dielectric material 98C comprises silicon oxide (e.g., SiO)_x) When the total hydrogen concentration of the dielectric material 98C may be about 1X 10²¹Atom/cm³To 1X 10²²Atom/cm³Within the range of (1). As another example, when dielectric material 98C comprises silicon nitride (e.g., SiN)_x) When the total hydrogen concentration of the dielectric material 98C may be greater than 1 × 10²²Atom/cm³. Because the relatively low hydrogen concentration dielectric material 98A separates the relatively high hydrogen concentration dielectric material 98C from the OS layer 92, the high hydrogen concentration in the dielectric material 98C may not significantly degrade the device performance of the resulting transistor, and the benefits described above may still be realized.

For ease of illustration, subsequent figures illustrate further processing based on the embodiment of fig. 22A (e.g., where dielectric material 98B and dielectric material 98A have the same material composition). Dielectric material 98B and dielectric material 98A may be collectively referred to hereinafter as dielectric material 98. It should be understood that a similar process may be applied to the embodiment of fig. 22B (e.g., where dielectric material 98C and dielectric material 98A have different material compositions). Fig. 33A-33C illustrate a memory array 200' according to the embodiment of fig. 22B.

In fig. 23A-23C, a removal process is then applied to dielectric material 98, OS layer 92, and memory film 90 to remove excess material located over multilayer stack 58. In some embodiments, a planarization process such as Chemical Mechanical Polishing (CMP), an etch back process, combinations thereof, and the like may be utilized. The planarization process exposes the multilayer stack 58 such that the top surface of the multilayer stack 58 is horizontal after the planarization process is complete. Fig. 23C shows a corresponding top view of the structure shown in fig. 23A.

Fig. 24A-27C illustrate intermediate steps in fabricating conductive lines 106 and 108 (e.g., source lines and bit lines) in memory array 200. Conductive lines 106 and 108 may extend in a direction perpendicular to conductive line 72 so that individual cells of memory array 200 may be selected for read and write operations. In fig. 24A to 27C, the figures ending with "a" show a 3D view. The figure ending with "B" shows a top view and the figure ending with "C" shows a corresponding cross-sectional view parallel to the line C-C' of fig. 1A.

In fig. 24A, 24B, and 24C, trench 100 is patterned to pass through OS layer 92 and dielectric material 98 (including dielectric material 98A and dielectric material 98B). FIG. 24C shows a cross-sectional view of line C-C' in FIG. 24B. For example, the patterning of the trench 100 may be performed by a combination of photolithography and etching. The trench 100 may be disposed between opposing sidewalls of the memory film 90, and the trench 100 may physically separate adjacent stacks of memory cells in a memory array 200 (see fig. 1A).

In fig. 25A, 25B and 25C, a dielectric material 102 is deposited in the trench 100 and fills the trench 100. FIG. 25C shows a cross-sectional view of line C-C' in FIG. 25B. The dielectric layer 102 may comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. Dielectric layer 102 may extend along the sidewalls and bottom surfaces of trench 86 over OS layer 92. After deposition, a planarization process (e.g., CMP, etchback, etc.) may be performed to remove excess portions of the dielectric material 102. In the resulting structure, the top surfaces of multilayer stack 58, memory film 90, OS layer 92, and dielectric material 102 may be substantially horizontal (e.g., within process variations). In some embodiments, the materials of dielectric materials 98 and 102 may be selected such that they may be selectively etched with respect to each other. For example, in some embodiments, the dielectric material 98 is an oxide and the dielectric material 102 is a nitride. In some embodiments, the dielectric material 98 is a nitride and the dielectric material 102 is an oxide. Other materials are also possible.

In fig. 26A, 26B, and 26C, the trench 104 is patterned for the conductive lines 106 and 108. FIG. 26C shows a cross-sectional view of line C-C' in FIG. 26B. The trench 104 is patterned by patterning the dielectric material 98 (including dielectric material 98A and dielectric material 98C) using, for example, a combination of photolithography and etching.

For example, photoresist 118 may be deposited over multilayer stack 58, dielectric material 98, dielectric material 102, OS layer 92, and memory film 90. The photoresist 118 may be formed by using, for example, a spin coating technique. The photoresist 118 is patterned to define openings 120. Each opening 120 may overlap a respective region of dielectric material 102, and each opening 120 may further partially expose two spaced apart regions of dielectric material 98. For example, each opening 120 may expose a region of the dielectric material 102; partially exposing a first region of dielectric material 98; and a second region of partially exposed dielectric material 98 that is spaced apart from the first region of dielectric material 98 by a region of dielectric material 102. In this manner, each opening 120 may define a pattern of conductive lines 106 and adjacent conductive lines 108 spaced apart by dielectric material 102. Acceptable photolithography techniques can be used to pattern the photoresist. For example, the photoresist 120 is exposed to light for patterning. After the exposure process, the photoresist 118 may be developed to remove either the exposed or unexposed portions of the photoresist, depending on whether a negative or positive resist is used, to define the pattern of openings 120 formed.

Subsequently, the portion of dielectric material 98 exposed by opening 122 may be removed by, for example, etching. The etching may be any acceptable etching process, such as by wet or dry etching, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), and the like, or combinations thereof. The etching may be anisotropic. The etching process may use an etchant that etches the dielectric material 98 without significantly etching the dielectric material 102. As a result, even if the opening 122 exposes the dielectric material 102, the dielectric material 102 may not be significantly removed. The pattern of the trench 104 may correspond to the conductive lines 106 and 108 (see fig. 27A, 27B, and 27C). For example, a portion of the dielectric material 98 between each pair of trenches 104 may remain, and the dielectric material 102 may be disposed between adjacent pairs of trenches 104. After patterning the trench 104, the photoresist 118 may be removed by, for example, ashing.

In fig. 27A, 27B, and 27C, the trench 104 is filled with a conductive material to form conductive lines 106 and 108. Fig. 27C shows a cross-sectional view of line C-C' in fig. 27B. The conductive lines 106 and 108 may each comprise a conductive material, such as copper, titanium nitride, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, and the like, which may each be formed using, for example, CVD, ALD, PVD, PECVD, and the like. After depositing conductive lines 106 and 108, planarization (e.g., CMP, etchback, etc.) may be performed to remove excess portions of the conductive material to form conductive lines 106 and 108. In the resulting structure, the top surfaces of multilayer stack 58, memory film 90, OS layer 92, conductive lines 106, and conductive lines 108 may be substantially horizontal (e.g., within process variations). Conductive line 106 may correspond to a bit line in a memory array and conductive line 108 may correspond to a source line in memory array 200. Although fig. 27C shows a cross-sectional view showing only wire 106, the cross-sectional view of wire 108 may be similar.

Thus, stacked TFTs 204 may be formed in the memory array 200. Each TFT204 includes a gate electrode (e.g., a portion of a respective conductive line 72), a gate dielectric (e.g., a portion of a respective memory film 90), a channel region (e.g., a portion of a respective OS layer 92), and source and drain electrodes (e.g., portions of respective conductive lines 106 and 108). The dielectric material 102 isolates adjacent TFTs 204 in the same column and on the same vertical level. The TFTs 204 may be arranged in an array of vertically stacked rows and columns.

In fig. 28A, 28B, 28C, and 28D, contacts 110 are made to the wires 72, 106, and 108. FIG. 28A shows a perspective view of memory array 200; FIG. 28B shows a top view of the memory array 200; and FIG. 28C shows a cross-sectional view of the device and underlying substrate along line 28C '-28C' of FIG. 28A. Fig. 28D shows a cross-sectional view of the device along line B-B' of fig. 1A. In some embodiments, the stepped shape of the wires 72 may provide a surface on each wire 72 for the conductive contact 110 to land on. Forming contacts 110 may include patterning openings in IMD70 and dielectric layer 52 to expose portions of conductive layer 54 using, for example, a combination of photolithography and etching. A liner (not shown) such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the opening. The liner may comprise titanium, titanium nitride, tantalum nitride, and the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process such as CMP may be performed to remove excess material from the surface of IMD 70. The remaining pad and conductive material form a contact 110 in the opening.

As also shown in the perspective view of fig. 28A, conductive contacts 112 and 114 may be made to the leads 106 and 108, respectively. The conductive contacts 110, 112, and 114 may be electrically connected to wires 116A, 116B, and 116C, respectively, which connect the memory array to underlying/overlying circuitry (e.g., control circuitry) and/or signal, power, and ground lines in the semiconductor die. For example, conductive vias 118 may extend through IMD70 to electrically connect leads 116C to the underlying circuitry of interconnect structure 220 and active devices located on substrate 50, as shown in fig. 28C. Other conductive vias may be formed through IMD70 to electrically connect leads 116A and 116B to the underlying circuitry of interconnect structure 220. In alternative embodiments, routing and/or power lines to and from the memory array may be provided by interconnect structures formed over the memory array 200 in addition to or in place of the interconnect structures 220. Thus, the memory array 200 may be completed.

Although the embodiments of fig. 2-28B show specific patterns for the conductive lines 106 and 108, other configurations are possible. For example, in these embodiments, the conductive lines 106 and 108 have a staggered pattern. In some embodiments, the conductive lines 106 and 108 in the same row of the array are all aligned with each other. Fig. 29 shows a top view, and fig. 30 shows a cross-sectional view along line C-C' of fig. 29. Fig. 31 shows a cross-sectional view along line D-D' of fig. 29. In fig. 29, 30 and 31, like reference numerals denote like elements formed by a similar process to those of fig. 2 to 28B.

Fig. 33A, 33B, 33C, and 33D illustrate a memory array 200' according to an alternative embodiment described and illustrated above with respect to fig. 22B. FIG. 33A shows a perspective view of the memory array 200; FIG. 33B shows a top view of the memory array 200; FIG. 33C illustrates a cross-sectional view of the underlying substrate and device along line 30C '-30C' of FIG. 33A; and FIG. 33D shows a cross-sectional view of the device along line B-B' of FIG. 1A. Memory array 200' may be similar to memory array 200, wherein like reference numbers refer to like elements formed using like processes. However, the dielectric material 98B is replaced with a dielectric material 98C, and the dielectric material 98C has a different material composition than the dielectric material 98A. For example, as described above, the hydrogen concentration of the dielectric material 98C may be higher than the hydrogen concentration of the dielectric material 98A. This may be accomplished, for example, by increasing the flow rate of the hydrogen-containing precursor while depositing the dielectric material 98C as compared to depositing the dielectric material 98A.

Various embodiments provide a 3D memory array with vertically stacked memory cells. Each memory cell includes a TFT having a memory film, a gate dielectric material, and an oxide semiconductor channel region. The TFTs include source/drain electrodes that are also source lines and bit lines in the memory array. A dielectric material is disposed between and separates adjacent source/drain electrodes. In some embodiments, at least a portion of the dielectric material is a low hydrogen material formed using a hydrogen-containing precursor introduced at a reduced flow rate. For example, at least a portion of the dielectric material (e.g., layer) that physically contacts the channel region of the TFT may have a relatively low hydrogen concentration, such as less than 3 at%. A low hydrogen concentration (e.g., within the above-described range) may reduce hydrogen diffusion into the channel region, thereby reducing defects and improving stability. Relatively low hydrogen concentrations in dielectric materials can be achieved by, for example, reducing the flow rate of hydrogen-containing precursors used to deposit the dielectric material.

In some embodiments, a memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting the word line; and an Oxide Semiconductor (OS) layer contacting the source line and the bit line, wherein the memory film is disposed between the OS layer and the word line; and connecting the source line to the bitLines of separated dielectric material. The dielectric material forms an interface with the OS layer. The dielectric material includes hydrogen, and a concentration of hydrogen at an interface between the dielectric material and the OS layer is no more than 3 atomic percent (at%). Optionally, in some embodiments, the dielectric material comprises: a first dielectric material contacting the OS layer, the first dielectric material continuously extending from the source line to the bit line; and a second dielectric material on a side of the first dielectric material opposite the OS layer, the second dielectric material extending continuously from the source line to the bit line, the second dielectric material having a hydrogen concentration greater than a hydrogen concentration of the first dielectric material. Optionally, in some embodiments, the dielectric material comprises silicon oxide, and the total hydrogen concentration of the dielectric material is greater than 0 at% and less than 5 at%. Optionally, in some embodiments, the dielectric material comprises silicon nitride, and the total hydrogen concentration of the dielectric material is greater than 0 at% and less than 10 at%. Optionally, in some embodiments, the OS layer comprises hydrogen. Optionally, in some embodiments, the OS layer has a hydrogen concentration of 10²⁰Atoms per cubic centimeter to 10²²Atoms per cubic centimeter. Optionally, in some embodiments, a longitudinal axis of the word line extends parallel to the major surface of the semiconductor substrate, a longitudinal axis of the source line extends perpendicular to the major surface of the semiconductor substrate, and a longitudinal axis of the bit line extends perpendicular to the major surface of the semiconductor substrate.

In some embodiments, a device comprises: a semiconductor substrate; a first memory cell over a semiconductor substrate, the first memory cell comprising a first thin film transistor, wherein the first thin film transistor comprises: a gate electrode including a portion of the first word line; a first portion of ferroelectric material located on sidewalls of the first word line; and a first channel region on a sidewall of the ferroelectric material, the first channel region including hydrogen, and the first channel region having a hydrogen concentration of 10²⁰Atoms per cubic centimeter to 10²²Atoms per cubic centimeter; a source line, wherein a first portion of the source line provides a first source/drain electrode for the first thin film transistor; a bit line, wherein a first portion of the bit line provides a second source/drain electrode for the first thin film transistor; a first dielectric separating the source and bit linesA material, wherein the first dielectric material physically contacts the first channel region; and a second memory cell located above the first memory cell. Optionally, in some embodiments, the second memory cell comprises a second thin film transistor, wherein the second portion of the source line provides a first source/drain electrode for the second thin film transistor, and wherein the second portion of the bit line provides a second source/drain electrode for the second thin film transistor. Optionally, in some embodiments, the device further comprises a second word line located above the first word line, wherein the gate electrode of the second thin film transistor comprises a portion of the second word line, and wherein the first word line is longer than the second word line. Optionally, in some embodiments, the hydrogen concentration at the interface between the first dielectric material and the first channel region is less than 3 atomic percent. Optionally, in some embodiments, the device further comprises a second dielectric material separating the source line and the bit line, the second dielectric material being separated from the first channel region by the first dielectric material, and the first dielectric material having a different material composition than the second dielectric material. Optionally, in some embodiments, the hydrogen concentration of the second dielectric material is greater than the hydrogen concentration of the first dielectric material.

In some embodiments, a method includes patterning a first trench extending through a first conductive line; depositing a memory film along a bottom surface and sidewalls of the first trench; depositing an Oxide Semiconductor (OS) layer over the memory film, the OS layer extending along a bottom surface and sidewalls of the first trench; depositing a first dielectric material over and in contact with the OS layer, wherein depositing the first dielectric material comprises simultaneously applying a first hydrogen-containing precursor at a first flow rate and a second hydrogen-free precursor at a second flow rate, and wherein a ratio of the second flow rate of the second hydrogen-free precursor to the first flow rate of the first hydrogen-containing precursor is at least 60; and depositing a second dielectric material over the first dielectric material to fill the remaining portion of the first trench. Optionally, in some embodiments, depositing the second dielectric material comprises simultaneously applying a third hydrogen-containing precursor at a third flow rate and a fourth hydrogen-free precursor at a fourth flow rate, and wherein a ratio of the fourth flow rate of the fourth hydrogen-free precursor to the third flow rate of the third hydrogen-containing precursor and the second flow rate of the second hydrogen-free precursorThe ratio of the second flow rate to the first flow rate of the first hydrogen-containing precursor is the same. Optionally, in some embodiments, depositing the second dielectric material comprises simultaneously applying a third hydrogen-containing precursor at a third flow rate and a fourth hydrogen-free precursor at a fourth flow rate, and wherein the third flow rate of the third hydrogen-containing precursor is greater than the first flow rate of the first hydrogen-containing precursor. Optionally, in some embodiments, the method further comprises patterning a third trench in the first and second dielectric materials; patterning a fourth trench in the first dielectric material and the second dielectric material; and filling the third trench and the fourth trench with a conductive material to define a source line and a bit line. Optionally, in some embodiments, the first hydrogen-containing precursor is Silane (SiH)₄) And the second hydrogen-free precursor is N₂And O. Optionally, in some embodiments, after depositing the first dielectric material, a hydrogen concentration at an interface between the first dielectric material and the OS layer is 3 at% or less. Optionally, in some embodiments, depositing the first dielectric material comprises diffusing hydrogen into the OS layer.

An embodiment of the present application provides a memory cell comprising: a thin film transistor over a semiconductor substrate, the thin film transistor comprising: a memory film contacting the word line; and an Oxide Semiconductor (OS) layer contacting the source line and the bit line, wherein the memory film is disposed between the OS layer and the word line; and a dielectric material separating the source line and the bit line, wherein the dielectric material forms an interface with the OS layer; wherein the dielectric material comprises hydrogen, and wherein a concentration of hydrogen at the interface between the dielectric material and the OS layer is no more than 3 atomic percent (at%).

In some embodiments, the dielectric material comprises: a first dielectric material contacting the OS layer, the first dielectric material extending continuously from the source line to the bit line; and a second dielectric material on a side of the first dielectric material opposite the OS layer, the second dielectric material continuously extending from the source line to the bit line, a hydrogen concentration of the second dielectric material being greater than a hydrogen concentration of the first dielectric material.

At one endIn some embodiments, the dielectric material comprises silicon oxide, and the total hydrogen concentration of the dielectric material is greater than 0 at% and less than 5 at%. In some embodiments, the dielectric material comprises silicon nitride, and the total hydrogen concentration of the dielectric material is greater than 0 at% and less than 10 at%. In some embodiments, the OS layer comprises hydrogen. In some embodiments, the hydrogen concentration of the OS layer is 10²⁰Atoms per cubic centimeter to 10²²Atoms per cubic centimeter. In some embodiments, longitudinal axes of the word lines extend parallel to a major surface of the semiconductor substrate, longitudinal axes of the source lines extend perpendicular to the major surface of the semiconductor substrate, and longitudinal axes of the bit lines extend perpendicular to the major surface of the semiconductor substrate.

Embodiments of the present application also provide a device, comprising: a semiconductor substrate; a first memory cell over the semiconductor substrate, the first memory cell comprising a first thin film transistor, wherein the first thin film transistor comprises: a gate electrode including a portion of the first word line; a first portion of ferroelectric material located on sidewalls of the first word line; and a first channel region on a sidewall of the ferroelectric material, the first channel region including hydrogen, and a hydrogen concentration of the first channel region being 10²⁰Atoms per cubic centimeter to 10²²Atoms per cubic centimeter; a source line, wherein a first portion of the source line provides a first source/drain electrode for the first thin film transistor; a bit line, wherein a first portion of the bit line provides a second source/drain electrode for the first thin film transistor; a first dielectric material separating the source line and the bit line, wherein the first dielectric material physically contacts the first channel region; and a second memory cell located above the first memory cell.

In some embodiments, the second memory cell comprises a second thin film transistor, wherein the second portion of the source line provides a first source/drain electrode for the second thin film transistor, and wherein the second portion of the bit line provides a second source/drain electrode for the second thin film transistor. In some embodiments, further comprising: a second word line over the first word line, wherein a gate electrode of the second thin film transistor includes a portion of the second word line, and wherein the first word line is longer than the second word line. In some embodiments, the hydrogen concentration at the interface between the first dielectric material and the first channel region is less than 3 atomic percent. In some embodiments, further comprising: a second dielectric material separating the source line and the bit line, the second dielectric material being separated from the first channel region by the first dielectric material, and the first dielectric material having a different material composition than the second dielectric material. In some embodiments, the hydrogen concentration of the second dielectric material is greater than the hydrogen concentration of the first dielectric material.

Embodiments of the present application further provide a method, comprising: patterning a first trench extending through the first conductive line; depositing a memory film along a bottom surface and sidewalls of the first trench; depositing an Oxide Semiconductor (OS) layer over the memory film, the OS layer extending along a bottom surface and sidewalls of the first trench; depositing a first dielectric material over and in contact with the OS layer, wherein depositing the first dielectric material comprises simultaneously applying a first hydrogen-containing precursor at a first flow rate and a second hydrogen-free precursor at a second flow rate of a second flow, and wherein a ratio of the second flow rate of the second hydrogen-free precursor to the first flow rate of the first hydrogen-containing precursor is at least 60; and depositing a second dielectric material over the first dielectric material to fill a remaining portion of the first trench.

In some embodiments, depositing the second dielectric material comprises simultaneously applying a third hydrogen-containing precursor at a third flow rate and a fourth hydrogen-free precursor at a fourth flow rate, and wherein a ratio of the fourth flow rate of the fourth hydrogen-free precursor to the third flow rate of the third hydrogen-containing precursor and a ratio of the second flow rate of the second hydrogen-free precursor to the first flow rate of the first hydrogen-containing precursor are the same. In some embodiments, depositing the second dielectric material includes simultaneously applying a third hydrogen-containing precursor at a third flow rateAnd a fourth hydrogen-free precursor at a fourth flow rate, and wherein the third flow rate of the third hydrogen-containing precursor is greater than the first flow rate of the first hydrogen-containing precursor. In some embodiments, further comprising: patterning a third trench in the first and second dielectric materials; patterning a fourth trench in the first and second dielectric materials; and filling the third trench and the fourth trench with a conductive material to define a source line and a bit line. In some embodiments, the first hydrogen-containing precursor is Silane (SiH)₄) And said second hydrogen-free precursor is N₂And O. In some embodiments, a concentration of hydrogen at an interface between the first dielectric material and the OS layer is 3 at% or less after depositing the first dielectric material. In some embodiments, depositing the first dielectric material comprises diffusing hydrogen into the OS layer.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.