阅读说明：本技术 有源区阵列及其形成方法、半导体器件及其形成方法 (Active area array and forming method thereof, semiconductor device and forming method thereof ) 是由 不公告发明人 于 2018-08-30 设计创作，主要内容包括：本发明提供了一种有源区阵列及其形成方法、半导体器件及其形成方法。利用辅助线自对准形成排布密集度呈双倍增加的第一自对准间隔图案,并基于第一自对准间隔图案自对准形成第二自对准间隔图案,第二自对准间隔图案的排布密集度相对于第一自对准间隔图案而言呈双倍增加,接着即可利用第二自对准间隔图案定义出有源区阵列的图形。可见,基于本发明提供的有源区阵列的形成方法,即使在光刻工艺的精度限制下,仍能够实现有源区尺寸的进一步缩减,并可以有效提高有源区阵列中有源区的密集度。(The invention provides an active area array and a forming method thereof, and a semiconductor device and a forming method thereof. The auxiliary lines are self-aligned to form a first self-aligned spacer pattern with double-increased arrangement density, a second self-aligned spacer pattern is self-aligned based on the first self-aligned spacer pattern, the arrangement density of the second self-aligned spacer pattern is double-increased relative to the first self-aligned spacer pattern, and then the second self-aligned spacer pattern is used for defining the pattern of the active area array. Therefore, based on the forming method of the active area array provided by the invention, the size of the active area can be further reduced even under the precision limit of the photoetching process, and the density of the active area in the active area array can be effectively improved.)

1. A method for forming an active area array, comprising:

providing a substrate, wherein the upper surface of the substrate comprises an element array area;

forming a plurality of auxiliary lines on the substrate, wherein the auxiliary lines extend along a first direction and penetrate through the element array region, and the auxiliary lines are sequentially arranged along a second direction, and each auxiliary line is provided with two parallel side walls higher than a first length direction side wall of the substrate;

forming a plurality of first self-aligned spacer patterns on the side of the first length-wise sidewall of the auxiliary line, the first self-aligned spacer patterns following the first length-wise sidewall of the auxiliary line and extending along the first direction; the forming of the plurality of first self-aligned spacer patterns includes: determining the length of the first self-aligned spacer pattern by using a pattern of a mask to completely form at least one first self-aligned spacer pattern in the device array region; removing the auxiliary lines, wherein each first self-aligned interval pattern is provided with two parallel side walls which are higher than the second length direction side wall of the substrate;

forming a plurality of second self-aligned spacer patterns on a second length-wise sidewall side of the first self-aligned spacer pattern, the second self-aligned spacer patterns following the second length-wise sidewall of the first self-aligned spacer pattern and extending along the first direction; the step of forming a plurality of second self-aligned spacer patterns comprising: then, determining the length of the second self-aligned spacing pattern by using the pattern of the photomask, wherein at least one group of pairwise paired second self-aligned spacing patterns are completely formed in the element array region and are separated from each other; and removing the first self-aligned spacer patterns, the gap of each set of the second self-aligned spacer patterns being defined by the lateral film formation thickness of the first self-aligned spacer patterns; and the number of the first and second groups,

and copying the pattern of the second self-aligned spacing pattern into the substrate to define a plurality of active regions in the substrate and form an active region array in the element array region.

2. The method of claim 1, wherein a first width dimension of the first self-aligned spacer pattern and a second width dimension of the second self-aligned spacer pattern are both smaller than an auxiliary line width dimension of the auxiliary line, and a first space dimension between the first self-aligned spacer patterns adjacent in the second direction is equal to or smaller than the auxiliary line width dimension.

3. The method of claim 2, wherein the first width dimension of the first self-aligned spacer pattern is between 20nm and 50 nm; the second width dimension of the second self-aligned spacer pattern is between 25nm and 60 nm; a second space dimension between the second self-aligned spacer patterns formed on the first self-aligned spacer patterns adjacent in the second direction and facing each other is between 10nm and 40 nm.

4. The method of forming an array of active regions of claim 1, wherein the method of forming the first self-aligned spacer pattern comprises:

forming a self-aligned continuous pattern on a first lengthwise sidewall of the auxiliary line, the self-aligned continuous pattern continuously extending along the first direction on the sidewall of the auxiliary line; and the number of the first and second groups,

and performing a photolithography process on the self-aligned continuous pattern by using the photomask, wherein the photomask is provided with a plurality of cutting windows for cutting off the self-aligned continuous pattern to form a plurality of mutually-separated first self-aligned interval patterns, and the first self-aligned interval patterns are arranged at intervals along the first direction.

5. The method of forming an array of active regions of claim 4, wherein the second self-aligned spacer pattern comprises:

forming a self-aligned surrounding pattern on sidewalls of the first self-aligned spacer pattern, the self-aligned surrounding pattern surrounding the first self-aligned spacer pattern such that portions of the self-aligned surrounding pattern on two second lengthwise sidewalls of the first self-aligned spacer pattern are connected to each other at ends of the first self-aligned spacer pattern; and the number of the first and second groups,

and performing a photolithography process on the self-aligned surrounding pattern by using the photomask, and removing a portion of the self-aligned surrounding pattern located at an end of the first self-aligned spacer pattern by using the cutoff window of the photomask, so that two portions of the self-aligned surrounding pattern located on two second length-wise sidewalls of the first self-aligned spacer pattern are separated from each other to form the second self-aligned spacer pattern, wherein two second self-aligned spacer patterns corresponding to the same first self-aligned spacer pattern are arranged in pairs.

6. The method of claim 5, wherein the self-aligned surrounding patterns are arranged in a same line along the first direction and have a segment spacing dimension greater than 2 times a second width dimension of the self-aligned surrounding patterns, such that the self-aligned surrounding patterns have ring-shaped structures surrounding the first self-aligned spacing patterns, each of the first self-aligned spacing patterns corresponds to one of the ring-shaped structures, and adjacent ring-shaped structures are separated from each other.

7. The method of forming an active area array of claim 5, wherein a segment space size between adjacent first self-aligned space patterns arranged on the same line along the first direction is 2 times or less a width size of the self-aligned surrounding pattern so that portions of the self-aligned surrounding patterns surrounding the adjacent first self-aligned space patterns are connected to each other between the adjacent first self-aligned space patterns.

8. The method of claim 1, wherein the pattern of the second self-aligned spacer pattern is replicated into the substrate to form a plurality of isolation trenches in the substrate, the plurality of isolation trenches surrounding a plurality of the active areas;

the method for forming the active area array further comprises the following steps: a layer of fill dielectric material is in the isolation trench.

9. The method of claim 8, wherein the dielectric material layer has a dielectric constant of less than 3.

10. The method of forming an active area array as claimed in any one of claims 1 to 9, wherein the auxiliary line width dimension of the auxiliary line is equal to or greater than a minimum feature size of a photolithography process.

11. The method of claim 10, wherein a width dimension of the active regions is between 25nm and 60nm, and a spacing dimension between adjacent active regions along the second direction is between 10nm and 40 nm.

12. An active area array comprises a plurality of active areas, the active areas extend along a first direction, the active areas are arranged in an aligned mode along the first direction to form an active extension line, the active extension lines in the active area array are sequentially arranged along a second direction, two adjacent active extension lines are arranged in pairs to form an active extension line pair group, and in the active extension line pair group, a plurality of active areas located in one active extension line and a plurality of active areas located in the other active extension line are arranged in a one-to-one opposite mode.

13. The active area array of claim 12, wherein two adjacent pairs of the active extension lines form an extension line repeating unit, each of the extension line repeating units includes a first active extension line, a second active extension line, a third active extension line, and a fourth active extension line sequentially arranged along the second direction;

in the same extension line repeating unit, the spacing size between two boundaries of the second active extension line and the third active region extension line which are deviated from each other is larger than or equal to the minimum characteristic size of the photoetching process; and in the adjacent extension line repeating units, the interval size between two boundaries, at which the second active extension line in one extension line repeating unit and the third active extension line of the other extension line repeating unit are close to each other, is greater than or equal to the minimum characteristic size of the photoetching process.

14. The active area array of claim 13, wherein a spacing dimension between two boundaries where the first active extension line and the second active extension line are close to each other, and a spacing dimension between two boundaries where the third active extension line and the fourth active extension line are close to each other are each between 20nm and 50nm in a same extension line repeating unit.

15. The active area array of claim 13, wherein a spacing dimension between two boundaries where the second active extension line and the third active extension line are close to each other is in a range of 10nm to 40nm in the same extension line repeating unit.

16. The active area array of claim 13, wherein a spacing dimension between two boundaries where the fourth active extension line in one extension line repeating unit and the first active extension line in another extension line repeating unit are close to each other in adjacent extension line repeating units is between 10nm and 40 nm.

17. The active area array of any of claims 12-16, wherein the width dimension of the active areas is between 25nm and 60nm, and the spacing dimension between adjacent active areas along the second direction is between 10nm and 40 nm.

18. A method of forming a semiconductor device, comprising: an array of active regions is formed in the substrate using the method of forming as claimed in claim 1.

19. The method of forming a semiconductor device according to claim 18, wherein the semiconductor device includes an integrated circuit memory, and a plurality of the active regions in the active region array are used to form a plurality of memory cells of the integrated circuit memory.

20. The method of forming a semiconductor device according to claim 19, further comprising:

forming a plurality of word lines in the substrate, the word lines intersecting a plurality of respective active regions in a word line extending direction; and the number of the first and second groups,

a plurality of bit lines are formed in the substrate, the bit lines intersecting a plurality of respective active regions in a bit line extension direction.

21. The method for forming a semiconductor device according to claim 20, wherein the method for forming the word line comprises:

forming a word line mask layer on the substrate, wherein the word line mask layer comprises a plurality of mask definition lines, a mask opening is defined between the adjacent mask definition lines, and the mask definition lines are formed by utilizing a space multiplication process;

etching the substrate by taking the mask layer as a mask to form a plurality of word line grooves corresponding to the mask openings in the substrate; and the number of the first and second groups,

word line material is filled in the word line trench to form the word line.

22. A semiconductor device comprising the active area array of claim 12.

Technical Field

The present invention relates to the field of semiconductor integrated circuit technology, and more particularly, to an active area array and a method for forming the same, and a semiconductor device and a method for forming the same.

Background

In a semiconductor integrated circuit device, it is often necessary to define an active area array in a substrate and to fabricate corresponding device cells in a plurality of active areas of the active area array. According to the conventional method for forming the active area array, the pattern of the active area array is usually directly defined by using a photolithography process. However, due to the precision limitation of the photolithography process, the minimum dimension of the pattern directly defined by the photolithography process can only reach the limit dimension of the photolithography process and cannot be further reduced.

At present, with the continuous development of semiconductor technology, semiconductor devices tend to be miniaturized. Therefore, the size of the active region needs to be reduced correspondingly to increase the density of the active regions in the active region array and increase the utilization rate of the active regions in the array region.

Disclosure of Invention

The present invention is directed to a method for forming an active area array, so as to solve the problem that the size of an active area in an existing active area array cannot be further reduced.

To solve the above technical problem, the present invention provides a method for forming an active area array, including:

providing a substrate, wherein the upper surface of the substrate comprises an element array area;

forming a plurality of auxiliary lines on the substrate, wherein the auxiliary lines extend along a first direction and penetrate through the element array region, and the auxiliary lines are sequentially arranged along a second direction, and each auxiliary line is provided with two parallel side walls higher than a first length direction side wall of the substrate;

forming a plurality of first self-aligned spacer patterns on the side of the first length-wise sidewall of the auxiliary line, the first self-aligned spacer patterns following the first length-wise sidewall of the auxiliary line and extending along the first direction; the forming of the plurality of first self-aligned spacer patterns includes: determining the length of the first self-aligned spacer pattern by using a pattern of a mask to completely form at least one first self-aligned spacer pattern in the device array region; removing the auxiliary lines, wherein each first self-aligned interval pattern is provided with two parallel side walls which are higher than the second length direction side wall of the substrate;

forming a plurality of second self-aligned spacer patterns on a second length-wise sidewall side of the first self-aligned spacer pattern, the second self-aligned spacer patterns following the second length-wise sidewall of the first self-aligned spacer pattern and extending along the first direction; the step of forming a plurality of second self-aligned spacer patterns comprising: determining the length of the second self-aligned spacer pattern by using the pattern of the photomask, wherein at least one group of pairwise paired second self-aligned spacer patterns are completely formed in the element array region and are separated from each other; and removing the first self-aligned spacer patterns, the gap of each set of the second self-aligned spacer patterns being defined by the lateral film formation thickness of the first self-aligned spacer patterns; and the number of the first and second groups,

and copying the pattern of the second self-aligned spacing pattern into the substrate to define a plurality of active regions in the substrate and form an active region array in the element array region.

Optionally, a first width dimension of the first self-aligned spacer pattern and a second width dimension of the second self-aligned spacer pattern are both smaller than an auxiliary line width dimension of the auxiliary line, and a first space dimension between adjacent first self-aligned spacer patterns in the second direction is smaller than or equal to the auxiliary line width dimension.

Optionally, a first width dimension of the first self-aligned spacer pattern is between 20nm and 50 nm; the second width dimension of the second self-aligned spacer pattern is between 25nm and 60 nm; a second space dimension between the second self-aligned spacer patterns formed on the first self-aligned spacer patterns adjacent in the second direction and facing each other is between 10nm and 40 nm.

Optionally, the method for forming the first self-aligned spacer pattern includes:

forming a self-aligned continuous pattern on a first lengthwise sidewall of the auxiliary line, the self-aligned continuous pattern continuously extending along the first direction on the sidewall of the auxiliary line; and the number of the first and second groups,

and performing a photolithography process on the self-aligned continuous pattern by using the photomask, wherein the photomask is provided with a plurality of cutting windows for cutting off the self-aligned continuous pattern to form a plurality of first self-aligned interval patterns, and the first self-aligned interval patterns are arranged at intervals along the first direction.

Optionally, the method for forming the second self-aligned spacer pattern includes:

forming a self-aligned surrounding pattern on sidewalls of the first self-aligned spacer pattern, the self-aligned surrounding pattern surrounding the first self-aligned spacer pattern such that portions of the self-aligned surrounding pattern on two second lengthwise sidewalls of the first self-aligned spacer pattern are connected to each other at ends of the first self-aligned spacer pattern; and the number of the first and second groups,

and performing a photolithography process on the self-aligned surrounding pattern by using the photomask, and removing a portion of the self-aligned surrounding pattern located at an end of the first self-aligned spacer pattern by using the cutoff window of the photomask, so that two portions of the self-aligned surrounding pattern located on two second length-wise sidewalls of the first self-aligned spacer pattern are separated from each other to form the second self-aligned spacer pattern, wherein two second self-aligned spacer patterns corresponding to the same first self-aligned spacer pattern are arranged in pairs.

Optionally, the self-aligned surrounding patterns are arranged on the same straight line along the first direction, and the segment spacing dimension between adjacent first self-aligned spacing patterns is greater than 2 times the second width dimension of the self-aligned surrounding patterns, so that the self-aligned surrounding patterns have ring-shaped structures surrounding the first self-aligned spacing patterns, each of the first self-aligned spacing patterns corresponds to one of the ring-shaped structures, and adjacent ring-shaped structures are separated from each other.

Optionally, a segment spacing dimension between adjacent first self-aligned spacer patterns arranged on the same straight line along the first direction is less than or equal to 2 times a width dimension of the self-aligned surrounding pattern, so that portions of the self-aligned surrounding patterns surrounding the adjacent first self-aligned spacer patterns are connected to each other between the adjacent first self-aligned spacer patterns.

Optionally, copying the pattern of the second self-aligned spacer pattern into the substrate to form a plurality of isolation trenches in the substrate, the plurality of isolation trenches surrounding the plurality of active regions;

the method for forming the active area array further comprises the following steps: a layer of fill dielectric material is in the isolation trench.

Optionally, the dielectric constant of the dielectric material layer is less than 3.

Optionally, the width of the auxiliary line is greater than or equal to the minimum feature size of the photolithography process.

Optionally, the width dimension of the active regions is 25nm to 60nm, and the spacing dimension between adjacent active regions along the second direction is 10nm to 40 nm.

Based on the forming method, another object of the present invention is to provide an active area array, which includes a plurality of active areas, the active areas extend along a first direction, and the active areas are aligned along the first direction to form an active extension line, the active extension lines in the active area array are sequentially arranged along a second direction, two adjacent active extension lines are arranged in pairs to form an active extension line pair group, and in the active extension line pair group, a plurality of active areas located in one active extension line are arranged opposite to a plurality of active areas located in the other active extension line one by one.

Optionally, two adjacent pairs of the active extension line pairs form an extension line repeating unit, and each extension line repeating unit includes a first active extension line, a second active extension line, a third active extension line, and a fourth active extension line sequentially arranged along the second direction;

in the same extension line repeating unit, the spacing size between two boundaries of the second active extension line and the third active region extension line which are deviated from each other is less than or equal to the minimum characteristic size of the photoetching process; and in the adjacent extension line repeating units, the interval size between two boundaries, at which the second active extension line in one extension line repeating unit and the third active extension line of the other extension line repeating unit are close to each other, is greater than or equal to the minimum characteristic size of the photoetching process.

Optionally, in the same extension line repeating unit, a space dimension between the first active extension line and the second active extension line, and a space dimension between the third active extension line and the fourth active extension line are both between 20nm and 50 nm.

Optionally, in the same extension line repeating unit, a size of a space between the second active extension line and the third active extension line is 10nm to 40 nm.

Optionally, in the adjacent extension line repeating units, a spacing dimension between the fourth active extension line in one extension line repeating unit and the third active extension line in another extension line repeating unit is 10nm to 40 nm.

Optionally, the width dimension of the active regions is 25nm to 60nm, and the spacing dimension between adjacent active regions along the second direction is 10nm to 40 nm.

It is a further object of the present invention to provide a method for forming a semiconductor device, which specifically includes the method for forming an active area array as described above.

Optionally, the semiconductor device includes an integrated circuit memory, and a plurality of the active regions in the active region array are used to form a plurality of memory cells of the integrated circuit memory.

Optionally, the method for forming the semiconductor device further includes:

forming a plurality of word lines in the substrate, the word lines intersecting a plurality of respective active regions in a word line extending direction; and the number of the first and second groups,

a plurality of bit lines are formed in the substrate, the bit lines intersecting a plurality of respective active regions in a bit line extension direction.

Optionally, the method for forming the word line includes:

forming a word line mask layer on the substrate, wherein the word line mask layer comprises a plurality of mask definition lines, a mask opening is defined between the adjacent mask definition lines, and the mask definition lines are formed by utilizing a space multiplication process;

etching the substrate by taking the mask layer as a mask to form a plurality of word line grooves corresponding to the mask openings in the substrate; and the number of the first and second groups,

word line material is filled in the word line trench to form the word line.

In the method for forming an active area array according to the present invention, the auxiliary lines are formed, so that the first self-aligned spacer pattern can be formed by self-alignment using a pitch multiplication process (at this time, the arrangement density of the first self-aligned spacer pattern is increased twice with respect to the arrangement density of the auxiliary lines), and the pitch multiplication process can be further performed based on the first self-aligned spacer pattern to form the second self-aligned spacer pattern, thereby further increasing the arrangement density of the second self-aligned spacer pattern twice with respect to the first self-aligned spacer pattern. Therefore, the size of the formed active region is far smaller than the minimum characteristic size of the photoetching process based on the precision limit of the conventional photoetching process, and the arrangement density of the active regions in the formed active region array is increased by multiple times.

Drawings

FIG. 1a is a schematic diagram of one of the structures of a conventional integrated circuit memory;

FIG. 1b is a schematic diagram showing another structure of an integrated circuit memory of the prior art;

fig. 2 is a schematic flow chart illustrating a method for forming an active area array according to a first embodiment of the invention;

fig. 3a to fig. 10a are top views of an active area array in a manufacturing process thereof according to a first embodiment of the present invention;

FIGS. 3 b-10 b are schematic cross-sectional views along aa' direction of the active area array in the first embodiment of the invention shown in FIGS. 3 a-10 a, respectively;

fig. 11a is a schematic size diagram of an active area repeat unit of an active area array formed by a method for forming an active area array according to an embodiment of the present invention;

fig. 11b is a schematic size diagram of an active area of a device unit of an active area array formed by a method for forming the active area array according to an embodiment of the present invention;

fig. 12a to 12c are top views illustrating a method for forming an active area array according to a second embodiment of the present invention during a manufacturing process thereof;

fig. 13 is a schematic layout view of an active area array according to a fourth embodiment of the present invention;

fig. 14 is a schematic structural view of a semiconductor device formed by the method for forming a semiconductor device in the fifth embodiment of the present invention.

Wherein the reference numbers are as follows:

10-an active region;

20-word lines; 30-bit line;

100-a substrate; 110-mask layer;

100A-element array region; 100B-peripheral zone;

101-an active region; 102-an isolation trench;

120-auxiliary line; 120 a-a first length-wise sidewall;

131/131' -a first self-aligned spacer pattern;

130-self-aligned continuous pattern; 131 a-a second lengthwise sidewall;

140 a-a mask; 141-truncating the window;

140b/140 c-etchant;

151/151' -a second self-aligned spacer pattern;

150/150' -self-aligned surround pattern;

200-word line; 300-bit line.

An AC-active region repeating unit;

w1 — first width dimension; w2 — second width dimension;

Z11/Z12-first granularity; Z2/Z2' -segment spacing dimension;

z3 — second granularity dimension;

AA-active region;

AL — active extension line;

AL1 — first active extension line; AL2 — second active extension line;

AL 3-third active extension line; AL 4-fourth active extension line;

an LC-extension line repeat unit;

g1-the dimension of the space between the second active extension line and the third active extension line in the same extension line repeat unit;

g2-the dimension of the space between the second active extension in one extension line repeat unit and the third active extension of another extension line repeat unit in the adjacent extension line repeat units.

Detailed Description

As described in the background art, with the continuous development of semiconductor integrated circuits, it is important to reduce the size of an active region, increase the arrangement density in an active region array, and increase the utilization rate in order to increase the arrangement density of devices and realize miniaturization of devices.

For example, FIG. 1a shows a schematic diagram of one structure of an existing integrated circuit memory, and FIG. 1b shows a schematic diagram of another structure of the existing integrated circuit memory. As shown in connection with fig. 1a and 1b, the integrated circuit memory generally comprises:

an active area array having a plurality of active areas 10, the active areas 10 being used to form memory cells, e.g. one active area 10 being used to form two memory cells;

a plurality of word lines 20, the word lines 20 intersecting the respective active regions 10 in a word line extending direction to connect to the memory cells; and the number of the first and second groups,

a plurality of bit lines 30, the bit lines 30 intersecting the respective active regions 10 in a bit line extending direction and being connected to the memory cells.

The active region 10, the word line 20 and the bit line 30 are directly defined based on a photolithography process, so that the minimum width dimension of the active region 10, the word line 20 and the bit line 30 can only reach the minimum line width feature dimension of the photolithography process, thereby further limiting the size of each memory cell in the memory, and preventing the size of the memory cell from being further reduced.

Referring now to FIG. 1a with emphasis on the integrated circuit memory shown in FIG. 1a, a memory cell is shownThe width dimension occupied in the direction perpendicular to the word lines 20 is 3F; and the width dimension occupied by one memory cell in the direction perpendicular to the bit line 30 is 2F, so that the occupied area S of one memory cell is 6F²(3F x 2F), wherein F is the minimum feature size. That is, the size of the defined pattern is limited based on the resolution of the conventional photolithography equipment, for example, the width of the active region 10 can only reach the limit line width of the photolithography process, so that the unit size of the prepared memory cell can only reach 6F²And cannot continue to scale down.

It should be noted that the "minimum feature size F" described herein is: based on the resolution of the current lithography equipment, the minimum critical line width dimension and the minimum critical line spacing dimension can be obtained. Wherein the minimum limit line width dimension and the minimum limit line spacing dimension are equal.

With particular reference to FIG. 1b, in the integrated circuit memory of FIG. 1b, one memory cell occupies a width dimension of 2F in a direction perpendicular to the word line 20; and a width dimension occupied by one memory cell in a direction perpendicular to the bit line 30 is 3F, so that an occupied area S of one memory cell is 6F²(2F x 3F), wherein F is the minimum feature size.

It follows that, based on the existing fabrication process, it is not possible to obtain an active region 10 with a further reduced size, so that minimizing the cell layout size (e.g., area S) of a single memory cell can only achieve 6 times (6F) the square of the minimum feature size²) And the size of the memory cell is greatly limited, so that the size of the integrated circuit memory is difficult to reduce.

To this end, the present invention provides a method of forming an active area array, which is capable of forming a first self-aligned spacer pattern having an arrangement density multiplied by a pitch multiplication process using an auxiliary line directly formed by a photolithography process; and passing through the pitch multiplication process again based on the first self-aligned spacer pattern to form a second self-aligned spacer pattern having an arrangement density multiplied. Therefore, the size reduction of the finally formed active region can be realized, and the arrangement density of the active region is increased by multiple times.

The active area array and the forming method thereof, the semiconductor device and the forming method thereof proposed by the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Fig. 2 is a flowchart illustrating a method for forming an active area array according to a first embodiment of the invention, fig. 3a to 10a are top views illustrating a manufacturing process of the active area array according to the first embodiment of the invention, and fig. 3b to 10b are cross-sectional views along the aa' direction illustrating the manufacturing process of the active area array according to the first embodiment of the invention shown in fig. 3a to 10a, respectively. The forming method in the present embodiment will be described in detail in its respective steps with reference to the drawings.

In step S100, referring to fig. 3a and 3b in particular, a substrate 100 is provided, an upper surface of the substrate 100 includes an element array region 100A, and the element array region 100A of the substrate 100 is used for forming the active area array in a subsequent process. And a peripheral region 100B is further included on the upper surface of the substrate 100, the peripheral region 100B being located on an outer periphery of the element array region 100A.

In a preferred embodiment, a mask layer 110 is further formed on the substrate 100, and the mask layer 110 is used for transferring the pattern of the active area array to the substrate 100 in a subsequent process, and can protect the substrate 100 before the pattern of the active area array is defined.

The mask layer 110 may be made of a material having a relatively large etching selection ratio with respect to the substrate 100, for example, in a subsequent process, when the mask layer 110 is used as a mask to etch the substrate 100 to transfer the active area array pattern to the substrate 100, the etching selection ratio of the mask layer 110 to the substrate 100 is greater than or equal to 4:1, so that high precision of pattern transfer can be ensured. Specifically, in the present embodiment, the material of the substrate 100 includes silicon, and the material of the mask layer 110 may include one or a combination of silicon oxide, silicon nitride, and carbon, for example.

In step S200, with continued reference to fig. 3a and 3b, a plurality of auxiliary lines 120 are formed on the substrate 100, the auxiliary lines 120 extending along a first direction (D1 direction) and penetrating through the element array region 100A, and the plurality of auxiliary lines 120 are sequentially arranged along a second direction (D2 direction), and each of the auxiliary lines 120 has two parallel sidewalls 120A higher than the first length of the substrate 100. In this embodiment, the auxiliary lines 120 are formed on the mask layer 110.

The pattern of the auxiliary lines 120 may be defined directly by using a photolithography process, and therefore the minimum line width of the auxiliary lines 120 and the minimum line spacing between adjacent auxiliary lines 120 may reach the minimum feature size F of the photolithography process. For example, the line width dimension of the auxiliary lines 120 is equal to or greater than 40nm, and the line pitch dimension between adjacent auxiliary lines 120 is equal to or greater than 40nm, respectively, based on the accuracy limit of the photolithography process. Of course, in other embodiments, the line space between adjacent auxiliary lines may be larger than the line width of the auxiliary line 120, so that the space between the adjacent first self-aligned space patterns in the second direction (D2 direction) in the plurality of first self-aligned space patterns formed by attaching to the auxiliary lines may be more uniform in the subsequent process.

In step S300, referring to fig. 4a to 6a and fig. 4b to 6b in particular, a plurality of first self-aligned spacer patterns 131 are formed on the side of the first length-oriented sidewall 120a of the auxiliary line 120, the first self-aligned spacer patterns 131 follow the first length of the auxiliary line 120 and extend along a first direction (D1 direction) toward the sidewall 120a, and each of the first self-aligned spacer patterns 131 has two parallel sidewalls 131a higher than the second length-oriented sidewall 131a of the substrate 100.

That is, by forming the auxiliary lines 120, the first self-aligned spacer patterns 131 may be formed to be self-aligned to sidewalls using the first lengths of the auxiliary lines 120, and the auxiliary lines 120 may be removed after the first self-aligned spacer patterns 131 are formed. At this time, the formed first self-aligned spacer patterns 131 can accordingly extend along the first direction (D1 direction). In addition, it should be appreciated that, in general, a plurality of first self-aligned spacer patterns 131 are formed on the sidewalls 120a of two first lengths of one auxiliary line 120 extending along the first direction, and the plurality of first self-aligned spacer patterns 131 are arranged at intervals along the first direction and are aligned along the sidewalls of the auxiliary line 120.

Specifically, the method for forming the first self-aligned spacer pattern 131 includes the following steps, for example.

First, referring to fig. 4a and 4b, a self-aligned continuous pattern 130 is formed on the first lengthwise sidewall 120a of the auxiliary line 120, and the self-aligned continuous pattern 130 continuously extends along the first direction (direction D1) on the first lengthwise sidewall 120a of the auxiliary line 120.

The self-aligned continuous pattern 130 may be formed on the sidewalls of the auxiliary lines 120 in a self-aligned manner, and the forming process includes: firstly, a thin film deposition process is performed to form a side wall material layer on the substrate 100, wherein the side wall material layer conformally covers the top wall and the side wall of the auxiliary line 120 and further extends to cover the bottom wall of the groove defined by the adjacent auxiliary lines 120; then, an etch-back process is performed to remove the portions of the sidewall material layer on the top wall of the auxiliary line 120 and the bottom wall of the groove, and the portions of the sidewall material layer on the sidewalls of the auxiliary line 120 are left to form the self-aligned continuous pattern 130.

In this embodiment, after the self-aligned continuous pattern 130 is formed, the auxiliary lines 120 may be removed. It should be appreciated of course that in other embodiments, the auxiliary lines 120 may be removed in a subsequent process. The material of the self-aligned continuous pattern 130 (i.e., the material of the first self-aligned spacer pattern) may be a material having a larger etching selectivity than the auxiliary line 120, so as to avoid the occurrence of abnormal topography due to damage to the self-aligned continuous pattern 130 when the auxiliary line 120 is removed. For example, the material of the self-aligned continuous pattern 130 may include silicon oxide and/or silicon nitride.

A second step, specifically referring to fig. 5a to 6a and 5b to 6b, of determining the length of the first self-aligned spacer pattern by using the pattern of a mask 140A, so that at least one first self-aligned spacer pattern 131 is completely formed in the device array region 100A.

Specifically, the photo-mask 140a is used to perform a photolithography process on the self-aligned continuous pattern 130, the photo-mask 140a has a plurality of cutting windows 141 for cutting the self-aligned continuous pattern 130, so that the self-aligned continuous pattern 130 can be cut based on an etching process to form a plurality of mutually separated first self-aligned spacer patterns 131, and the plurality of first self-aligned spacer patterns 131 are arranged at intervals along the first direction.

As shown in fig. 5a and 5b, when performing an etching process on the self-aligned continuous pattern 130, an etchant 140b may enter from a region corresponding to the intercepting window 141 to etch the exposed self-aligned continuous pattern 130.

Referring to fig. 4a and 6a in combination, the lateral film thickness of the self-aligned continuous pattern 130 corresponds to the first width dimension W1 (specifically, the width dimension parallel to the substrate surface) of the first self-aligned spacer pattern 131, and the first width dimension W1 of the first self-aligned spacer pattern 131 is smaller than the auxiliary line width dimension of the auxiliary lines 120 and is also smaller than the line space dimension between adjacent auxiliary lines 120. Further, the first width dimension W1 of the first self-aligned spacer pattern 131 is between 20nm and 50nm, and the lateral film thickness of the corresponding self-aligned continuous pattern 130 may also be between 20nm and 50 nm. Obviously, the opening size of the cutting window 141 of the mask 140a in the second direction is larger than the lateral film thickness of the self-aligned continuous pattern 130, so that the self-aligned continuous pattern 130 can be cut.

Further, a first space dimension between the first self-aligned space patterns 131 adjacent in the second direction is equal to or smaller than an auxiliary line width dimension of the auxiliary line, e.g., a first space dimension Z11 between two first self-aligned space patterns 131 corresponding to both sides of the same auxiliary line 120 is equal to the auxiliary line width dimension of the auxiliary line, and a first space dimension Z12 between first self-aligned space patterns corresponding to adjacent auxiliary lines and facing each other is smaller than the auxiliary line width dimension of the auxiliary line.

Further, the segment interval dimension Z2 between the adjacent first self-aligned spacer patterns 131 arranged in the same line along the first direction may be adjusted according to actual requirements as long as the length dimension of the segmented first self-aligned spacer patterns 131 meets the requirements. In this embodiment, the first self-aligned spacer patterns 131 arranged on the same line along the first direction have a larger segment spacing size therebetween.

In step S400, referring to fig. 7a to 9a and fig. 7b to 9b, a plurality of second self-aligned spacer patterns 151 are formed on the side of the second length-wise sidewall 131a of the first self-aligned spacer pattern 131, and the second self-aligned spacer patterns 151 conform to the second length-wise sidewall 131a of the first self-aligned spacer pattern 131 and extend along the first direction. Wherein a plurality of the second self-aligned spacer patterns 151 are disposed in pairs and separated from each other, and a gap of each set of the second self-aligned spacer patterns 151 is defined by a lateral film formation thickness of the first self-aligned spacer pattern 131.

That is, the second self-aligned spacer patterns 151 can be self-aligned to the sidewalls 131a using the second length of the first self-aligned spacer patterns 131, and one first self-aligned spacer pattern 131 can correspondingly form two second self-aligned spacer patterns 151. Accordingly, the second self-aligned spacer pattern 151 can further achieve an increase in double patterns compared to the first self-aligned spacer pattern 131. As can be seen, compared to the auxiliary lines 120 defined only by the photolithography process, the finally obtained second self-aligned spacer pattern 151 in the present embodiment achieves an increase of 4 times the pattern; and the second width dimension W2 of the second self-aligned spacer pattern 151 is much smaller than the auxiliary line width dimension of the auxiliary line 120 with respect to the auxiliary line width dimension of the auxiliary line 120. Therefore, the size of the active region is greatly reduced, and compared with the conventional active region array, the number of the active regions of the active region array formed by the embodiment can be increased by at least 4 times, so that the arrangement density of the active regions is favorably improved, and the utilization rate of the active regions in the array region can be greatly improved.

Specifically, the method for forming the second self-aligned spacer pattern 150 includes the following steps, for example.

Step one, specifically referring to fig. 7a and 7b, forming a self-aligned surrounding pattern 150 on sidewalls of the first self-aligned spacer pattern 130, the self-aligned surrounding pattern 150 surrounding the first self-aligned spacer pattern 131, so that portions of the self-aligned surrounding pattern 150 located on two second lengthwise sidewalls 131a of the first self-aligned spacer pattern 131 are connected to each other on ends of the first self-aligned spacer pattern 131; and the number of the first and second groups,

in the present embodiment, the segment interval dimension Z2 between adjacent first self-aligned spacer patterns 131 arranged in the same line along the first direction is larger and larger than 2 times the lateral film-forming thickness of the self-aligned surround pattern 150 (i.e., the second width dimension W2 of the second self-aligned spacer pattern 151), so that the self-aligned surround pattern 150 has ring-shaped structures surrounding the first self-aligned spacer patterns 131, each of the first self-aligned spacer patterns 131 corresponds to one of the ring-shaped structures, and adjacent ring-shaped structures are spaced apart from each other.

Specifically, the lateral film thickness of the self-aligned surrounding pattern 150 (i.e., the second width dimension W2 of the second self-aligned spacer pattern 151) is also smaller than the auxiliary line width dimension of the auxiliary line, for example, between 25nm and 60 nm.

In addition, two ring-shaped structures adjacent along the second direction (D2 direction) have a second spacing dimension Z3 therebetween, and among the plurality of second self-aligned spacing patterns 151 formed subsequently, the second spacing dimension is provided between the second self-aligned spacing patterns that are formed on the first self-aligned spacing patterns adjacent in the second direction and face each other, respectively. The second spacing dimension Z3 is, for example, between 10nm and 40 nm.

The self-aligned surrounding pattern 150 may also be formed by a self-aligned process, and the forming method thereof may refer to the forming method of the self-aligned continuous pattern 130, which is not described herein again.

Step two, specifically referring to fig. 8a to 9a and 8b to 9b, determining the length of the second self-aligned spacer pattern 151 by using the pattern of the mask 140A, forming at least one set of pairwise pairs of the second self-aligned spacer patterns 151 completely in the device array region 100A and separating them from each other, and removing the first self-aligned spacer patterns 131.

Specifically, a photolithography process is performed on the self-aligned surrounding pattern 150 using the photo-mask 140a, and a portion of the self-aligned surrounding pattern 150 located at an end of the first self-aligned spacer pattern 131 is removed using the cut-off window 141 of the photo-mask 140a, so that two portions of the self-aligned surrounding pattern 150 located on two second length side walls 131a of the first self-aligned spacer pattern 131 are separated from each other, so as to form the second self-aligned spacer pattern 151, wherein two second self-aligned spacer patterns 151 corresponding to the same first self-aligned spacer pattern 131 are arranged in pairs.

In this embodiment, the mask 140a used for forming the second self-aligned spacer patterns 151 may be the same as the mask 140a used for forming the first self-aligned spacer patterns 131. Specifically, when the first self-aligned spacer pattern 131 is formed, the self-aligned continuous pattern 130 is truncated using the mask 140a to form a plurality of segmented first self-aligned spacer patterns 131, and the boundary of the truncated window 141 of the mask 140a corresponds to the outer boundary of the end of the first self-aligned spacer pattern 131. Accordingly, when the self-aligned surrounding pattern 150 is cut off by the mask 140a, the connection portion of the self-aligned surrounding pattern 150 located at the end of the first self-aligned spacer pattern may correspond to the cut-off window 141. Based on this, the photo-mask 140a can be used again to remove the connecting portion of the self-aligned surrounding pattern 150 located at the end of the first self-aligned spacer pattern in the region corresponding to the intercepting window 141 by the etchant 140c, so that each of the ring-shaped structures in the self-aligned surrounding pattern 150 is divided into two second self-aligned spacer patterns 151.

With continued reference to fig. 9a and 9b, after the second self-aligned spacer patterns 151 are formed, the first self-aligned spacer patterns 131 may be removed. Wherein the first self-aligned spacer pattern 131 may be removed after the self-aligned surrounding pattern 150 is formed and before the self-aligned surrounding pattern 150 is etched; of course, the first self-aligned spacer pattern 131 may be removed after the self-aligned surrounding pattern 150 is etched to form a plurality of divided second self-aligned spacer patterns 151.

The material of the self-aligned surrounding pattern 150 (i.e., the material of the second self-aligned spacer pattern 151) may be a material having a larger etching selectivity than the first self-aligned spacer pattern 131. For example, the material of the first self-aligned spacer pattern 131 includes silicon nitride, and the material of the second self-aligned spacer pattern 151 includes silicon oxide; alternatively, the material of the first self-aligned spacer pattern 131 includes silicon oxide, and the material of the second self-aligned spacer pattern 151 includes silicon nitride.

In this regard, a pattern of an active area array can be defined on the substrate 100, wherein the pattern of the plurality of second self-aligned spacer patterns 151 corresponds to the pattern of the plurality of active areas. In a subsequent process, the pattern of the second self-aligned spacer pattern 151 may be copied into the substrate 100.

In this embodiment, a mask layer 110 is further formed on the substrate 100, and during the process of forming the first self-aligned spacer patterns 131 by self-alignment using the auxiliary lines and forming the second self-aligned spacer patterns 151 by self-alignment using the first self-aligned spacer patterns 131 to define the pattern of the active area array, the mask layer 110 is formed on the substrate 110, so that during the above-mentioned manufacturing process, the substrate 100 is effectively prevented from being damaged during the above-mentioned manufacturing process based on the isolation effect of the mask layer 110.

Step S500, specifically referring to fig. 10A and 10b, copies the pattern of the second self-aligned spacer pattern 151 into the substrate 100 to define a plurality of active regions 101 corresponding to the second self-aligned spacer pattern 151 in the element array region 100A of the substrate 100 and form an active region array.

At this time, the width dimension of the active region 101 is equal to or close to the second width dimension W2 of the second self-aligned spacer pattern 151, for example, the width dimension of the active region 101 is 25nm to 60 nm. And a space size between the active regions adjacent along the second direction is the same as or similar to a space size of the second self-aligned space pattern 151 adjacent along the second direction, for example, a space size between the active regions adjacent along the second direction is 10nm to 40 nm.

It should be noted that, when the pattern of the second self-aligned spacer pattern 151 is copied to the substrate 100, a masking mask may be used to cover the peripheral region 100B outside the element array region 100A and expose the element array region 100A, so that the second self-aligned spacer pattern 151 can be copied only to the element array region 100A.

In this embodiment, a mask layer 110 is further formed on the substrate 100, so that the pattern of the second self-aligned spacer pattern 150 may be copied into the mask layer 110 first, and then the substrate 100 is etched by using the mask layer 110 as a mask, so as to be further copied into the substrate 100.

With continued reference to fig. 10a and 10b, when the pattern of the second self-aligned spacer pattern is copied into the substrate 100, a plurality of isolation trenches 102 may be formed in the substrate 100, wherein the plurality of isolation trenches 102 surround the plurality of active regions 101. And a filling medium material layer 103 is further included in the isolation trench 102 after the isolation trench 102 is formed, so as to form an isolation structure. In a preferred embodiment, the dielectric material layer 103 has a dielectric constant (K value) of less than 3, which is beneficial to improve the leakage current of the device and can effectively alleviate the phenomenon of electrical coupling (coupling). The material of the dielectric material layer 103 may include, for example, silicon oxide.

As described above, the second self-aligned spacer pattern in the present embodiment achieves a 4-fold increase in pattern compared to the auxiliary lines, so that the number of active regions in the formed active region array is correspondingly increased by a factor of 4, and the size of the active region in the present embodiment can be greatly reduced compared to the active region formed by the conventional process.

Fig. 11a is a schematic size diagram of an active area repeat unit of an active area array formed by a method for forming an active area array according to an embodiment of the invention. In fig. 11a, patterns of the auxiliary lines 120 and the first self-aligned spacer patterns 131 are superimposed on the active area array pattern to assist in explaining the size of the active area in the active area array pattern.

Referring specifically to fig. 11a, a plurality of active regions 101 in the active region array constitute a plurality of active region repeating units AC, wherein a total width dimension a of the active region repeating units AC in the Y direction includes 3 times an auxiliary line width dimension of an auxiliary line 120 and 3 times an auxiliary line interval dimension between adjacent auxiliary lines 120. As described above, the auxiliary lines 120 are directly defined by the photolithography process, and therefore it is assumed that the auxiliary line width dimension of the auxiliary lines 120 can reach the minimum feature size F of the photolithography process, and the auxiliary line spacing dimension between adjacent auxiliary lines 120 also reaches the minimum feature size F of the photolithography process. Then, it can be derived that the total width dimension a of the active area repeating unit AC in the Y direction is 6F.

And, assuming that the active region 101 formed in the present embodiment only achieves a reduction in width dimension compared to the active region formed by the conventional process (for example, as shown in fig. 1a and 1 b), and the length dimension thereof is not changed, the total width dimension b of the active region repeating unit AC in the X direction may reach 2F at this time. Namely, the cell arrangement size S of the active region repeating unit AC_ACF＝6F×2F。

With continued reference to fig. 11a, each active area repeating unit AC can be used to form 8 device cells, based on which the average layout size S of each of the device cells is known_AF＝S_ACF/8＝1.5F². However, in the conventional active area array shown in fig. 1a and 1b, the average configuration size of each device unit can only reach 6F at the minimum²It can be seen that the average configuration size of the device unit in this embodiment is much smaller than that of the active region formed by the conventional process.

Fig. 11b is a schematic size diagram of an active area of a device unit of an active area array formed by a method for forming the active area array according to an embodiment of the invention. As shown in fig. 11b, in this embodiment, the total width dimension a of the active area repeating unit AC in the Y direction specifically includes: 12 times (12 xw 2) the width dimension (i.e., W2) of the active region, 6 times (6 xw 1) the spacing dimension (i.e., W1) Z1 between two active regions corresponding to both sides of the same first self-aligned spacing pattern, and 6 times (6 xz 3) the spacing dimension (i.e., Z3) between two active regions corresponding to adjacent first self-aligned spacing patterns and facing each other. That is, the total width dimension a of the active region repeating unit AC in the Y direction is (12 × W2) + (6 × W1) +6 × Z3), and the actual total area dimension S of the active region repeating unit AC is_ACT＝a×b＝(12×W2+6×W1+6×Z3)×b。

Wherein, the actual area size S of the active region corresponding to each device unit_ATW2 × b, the actual total area size S of the active region of the 8 device cells in the active region repeat unit AC_A88 × (W2 × b). Based on this, in each active region repeating unit AC, the active region utilization ratio R ═ S for forming the device unit_A8/S_ACT(8 × W2 × b)/((12 × W2+6 × W1+6 × Z3) × b). In the embodiment, the spacing dimension W1 between two active regions corresponding to the same first self-aligned spacer pattern is between 20nm and 50nm, the width dimension W2 of the active regions is between 25nm and 60nm, and the spacing dimension Z3 between two active regions facing each other corresponding to different first self-aligned spacer patterns is between 10nm and 40nm, so that the utilization rate of the active regions can reach 55% in the embodiment.