Digital-to-analog converter
阅读说明:本技术 数字模拟转换器 (Digital-to-analog converter ) 是由 尼森伊根 于 2019-08-22 设计创作,主要内容包括:本发明提供一种数字模拟转换器,包括:第一开关和第二开关;电流源,配置为基于第一信号并通过第一开关将电流推向第一输出节点或从所述第一输出节点拉电流,基于第二信号并通过第二开关将电流推向第二输出节点或从所述第二输出节点拉电流;和开关驱动器,配置为接收数据信号和时钟信号,所述开关驱动器包括第一锁存器、第二锁存器和正反馈电路,其中所述第二锁存器包括用于输出所述第一信号的第一节点和用于输出所述第二信号的第二节点;其中所述第一锁存器包括用于输出第三信号的第三节点和用于输出第四信号的第四节点,所述正反馈电路配置为连接在所述第三节点和所述第四节点之间。可解决导致存储器效应及引入失真的浮动节点问题,及改善了开关驱动器的数据独立性。(The present invention provides a digital-to-analog converter, comprising: a first switch and a second switch; a current source configured to push current to or pull current from a first output node through a first switch based on a first signal and to push current to or pull current from a second output node through a second switch based on a second signal; and a switch driver configured to receive a data signal and a clock signal, the switch driver comprising a first latch, a second latch, and a positive feedback circuit, wherein the second latch comprises a first node for outputting the first signal and a second node for outputting the second signal; wherein the first latch includes a third node for outputting a third signal and a fourth node for outputting a fourth signal, the positive feedback circuit being configured to be connected between the third node and the fourth node. The floating node problem that causes memory effects and introduces distortion can be solved and the data independence of the switch driver is improved.)
1. A digital to analog converter, comprising:
a first switch and a second switch;
a current source configured to push current to or pull current from a first output node through a first switch based on a first signal and to push current to or pull current from a second output node through a second switch based on a second signal; and
a switch driver configured to receive a data signal and a clock signal, the switch driver including a first latch, a second latch, and a positive feedback circuit,
wherein the second latch comprises a first node for outputting the first signal and a second node for outputting the second signal;
wherein the first latch includes a third node for outputting a third signal and a fourth node for outputting a fourth signal, the positive feedback circuit being configured to be connected between the third node and the fourth node.
2. The digital-to-analog converter of claim 1, wherein the positive feedback circuit is configured to receive the clock signal such that the first latch can be reset.
3. The digital-to-analog converter of claim 1, wherein the first latch is configured to receive a data signal and a clock signal.
4. The digital-to-analog converter of claim 1, wherein the second latch includes a fifth node for outputting a fifth signal, the digital-to-analog converter further including a third switch for discarding current to a discard node based on the fifth signal.
5. The digital-to-analog converter of claim 1, wherein the first latch further comprises a sixth node for outputting a sixth signal, the positive feedback circuit further configured to connect the sixth node.
6. The digital-to-analog converter of claim 3,
the data signal includes a first portion and a second portion, an
The first latch includes a third node configured to output a result of an XOR operation of the first portion and the second portion of the data signal.
7. The digital-to-analog converter of claim 1,
the first latch is configured to receive an inverted version of a clock signal, an
The first latch includes two additional output nodes configured to output signals based on an inverted version of the clock signal and the third and fourth signals.
8. The digital-to-analog converter of claim 1, wherein the second latch comprises a level shifting circuit that causes the first switch and the second switch to operate in a saturation region.
9. The digital-to-analog converter of claim 1, wherein the second latch comprises cross-coupled output nodes.
10. The digital-to-analog converter of claim 3,
the clock signal is a first clock signal and,
the second latch is configured to receive a second clock signal, an
The second clock signal is a delayed version of the first clock signal.
11. A digital to analog converter, comprising:
a first switch and a second switch;
a current source configured to push current to or pull current from a first output node through a first switch based on a first signal and to push current to or pull current from a second output node through a second switch based on a second signal; and
a switch driver configured to receive a data signal and a clock signal, the switch driver including a latch including a first node for outputting the first signal and a second node for outputting the second signal, and a positive feedback circuit configured to be connected between the first node and the second node.
12. The digital-to-analog converter of claim 11, wherein the positive feedback circuit is configured to receive the clock signal such that the latch can be reset.
13. The digital-to-analog converter of claim 11,
the latch is a first latch, and the switch driver includes a second latch connected in series with the first latch.
14. The digital-to-analog converter of claim 11,
the first latch includes a transistor of a first type configured to receive a data signal, an
The second latch includes a second type of transistor configured to receive the first signal and the second signal.
15. The digital-to-analog converter of claim 11, wherein the latch further comprises a third node for outputting a third signal, the positive feedback circuit further configured to connect the third node.
16. The digital-to-analog converter of claim 15, further comprising a third switch to dump current to a dump node based on the third signal.
17. A digital to analog converter, comprising:
a first current source configured to push current to a first output node and a second output node;
a second current source configured to source current from the first output node and the second output node; and
a plurality of switching legs configured to be triggered by a first type edge of a clock signal to push current of the first current source to the first output node and to pull current from the second output node to the second current source, and triggered by a subsequent second type edge of the clock signal to push current of the first current source to the second output node and to pull current from the first output node to the second current source.
18. The digital-to-analog converter of claim 17,
the plurality of switching legs is a first plurality of switching legs, the digital-to-analog converter includes a second plurality of switching legs including a dump node configured to direct current to the dump node when the first plurality of switching legs push current toward the first output node and the second output node.
19. The digital-to-analog converter of claim 17,
the plurality of switching legs includes a first switching leg driven by a first signal, and
the first switching leg includes a first switch and a second switch and is configured to be triggered by a first type edge of the clock signal and to push or pull current to or from the first output node based on the first signal.
20. The digital-to-analog converter of claim 19,
the first switch is coupled between the first current source and the second switch,
the second switch is coupled between the first switch and the second current source,
the first output node is located between the first switch and the second switch.
21. The digital-to-analog converter of claim 19,
the plurality of switching legs includes a second switching leg driven by the first signal,
the first signal is coupled to the second switching leg through a latch, and
the second switching leg includes a third switch and a fourth switch and is configured to be triggered by a second type edge of the clock signal and to push current to or pull current from a first output node based on the first signal.
22. The digital-to-analog converter of claim 19,
the plurality of switching legs includes a third switching leg driven by a second signal,
the second signal is an inverted version of the first signal, an
The third switching leg includes a fifth switch and a sixth switch and is configured to be triggered by a first type edge of the clock signal and to push current to or pull current from the second output node based on the second signal.
23. The digital-to-analog converter of claim 20,
the fifth switch is coupled between the first current source and the sixth switch,
the sixth switch is coupled between the fifth switch and the second current source, and
the second output node is located between the fifth switch and the sixth switch.
24. The digital-to-analog converter of claim 20,
the plurality of switching legs includes a fourth switching leg driven by a second signal,
the fourth switching leg includes a seventh switch and an eighth switch and is configured to be triggered by a second type edge of the clock signal and to push current to or pull current from the second output node based on the second signal.
25. The digital-to-analog converter of claim 18,
the plurality of switching legs is a first plurality of switching legs,
the digital-to-analog converter comprises a second plurality of switching legs,
the second plurality of switching legs includes a fifth switching leg driven by a third signal
The fifth switching leg is configured to be triggered by a first type clock edge and to drop current based on a third signal.
26. The digital-to-analog converter of claim 23, wherein the third signal is a result of an XOR operation of the first signal and the second signal.
Technical Field
The present invention relates generally to the field of digital-to-analog conversion, and more particularly to digital-to-analog converters.
Background
Digital-to-Analog converters (DACs) are used to convert Digital signals into Analog signals. For example, a DAC may be employed to generate a voltage waveform based on the stream of digital values. A DAC typically provides an output voltage whose magnitude corresponds to the magnitude of the received digital value. In particular, the output voltage of the DAC may be proportional to the magnitude of the received digital value.
Analog-to-Digital converters (ADCs) are widely used in various electronic devices and systems, such as mobile phones, audio devices, image capture devices, video devices, communication systems, sensors and measurement devices, and radar systems. A typical ADC is an electronic circuit configured to receive an analog signal, usually a time-varying signal, repeatedly sample the analog signal at discrete time intervals, and output, for each sampling interval, a digital signal (e.g., a sequence of bits or a digital word) representative of the value of the analog signal during the sampling interval. Because the output of the ADC is a sequence of N bits, the analog signal is discretized into an integer value where M is 2N. The number N is referred to as the bit resolution of the ADC. For example, if a single-ended ADC is an 8-bit device, the input signal may be discretized into 256 values (0, 1, 2, 3.. 255).
The feedback DAC is used for a delta sigma (delta-sigma) ADC. In delta modulation, changes in the analog signal are encoded, producing a stream of pulses. In delta-sigma modulation, the accuracy of the modulation is improved by the feedback DAC passing a digital output and adding the resulting analog signal to the input signal, thereby reducing the error introduced by delta modulation.
Disclosure of Invention
The present invention provides a digital-to-analog converter, comprising: a first switch and a second switch; a current source configured to push current to or pull current from a first output node through a first switch based on a first signal and to push current to or pull current from a second output node through a second switch based on a second signal; and a switch driver configured to receive a data signal and a clock signal, the switch driver comprising a first latch, a second latch, and a positive feedback circuit, wherein the second latch comprises a first node for outputting the first signal and a second node for outputting the second signal; wherein the first latch includes a third node for outputting a third signal and a fourth node for outputting a fourth signal, the positive feedback circuit being configured to be connected between the third node and the fourth node.
The present invention provides another digital-to-analog converter comprising: a first switch and a second switch; a current source configured to push current to or pull current from a first output node through a first switch based on a first signal and to push current to or pull current from a second output node through a second switch based on a second signal; and a switch driver configured to receive a data signal and a clock signal, the switch driver including a latch including a first node for outputting the first signal and a second node for outputting the second signal, and a positive feedback circuit configured to be connected between the first output node and the second output node.
The switch driver of embodiments of the present invention may include a positive feedback circuit that solves the floating node problem that causes memory effects and introduces distortion and achieves low latency by forcing the latch of the switch driver to make fast decisions (e.g., within 100 ps), in addition to improving the data independence of the switch driver.
The present invention provides another digital-to-analog converter comprising: a first current source configured to push current to a first output node and a second output node; a second current source configured to source current from the first output node and the second output node; and a plurality of switching legs configured to be triggered by a first type edge of a clock signal to push current from the first current source to the first output node and to pull current from the second output node to the second current source, and triggered by a subsequent second type edge of the clock signal to push current from the first current source to the second output node and to pull current from the first output node to the second current source. The embodiment of the invention triggers to push current to the output node or pull current from the output node at the edge of the clock signal, thereby reducing noise.
The foregoing is a summary and thus contains, by necessity, simplifications, generalizations, and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and is not intended to be in any way limiting. Other aspects, inventive features, and advantages of the present invention, as defined solely by the claims, will become apparent in the non-limiting detailed description set forth below.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 depicts an example of a delta-sigma analog-to-digital converter (ADC)
Fig. 2 depicts a simplified block diagram of a
Fig. 3A depicts an exemplary dual-bit-
Fig. 3B depicts an exemplary
Fig. 4A depicts an exemplary three-
Fig. 4B depicts an exemplary
A portion of the
Fig. 5 depicts an exemplary dual-bit-level
Fig. 6 depicts an exemplary three-order
Detailed Description
Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This specification and claims do not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. By "substantially" it is meant within an acceptable error range, within which one skilled in the art would be able to solve the technical problem to substantially achieve the technical result. Furthermore, the term "coupled" is intended to include any direct or indirect electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. The following is a preferred embodiment of the invention for the purpose of illustrating the spirit of the invention and not for the purpose of limiting the scope of the invention, which is defined in the appended claims.
The following description is of the best embodiments contemplated by the present invention. The description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention should be determined with reference to the claims that follow.
Described herein are apparatus and methods for converting digital signals to analog signals at high frequencies (e.g., at least 1GHz or 2GHz or 7GHz or 9 GHz). The inventors have recognized and appreciated that digital-to-analog converters (DACs) operating at high frequencies suffer from higher distortion, e.g., caused by code-dependent spurs, and higher power consumption, which may increase linearly with clock frequency. The inventors have recognized and appreciated apparatus and methods that enable DACs to operate at high frequencies with linear output, low distortion, low power consumption and input data independence.
In some embodiments, the DAC may operate in a current steering mode configured to convert a digital signal received by the DAC into a current that is an analog representation of the digital input signal. In some embodiments, the DAC may operate in a bipolar four (quad) or sixteen (hex) switching scheme configured to be triggered by each edge of the clock signal and to push (push) and pull (pull) current to or from the positive output node depending on the digital signal received by the DAC. In some embodiments, the digital signal received by the DAC may be decoded into a variety of formats, including, for example, a dual-level (dual-level) format and a tri-level (tri-level) format. In some embodiments, when the received digital signal is decoded into a dual-level format, the DAC may be configured to direct current from the positive output node to the negative output node or from the negative output node to the positive output node triggered by an edge of the clock signal. In some embodiments, when the received digital signal is decoded into a three-level format, the DAC may be configured to be triggered by an edge of the clock signal to direct current to either the positive output node or the negative output node, or to drop (dump) current to a drop node (dump node), which may be driven by the amplifier.
In some embodiments, the DAC may include a switch driver and an output switch driven by the switch driver. In some embodiments, the switch driver may include a positive feedback circuit that addresses floating node issues that cause memory effects and introduce distortion, and achieves low latency by forcing the latch of the switch driver to make fast decisions (e.g., within 100 ps). In some embodiments, the switch driver may reduce latency by integrating an exclusive or gate (XOR) into a latch of the switch driver when the received digital signal is decoded into a three-level format. In some embodiments, the output switch may be configured to switch (toggle) each clock edge to obtain low noise and push current to and pull current from the DAC output. In some embodiments, the additional output switch may be configured to dump current to the dump node when the received digital signal is decoded into a three-level format, which reduces noise.
One or more DACs may be used in the system for converting digital signals to analog signals. Fig. 1 depicts an example of such a
The illustrated example is for guidance purposes only and is not intended to limit the architecture of the system to the illustrated delta-sigma ADC. In some embodiments, the system may be a direct RF sampling delta-sigma ADC configured to operate without an external band pass filter, which may be activated by one or more high speed DACs according to some embodiments.
Fig. 2 depicts a simplified block diagram of a
Table I illustrates an exemplary relationship between the encoded
Table II shows an exemplary relationship between the encoded
It should be appreciated that any suitable decoder may be used to convert the encoded
Table I: according to some embodiments, an exemplary relationship between an encoded input signal to a DAC decoder and a decoded signal in a dual-level format to a switch driver.
Input signal S<15:0>
P<15:0>
N<15:0>
1111 1111 1111 1111
1111 1111 1111 1111
0000 0000 0000 0000
0111 1111 1111 1111
0111 1111 1111 1111
0000 0000 0000 0001
0011 1111 1111 1111
0011 1111 1111 1111
0000 0000 0000 0011
0001 1111 1111 1111
0001 1111 1111 1111
0000 0000 0000 0111
0000 1111 1111 1111
0000 1111 1111 1111
0000 0000 0000 1111
0000 0111 1111 1111
0000 0111 1111 1111
0000 0000 0001 1111
0000 0011 1111 1111
0000 0011 1111 1111
0000 0000 0011 1111
0000 0001 1111 1111
0000 0001 1111 1111
0000 0000 0111 1111
0000 0000 1111 1111
0000 0000 1111 1111
0000 0000 1111 1111
0000 0000 0111 1111
0000 0000 0111 1111
0000 0001 1111 1111
0000 0000 0011 1111
0000 0000 0011 1111
0000 0011 1111 1111
0000 0000 0001 1111
0000 0000 0001 1111
0000 0111 1111 1111
0000 0000 0000 1111
0000 0000 0000 1111
0000 1111 1111 1111
0000 0000 0000 0111
0000 0000 0000 0111
0001 1111 1111 1111
0000 0000 0000 0011
0000 0000 0000 0011
0011 1111 1111 1111
0000 0000 0000 0001
0000 0000 0000 0001
0111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
Table II: according to some embodiments, an exemplary relationship between an encoded input signal to a DAC decoder and a decoded signal in a three-level format to a switch driver.
Referring again to fig. 2, the
In some embodiments, the
The
Fig. 3A depicts an exemplary dual-bit-
The
The
The
Fig. 4A depicts an exemplary three-
In some embodiments, the
Unlike the
The inventors have recognized and appreciated that, similar to the
The inventors have recognized and appreciated that an output switch circuit configuration enables the use of Nyquist zones (Nyquist zones) other than the first Nyquist zone to operate the output switch circuit to reconstruct the received drive signal. The nyquist zone may define a frequency band that is one-half the sampling frequency width (e.g., the frequency of the clock signal received by the DAC). The first nyquist zone may extend from 0Hz to half the sampling frequency. The second nyquist zone may extend from half the sampling frequency to the sampling frequency, and so on.
Fig. 5 depicts an exemplary dual-bit-level
The
The
Fig. 6 depicts an exemplary three-order
The
The
Various aspects of the devices and techniques described herein may be used alone, in combination, or in a variety of arrangements not specifically discussed in the embodiments described in the foregoing description, and is therefore not limited in their application to the details of the foregoing components and arrangements or to the details shown in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments.
In some embodiments, the terms "about," "approximately," and "approximately" may be used to denote a range of ± 10% less than a target value and may include the target value. For example: less than + -5% of the target value and less than + -1% of the target value.
Use of ordinal terms such as "first," "second," "third," etc., in the claims to modify a claim element does not imply any priority or order, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name.
Although the present invention has been described with reference to particular embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
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