阅读说明：本技术 一种衬底辅助触发与电压钳位的esd/eos防护方法 (ESD/EOS protection method for substrate auxiliary trigger and voltage clamp ) 是由 梁海莲 冯希昆 顾晓峰 于 2019-11-19 设计创作，主要内容包括：本发明公开了一种衬底辅助触发与电压钳位的ESD/EOS防护方法,属于集成电路的静电放电防护及抗浪涌领域。本发明提供的衬底辅助触发与电压钳位的ESD/EOS防护器件,可用于提高集成电路的抗ESD/EOS能力。本发明方法的应用电路单元主要由P衬底、第一N阱、第二N阱、P阱、第一P+注入区、第二P+注入区、第三P+注入区、第四P+注入区、第四P+注入区、第五P+注入区、第六P+注入区、第一N+注入区、第二N+注入区、第三N+注入区、第四N+注入区、第五N+注入区、第六N+注入区、多晶硅栅以及其覆盖的薄栅氧化层、金属线构成。本发明可降低触发电压、提高开启速度快,增强ESD鲁棒性,避免闩锁效应并增强单位面积防护效率。(The invention discloses an ESD/EOS (electro static discharge/EOS) protection method for substrate auxiliary triggering and voltage clamping, belonging to the field of electrostatic discharge protection and anti-surge of an integrated circuit. The ESD/EOS protection device with the substrate auxiliary trigger and the voltage clamp provided by the invention can be used for improving the ESD/EOS resistance of an integrated circuit. The application circuit unit of the method mainly comprises a P substrate, a first N well, a second N well, a P well, a first P + injection region, a second P + injection region, a third P + injection region, a fourth P + injection region, a fifth P + injection region, a sixth P + injection region, a first N + injection region, a second N + injection region, a third N + injection region, a fourth N + injection region, a fifth N + injection region, a sixth N + injection region, a polysilicon gate, a thin gate oxide layer covered by the polysilicon gate and a metal wire. The invention can reduce the trigger voltage, improve the starting speed, enhance the ESD robustness, avoid the latch-up effect and enhance the unit area protection efficiency.)

1. An ESD and/or EOS protection device is characterized in that the device is triggered by a substrate in an auxiliary mode and clamped by voltage, comprises an embedded MOS, an SCR, a Zener diode structure and a metal wire, and particularly mainly comprises a P substrate (100), a P well (101), a first N well (102), a second N well (103), a first N + injection region (104), a first P + injection region (105), a second N + injection region (106), a third N + injection region (107), a fourth N + injection region (108), a fifth N + injection region (109), a second P + injection region (110), a sixth N + injection region (111), a third P + injection region (112), a fourth P + injection region (113), a fifth P + injection region (114), a sixth P + injection region (115), a polysilicon gate (116) and a thin gate oxide layer (117) covered by the P substrate;

the upper surface area of the P substrate (100) is sequentially provided with a first N well (102), a P well (101) and a second N well (103) from left to right, the left edge of the P well (101) is connected with the right edge of the first N well (102), and the right edge of the P well (101) is connected with the left edge of the second N well (103);

a first N + injection region (104) and a first P + injection region (105) are sequentially arranged on the surface region of the first N well (102) from left to right along the length direction;

a second N + injection region (106) spans the surface region between the first N well (102) and the P well (101), a safety distance is arranged between the second N + injection region (106) and the first P + injection region (105), a fifth N + injection region (109) spans the surface region between the P well (101) and the second N well (103), and a safety distance is arranged between the fifth N + injection region (109) and the second P + injection region (110);

a third P + injection region (112), a third N + injection region (107), a fifth P + injection region (114), a polysilicon gate (116) and a thin gate oxide layer (117), a fourth P + injection region (113), a fourth N + injection region (108) and a sixth P + injection region (115) which are covered by the polysilicon gate (116) are arranged in the surface region of the P well (101) between the second N + injection region (106) and the fifth N + injection region (109);

in the surface area between the second N + injection region (106) and the polysilicon gate (116) and the thin gate oxide layer (117) covered by the polysilicon gate, a fifth P + injection region (114), a third N + injection region (107) and a third P + injection region (112) are all arranged in alignment along the width direction, the left side of the third N + injection region (107) is connected with the right side edge of the second N + injection region (106), a safety interval is arranged between the fifth P + injection region (114) and the third P + injection region (112) and the right side of the second N + injection region (106), and the right side edges of the fifth P + injection region (114), the third N + injection region (107) and the third P + injection region (112) are all connected with the polysilicon gate (116) and the left side edge of the thin gate oxide layer (117) covered by the polysilicon gate (116);

in the surface area between the polysilicon gate (116) and the thin gate oxide layer (117) and the fifth N + injection region (109) covered by the polysilicon gate, the sixth P + injection region (115), the fourth N + injection region (108) and the fourth P + injection region (113) are all arranged in alignment along the width direction, the left edges of the sixth P + injection region (115), the fourth N + injection region (108) and the fourth P + injection region (113) are all connected with the polysilicon gate (116) and the right edge of the thin gate oxide layer (117) covered by the polysilicon gate, the right edge of the fourth N + injection region (108) is connected with the left edge of the fifth N + injection region (109), and a safety interval is arranged between the sixth P + injection region (115) and the fourth P + injection region (113) and the left side of the fifth N + injection region (109);

a second P + injection region (110) and a sixth N + injection region (111) are sequentially arranged on the surface region of the second N well (103) from left to right, and a safety interval is arranged between the fifth N + injection region (109) and the second P + injection region (110);

the metal wire is used for connecting the injection region and the polysilicon gate, two electrodes are led out from the metal wire and are respectively used as a forward conduction loop and a reverse conduction loop of a circuit, the first N + injection region (104) is connected with the first metal 1(201), the first P + injection region (105) is connected with the second metal 1(202), the third P + injection region (112) is connected with the third metal 1(203), the fourth P + injection region (113) is connected with the fourth metal 1(204), the second P + injection region (110) is connected with the fifth metal 1(205), the sixth N + injection region (111) is connected with the sixth metal 1(206), the fifth P + injection region (114) is connected with the seventh metal 1(207), the sixth P + injection region (115) is connected with the eighth metal 1(208), and the polysilicon gate (116) is connected with the ninth metal 1(209) and the tenth metal 1 (210);

the first metal 1(201), the second metal 1(202) are connected with the first metal 2(211), the seventh metal 1(207), the eighth metal 1(208), the tenth metal 1(210) are connected with the second metal 2(212), the third metal 1(203), the fourth metal 1(204), the ninth metal 1(209) are connected with the third metal 2(213), the fifth metal 1(205), the sixth metal 1(206) are connected with the fourth metal 2 (214);

a first electrode (301) is led out from the first metal 2(211) to serve as a first electrical stress end of the protection circuit, and a second electrode (302) is led out from the fourth metal 2(214) to serve as a second electrical stress end of the protection circuit.

2. An ESD and/or EOS protection device according to claim 1, characterized in that the first N + implant region (104), the first P + implant region (105), the second N + implant region (106), the third N + implant region (107), the fifth P + implant region (114), the third P + implant region (112) and the sixth N + implant region (111), the second P + implant region (110), the fifth N + implant region (109), the fourth N + implant region (108), the sixth P + implant region (115), the fourth P + implant region (113) are fully symmetric layout and circuit structure centered around the silicon gate (116) and its overlying thin gate oxide (117), when between the first electrode (301) and the second electrode (302) of the circuit, the internal electrical characteristics under forward electrical stress and the internal electrical characteristics under reverse electrical stress are the same, no matter the forward and reverse electrical stress is applied, has the functions of bidirectional overvoltage protection, overcurrent protection or surge resistance.

3. The ESD and/or EOS protection device according to claim 1, wherein when the first electrode (301) is connected to a high potential and the second electrode (302) is connected to ground, a forward auxiliary trigger MOS is formed by the third N + injection region (107), the polysilicon gate (116), and the covered thin gate oxide layer (117) and the fourth N + injection region (108), so that a trigger voltage of the circuit can be reduced, and by adjusting the width of the forward MOS auxiliary trigger structure, current conduction uniformity inside the circuit is improved, a current heat accumulation effect is weakened, and ESD robustness of the circuit is enhanced.

4. An ESD and/or EOS protection device according to claim 1, wherein: the MOS triggered in the forward direction is formed by a third N + injection region (107), a polysilicon gate (116), a thin gate oxide layer (117) covered by the third N + injection region and a fourth N + injection region (108), the polysilicon gate of the MOS triggered in the forward direction is connected to a third P + injection region (112), a fourth P + injection region (113), a fifth P + injection region (114) and a sixth P + injection region (115) through metal wires, and when a circuit is under the action of electrical stress, substrate leakage current can provide weak potential for the polysilicon gate of the MOS triggered in the assisting mode through a substrate resistor, so that the circuit is promoted to be opened quickly.

5. An ESD and/or EOS protection device according to claim 1, wherein: by adjusting the distance between the fifth N + injection region (109) and the second P + injection region (110) and the distance between the first P + injection region (105) and the second N + injection region (106), a first Zener diode (Z1) and a second Zener diode (Z2) are respectively formed, and when the circuit is conducted, both Z1 and Z2 have a voltage clamping effect, so that the voltage hysteresis amplitude is reduced, and the latch-up resistance of the circuit is enhanced.

6. An ESD and/or EOS protection device according to claim 1, wherein: the application circuit units can be stacked along the width direction, and the ESD/EOS resistance robustness of the circuit is enhanced.

7. An ESD/EOS protection method is characterized in that a substrate is triggered and clamped with voltage in an auxiliary mode, firstly, an MOS is embedded into a circuit to trigger an SCR in an auxiliary mode, and the trigger voltage of a device is reduced; secondly, a Zener diode is embedded in the SCR path, and the voltage clamping function of the Zener diode is utilized to clamp the maintaining voltage of the circuit at a higher potential, so that the latch-up problem is avoided; thirdly, by connecting the MOS grid electrode with the substrate resistor, the substrate leakage current can provide a weak potential for the polysilicon gate of the MOS through the substrate resistor, and the device is promoted to be quickly started; finally, by designing an application circuit with a symmetrical structure, the same internal electrical characteristics under the action of forward and reverse electrical stress are realized, and the bidirectional overvoltage, overcurrent protection or surge resistance function is realized.

8. The ESD/EOS protection method according to claim 7, wherein a device having the following structure is prepared and used for protection;

the device comprises: the field effect transistor comprises a P substrate (100), a P well (101), a first N well (102), a second N well (103), a first N + injection region (104), a first P + injection region (105), a second N + injection region (106), a third N + injection region (107), a fourth N + injection region (108), a fifth N + injection region (109), a second P + injection region (110), a sixth N + injection region (111), a third P + injection region (112), a fourth P + injection region (113), a fifth P + injection region (114), a sixth P + injection region (115), a silicon gate (116) and a thin gate oxide layer (117) covered by the P substrate;

the upper surface area of the P substrate (100) is sequentially provided with a first N well (102), a P well (101) and a second N well (103) from left to right, the left edge of the P well (101) is connected with the right edge of the first N well (102), and the right edge of the P well (101) is connected with the left edge of the second N well (103);

a first N + injection region (104) and a first P + injection region (105) are sequentially arranged on the surface region of the first N well (102) from left to right along the length direction;

a second N + injection region (106) spans the surface region between the first N well (102) and the P well (101), a safety distance is arranged between the second N + injection region (106) and the first P + injection region (105), a fifth N + injection region (109) spans the surface region between the P well (101) and the second N well (103), and a safety distance is arranged between the fifth N + injection region (109) and the second P + injection region (110);

a third P + injection region (112), a third N + injection region (107), a fifth P + injection region (114), a polysilicon gate (116) and a thin gate oxide layer (117), a fourth P + injection region (113), a fourth N + injection region (108) and a sixth P + injection region (115) which are covered by the polysilicon gate (116) are arranged in the surface region of the P well (101) between the second N + injection region (106) and the fifth N + injection region (109);

in the surface area between the second N + injection region (106) and the polysilicon gate (116) and the thin gate oxide layer (117) covered by the polysilicon gate, a fifth P + injection region (114), a third N + injection region (107) and a third P + injection region (112) are all arranged in alignment along the width direction, the left side of the third N + injection region (107) is connected with the right side edge of the second N + injection region (106), a safety interval is arranged between the fifth P + injection region (114) and the third P + injection region (112) and the right side of the second N + injection region (106), and the right side edges of the fifth P + injection region (114), the third N + injection region (107) and the third P + injection region (112) are all connected with the polysilicon gate (116) and the left side edge of the thin gate oxide layer (117) covered by the polysilicon gate (116);

in the surface area between the polysilicon gate (116) and the thin gate oxide layer (117) and the fifth N + injection region (109) covered by the polysilicon gate, the sixth P + injection region (115), the fourth N + injection region (108) and the fourth P + injection region (113) are all arranged in alignment along the width direction, the left edges of the sixth P + injection region (115), the fourth N + injection region (108) and the fourth P + injection region (113) are all connected with the polysilicon gate (116) and the right edge of the thin gate oxide layer (117) covered by the polysilicon gate, the right edge of the fourth N + injection region (108) is connected with the left edge of the fifth N + injection region (109), and a safety interval is arranged between the sixth P + injection region (115) and the fourth P + injection region (113) and the left side of the fifth N + injection region (109);

a second P + injection region (110) and a sixth N + injection region (111) are sequentially arranged on the surface region of the second N well (103) from left to right, and a safety interval is arranged between the fifth N + injection region (109) and the second P + injection region (110);

the metal wire is used for connecting the injection region and the polysilicon gate, two electrodes are led out from the metal wire and are respectively used as a forward conduction loop and a reverse conduction loop of a circuit, the first N + injection region (104) is connected with the first metal 1(201), the first P + injection region (105) is connected with the second metal 1(202), the third P + injection region (112) is connected with the third metal 1(203), the fourth P + injection region (113) is connected with the fourth metal 1(204), the second P + injection region (110) is connected with the fifth metal 1(205), the sixth N + injection region (111) is connected with the sixth metal 1(206), the fifth P + injection region (114) is connected with the seventh metal 1(207), the sixth P + injection region (115) is connected with the eighth metal 1(208), and the polysilicon gate (116) is connected with the ninth metal 1(209) and the tenth metal 1 (210);

the first metal 1(201), the second metal 1(202) are connected with the first metal 2(211), the seventh metal 1(207), the eighth metal 1(208), the tenth metal 1(210) are connected with the second metal 2(212), the third metal 1(203), the fourth metal 1(204), the ninth metal 1(209) are connected with the third metal 2(213), the fifth metal 1(205), the sixth metal 1(206) are connected with the fourth metal 2 (214);

a first electrode (301) is led out from the first metal 2(211) to serve as a first electrical stress end of the protection circuit, and a second electrode (302) is led out from the fourth metal 2(214) to serve as a second electrical stress end of the protection circuit.

9. Use of an ESD and/or EOS protection device according to any of claims 1 to 6 for electrostatic discharge and electrostatic overstress protection.

10. An integrated circuit comprising an ESD and/or EOS protection device as claimed in any one of claims 1 to 6.

Technical Field

The invention belongs to the field of electrostatic discharge protection and surge resistance of integrated circuits, relates to an ESD protection or surge resistance circuit, and particularly relates to an ESD/EOS protection method for substrate auxiliary triggering and voltage clamping.

Background

With the development of semiconductor technology, the circuit integration degree is continuously expanded, and the electrical performance is also continuously improved. However, as the integration scale is increased, the process size is reduced, and the reliability of Integrated Circuits (ICs) and electronic products is becoming more and more significant, mainly due to the significant process variation and the increased power consumption per unit area. As a result, the electrostatic discharge (ESD) and Electrostatic Overstress (EOS) protection capabilities of ICs and electronics are diminished, which has formed a major factor in failure or damage to the IC and electronics systems. The problem of reduced product yield due to ESD/EOS has caused enormous economic losses in the electronics industry worldwide each year. The major agenda for solving the ESD/EOS problem has been proposed by colleges and universities, research institutes and enterprises at home and abroad, and the ESD/EOS unit libraries of various chips are researched, so that the yield of IC and electronic products is improved, and the production cost is reduced. Therefore, the research and design of the high-efficiency ESD/EOS protection method have important scientific research significance and economic value.

Currently, in the IC design process, a large-scale grounded gate N-type field effect transistor (GGNMOS) with an interdigital structure is commonly used to realize ESD/EOS protection. However, this approach has some drawbacks, such as: the occupied chip area is large; the interdigital structure is easy to cause the problem of uneven current distribution, is influenced by the current heat accumulation effect, and has poor ESD robustness of a circuit on a unit area; under forward electrical stress, the GGNMOS has normal ESD/EOS protection characteristics, but under reverse electrical stress, the GGNMOS is in an on state, the leakage current is large, and the normal operation of an internal core circuit is seriously influenced. In recent years, the SCR structure has attracted much attention in the industry due to its advantage of strong ESD robustness per unit area, however, the short plate with too high SCR trigger voltage, easy latch-up and large leakage current makes it difficult to be directly applied to the ESD/EOS protection field of the integrated circuit.

Disclosure of Invention

[ problem ] to

The ESD protection method aims at the problems that in the traditional ESD/EOS protection scheme, latch-up is easy, ESD robustness on unit area is poor, the protection direction is single and the like.

[ solution ]

The invention provides an ESD/EOS protection method of substrate auxiliary trigger and voltage clamp, which is characterized in that the applied circuit structure is completely symmetrical, and various circuit structures are compounded through the optimized design on a layout structure, so that the bidirectional ESD/EOS protection function can be realized, and the protection circuit can be ensured to have lower trigger voltage, better latch-up resistance and stronger ESD robustness. Specifically, firstly, the MOS is embedded in the circuit to assist in triggering the SCR, so that the triggering voltage of the device can be reduced; secondly, by embedding a Zener diode in the SCR path, the voltage clamping function of the Zener diode is utilized to clamp the maintaining voltage of the circuit at a higher potential, so that the latch-up problem is avoided; then, by connecting the MOS grid with the substrate resistor, the substrate leakage current can provide a weak potential for the polysilicon gate of the MOS through the substrate resistor, and the device can be promoted to be quickly started; finally, by designing an application circuit with a symmetrical structure, the internal electrical characteristics under the action of forward and reverse electrical stress can be the same, and the bidirectional overvoltage, overcurrent protection or surge resistance function is realized.

The invention provides an ESD/EOS (electro-static discharge/oxide-semiconductor) protection device with substrate-assisted triggering and voltage clamping, which comprises an embedded MOS (metal oxide semiconductor), an SCR (silicon controlled rectifier), a Zener diode structure and a metal wire, wherein an application circuit mainly comprises a P substrate, a P well, a first N well, a second N well, a first N + injection region, a first P + injection region, a second N + injection region, a third N + injection region, a fourth N + injection region, a fifth N + injection region, a second P + injection region, a sixth N + injection region, a third P + injection region, a fourth P + injection region, a fifth P + injection region, a sixth P + injection region, a polysilicon gate and a thin gate oxide layer covered by the polysilicon gate;

the upper surface area of the P substrate is sequentially provided with a first N trap, a P trap and a second N trap from left to right, the left edge of the P trap is connected with the right edge of the first N trap, and the right edge of the P trap is connected with the left edge of the second N trap;

a first N + injection region and a first P + injection region are sequentially arranged on the surface region of the first N well from left to right along the length direction;

the second N + injection region spans the surface region between the first N well and the P well, a safety space is arranged between the second N + injection region and the first P + injection region, the fifth N + injection region spans the surface region between the P well and the second N well, and a safety space is arranged between the fifth N + injection region and the second P + injection region;

a third P + injection region, a third N + injection region, a fifth P + injection region, a polysilicon gate and a thin gate oxide layer, a fourth P + injection region, a fourth N + injection region and a sixth P + injection region which are covered by the polysilicon gate are arranged in the surface region of the P well between the second N + injection region and the fifth N + injection region;

in the surface area between the second N + injection region and the polysilicon gate and the thin gate oxide layer covered by the polysilicon gate, a fifth P + injection region, a third N + injection region and a third P + injection region are all arranged in alignment along the width direction, the left side of the third N + injection region is connected with the right side edge of the second N + injection region, a safety interval is arranged between the fifth P + injection region and the right side of the second N + injection region, and the right side edges of the fifth P + injection region, the third N + injection region and the third P + injection region are all connected with the left side edge of the polysilicon gate and the thin gate oxide layer covered by the polysilicon gate;

in the surface area between the polycrystalline silicon gate and the thin gate oxide layer covered by the polycrystalline silicon gate and the fifth N + injection area, a sixth P + injection area, a fourth N + injection area and a fourth P + injection area are all arranged in alignment along the width direction, the left side edges of the sixth P + injection area, the fourth N + injection area and the fourth P + injection area are all connected with the polycrystalline silicon gate and the right side edge of the thin gate oxide layer covered by the polycrystalline silicon gate, the right side edge of the fourth N + injection area is connected with the left side edge of the fifth N + injection area, and a safety interval is arranged between the sixth P + injection area and the left side of the fifth N + injection area;

a second P + injection region and a sixth N + injection region are sequentially arranged on the surface region of the second N well from left to right, and a safety space is arranged between the fifth N + injection region and the second P + injection region;

the metal wire is used for connecting the injection region with the polysilicon gate, two electrodes are led out from the metal wire and are respectively used as a forward conduction loop and a reverse conduction loop of a circuit, the first N + injection region is connected with the first metal 1, the first P + injection region is connected with the second metal 1, the third P + injection region is connected with the third metal 1, the fourth P + injection region is connected with the fourth metal 1, the second P + injection region is connected with the fifth metal 1, the sixth N + injection region is connected with the sixth metal 1, the fifth P + injection region is connected with the seventh metal 1, the sixth P + injection region is connected with the eighth metal 1, and the polysilicon gate is connected with the ninth metal 1 and the tenth metal 1;

the first metal 1 and the second metal 1 are connected with the first metal 2, the seventh metal 1, the eighth metal 1 and the tenth metal 1 are connected with the second metal 2, the third metal 1, the fourth metal 1 and the ninth metal 1 are connected with the third metal 2, and the fifth metal 1 and the sixth metal 1 are connected with the fourth metal 2;

a first electrode is led out from the first metal 2 and serves as a first electrical stress end of the protection circuit, and a second electrode is led out from the fourth metal 2 and serves as a second electrical stress end of the protection circuit.

The invention has the beneficial effects that:

1. the ESD/EOS protection device with substrate auxiliary triggering and voltage clamping provided by the invention has the advantages that the first N + injection region, the first P + injection region, the second N + injection region, the third N + injection region, the fifth P + injection region, the third P + injection region, the sixth N + injection region, the second P + injection region, the fifth N + injection region, the fourth N + injection region, the sixth P + injection region and the fourth P + injection region are fully symmetrical layouts and circuit structures taking a polycrystalline silicon grid and a thin grid oxide layer covered by the polycrystalline silicon grid as centers, when a first electrode and a second electrode of a circuit are arranged between the first electrode and the second electrode, no matter forward and reverse electrical stress is applied, the internal electrical characteristics under the action of the forward electrical stress and the internal electrical characteristics under the action of the reverse electrical stress in the circuit are the same, and the ESD/EOS protection device has the functions of bidirectional overvoltage protection, overcurrent protection or anti-surge.

2. According to the ESD/EOS protection device for substrate auxiliary triggering and voltage clamping, when the first electrode is connected with a high potential and the second electrode is grounded, the third N + injection region, the polysilicon gate, the thin gate oxide layer covered by the polysilicon gate and the fourth N + injection region form a forward auxiliary triggering MOS, the triggering voltage of a circuit can be reduced, the current conduction uniformity in the circuit can be improved by adjusting the width of the forward MOS auxiliary triggering structure, the current heat accumulation effect is weakened, and the ESD robustness of the circuit is enhanced.

3. The ESD/EOS protection device of the substrate auxiliary trigger and voltage clamp comprises an MOS (metal oxide semiconductor) of a forward auxiliary trigger, wherein a third N + injection region, a polysilicon gate, a thin gate oxide layer covered by the polysilicon gate and a fourth N + injection region form the MOS of the forward auxiliary trigger, the polysilicon gate of the forward auxiliary trigger is connected to the third P + injection region, the fourth P + injection region, the fifth P + injection region and the sixth P + injection region through metal wires, and when a circuit is under the action of electrical stress, the substrate leakage current can provide weak potential for the polysilicon gate of the MOS of the auxiliary trigger through a substrate resistor, so that the circuit can be promoted to be quickly started.

4. According to the ESD/EOS protection device with the substrate auxiliary triggering and voltage clamping, the first Zener diode and the second Zener diode can be formed by adjusting the distance between the fifth N + injection region and the second P + injection region and the distance between the first P + injection region and the second N + injection region respectively, and when a circuit is conducted, the Z1 and the Z2 have a voltage clamping effect, so that the voltage hysteresis amplitude can be reduced, and the latch-up resistance of the circuit is enhanced.

5. The ESD/EOS protective device of the substrate auxiliary trigger and voltage clamp can be stacked along the width direction, and the ESD/EOS robustness of the circuit is enhanced.

Drawings

FIG. 1 is a three-dimensional block diagram of a device of the present invention;

FIG. 2 is a metal wiring diagram of the device of the present invention;

FIG. 3 is a different cross-sectional position of the device structure of the present invention;

FIG. 4 is a cross-sectional view of the device along direction AA';

fig. 5 is a cross-sectional view of the device along the BB' direction.

100: p substrate, 101: p-well, 102: first N-well, 103: second N-well, 104: first N + implant region, 105: first P + implant region, 106: second N + implant region, 107: third N + implant region, 108: fourth N + implant region, 109: fifth N + implant region, 110: second P + implant region, 111: sixth N + implant region, 112: third P + implant region, 113: fourth P + implant region, 114: fifth P + implant region, 115: sixth P + implant region, 116: polysilicon gate, 117: a thin gate oxide layer covered by the polysilicon gate;

201: first metal 1, 202: second metal 1, 203: third metal 1, 204: fourth metal 1, 205: fifth metal 1, 206: sixth metal 1, 207: seventh metal 1, 208: eighth metal 1, 209: ninth metal 1, 210: tenth metal 1, 211: first metal 2, 212: second metal 2, 213: third metal 2, 214: a fourth metal 2;

301: first electrode, 302: a second electrode;

z1: first zener diode, Z2: a second zener diode.

Detailed Description

The invention is explained in more detail below with reference to the drawing and example 1: