阅读说明：本技术 间隙填充层、其形成方法、以及半导体装置 (Gap filling layer, method for forming the same, and semiconductor device ) 是由 申美笑 闵忠基 金己焕 金相赫 金孝亭 林根元 于 2019-09-05 设计创作，主要内容包括：本申请提供了包括间隙填充层的装置、形成间隙填充层的方法、以及半导体装置。包括间隙填充层的装置可包括在下层上的上层,其限定从上层的顶表面朝着下层延伸的沟槽,并且间隙填充层可以是填充沟槽的多层结构。间隙填充层可包括：第一介电层,其填充沟槽的第一部分并具有靠近上层的顶表面的顶表面；第二介电层,其填充沟槽的第二部分并具有靠近上层的顶表面并且比第一介电层的顶表面更朝着下层凹陷的顶表面；以及第三介电层,其填充沟槽的剩余部分并覆盖第二介电层的顶表面。(The application provides a device including a gap filling layer, a method of forming the gap filling layer, and a semiconductor device. The apparatus including the gap filling layer may include an upper layer on a lower layer that defines a trench extending from a top surface of the upper layer toward the lower layer, and the gap filling layer may be a multi-layer structure that fills the trench. The gap filling layer may include: a first dielectric layer filling a first portion of the trench and having a top surface proximate to a top surface of the upper layer; a second dielectric layer filling a second portion of the trench and having a top surface that is close to a top surface of the upper layer and is recessed more toward the lower layer than a top surface of the first dielectric layer; and a third dielectric layer filling the remaining portion of the trench and covering the top surface of the second dielectric layer.)

1. An apparatus having a gap fill layer, comprising:

a lower layer;

an upper layer on the lower layer defining a trench extending from a top surface of the upper layer toward the lower layer; and

the gap filling layer filling the trench, the gap filling layer having a multi-layer structure, the gap filling layer including:

a first dielectric layer filling a first portion of the trench, a top surface of the first dielectric layer being proximate to a top surface of the upper layer;

a second dielectric layer filling a second portion of the trench, a top surface of the second dielectric layer being proximate to a top surface of the upper layer, the top surface of the second dielectric layer being recessed toward the lower layer more than the top surface of the first dielectric layer; and

a third dielectric layer filling the remaining portion of the trench and covering a top surface of the second dielectric layer.

2. The apparatus of claim 1, wherein,

the first dielectric layer has a U-shape, and

the first dielectric layer includes two top ends on an inner sidewall surface of the trench, the two top ends of the first dielectric layer being adjacent to a top surface of the upper layer.

3. The apparatus of claim 2, wherein each of the two top ends of the first dielectric layer is exposed at a top surface of the upper layer.

4. The apparatus of claim 2, wherein a top surface of each of the two top ends of the first dielectric layer is at a level above a top surface of the lower layer that is equal to or less than a level of a top surface of the upper layer.

5. The apparatus of claim 2, wherein the third dielectric layer further covers the two top ends of the first dielectric layer.

6. The device of claim 1, wherein an interface between the second dielectric layer and the third dielectric layer has a concave shape toward the lower layer.

7. The apparatus of claim 1, wherein a density of the first dielectric layer is greater than a density of the second dielectric layer.

8. The apparatus of claim 1, wherein the second dielectric layer and the third dielectric layer have the same material composition.

9. The apparatus of claim 1, wherein,

the upper layer includes a plurality of stacked layers, and

the plurality of stacked layers includes dielectric layers, conductive layers, or a combination thereof.

10. The apparatus of claim 1, wherein,

the first dielectric layer has a U-shape defining an open enclosure open to a top surface of the upper layer,

the second dielectric layer fills a portion of the open enclosures of the first dielectric layer, and

the third dielectric layer fills the remaining portion of the open enclosures of the first dielectric layer.

11. A method of forming a gap fill layer, the method comprising:

forming an upper layer on the lower layer;

forming a trench extending through the upper layer from a top surface of the upper layer toward the lower layer;

forming a first dielectric layer extending along an inner sidewall surface of the trench;

forming a second dielectric layer filling a portion of the trench in which the first dielectric layer is formed;

recessing a top surface of the first dielectric layer and a top surface of the second dielectric layer away from a top surface of the upper layer and toward the lower layer, the top surface of the second dielectric layer being recessed further toward the lower layer than the top surface of the first dielectric layer; and

forming a third dielectric layer covering a top surface of the first dielectric layer and a top surface of the second dielectric layer.

12. The method of claim 11, wherein forming the upper layer comprises: a dielectric layer, a conductive layer, a semiconductor layer, a sub-combination thereof, or a combination thereof is formed on the lower layer.

13. The method of claim 11, wherein,

the step of forming the first dielectric layer comprises: depositing a dielectric material in the trench having a density greater than that of the second dielectric layer, and

the first dielectric layer has a U-shape extending along an inner sidewall surface of the trench.

14. The method of claim 13, wherein,

the step of forming the second dielectric layer comprises: depositing a dielectric material in the trench and on the first dielectric layer having a density less than a density of the first dielectric layer,

the second dielectric layer fills the open enclosure defined by the first dielectric layer.

15. The method of claim 11, wherein,

recessing the first dielectric layer and the second dielectric layer comprises: performing an etching process to remove respective upper portions of the first dielectric layer and the second dielectric layer,

the top end of the recessed first dielectric layer is further from the top surface of the lower layer with respect to the recessed second dielectric layer.

16. The method of claim 11, wherein forming the second dielectric layer comprises:

depositing a dielectric material different from the dielectric material of the first dielectric layer, the deposited dielectric material filling the trench and covering the upper layer; and

a polishing process is performed to planarize the deposited dielectric material.

17. The method of claim 11, wherein forming the third dielectric layer comprises:

depositing a dielectric material that is the same material as the dielectric material of the second dielectric layer, the deposited dielectric material filling the trench and covering the upper layer;

annealing the first dielectric layer, the second dielectric layer, and the deposited dielectric material; and

a polishing process is performed to planarize the annealed dielectric material.

18. The method of claim 17, further comprising the step of:

forming a polish stop layer on the upper layer prior to forming the trench,

wherein the step of forming the third dielectric layer further comprises:

removing the polish stop layer after performing the polishing process, the planarized dielectric material protruding above the upper layer; and

the dielectric material protruding above the upper layer is polished.

19. A semiconductor device, comprising:

a peripheral region including peripheral circuitry, the peripheral circuitry comprising:

a plurality of transistors on the substrate, an

A plurality of wires electrically connected to the plurality of transistors;

a cell region on the peripheral region, the cell region including:

a semiconductor layer on the peripheral region,

an electrode stack on the semiconductor layer and overlapping the peripheral circuit in a direction perpendicular to a top surface of the semiconductor layer, the electrode stack having a stepped structure, an

A plurality of electrical vertical channels extending through the electrode stack in a direction perpendicular to a top surface of the semiconductor layer, the plurality of electrical vertical channels electrically connected to the semiconductor layer; and

a first gap filling layer surrounding a first connection plug extending sequentially through the cell region and the peripheral region and coupled to one of the plurality of wires, wherein the first gap filling layer includes:

a first dielectric layer filling a first portion of a first trench having a depth extending through the cell region and the peripheral region and proximate to the one wire, a top surface of the first dielectric layer proximate to a top surface of the electrode stack;

a second dielectric layer filling a second portion of the first trench, a top surface of the second dielectric layer being proximate to a top surface of the electrode stack, the top surface of the second dielectric layer being recessed toward the semiconductor layer more than the top surface of the first dielectric layer; and

a third dielectric layer filling the remaining portion of the first trench and covering a top surface of the second dielectric layer.

20. The semiconductor device according to claim 19,

the first dielectric layer has a U-shape defining an open enclosure open to a top surface of the electrode stack, and

the U-shape has two top ends on an inner sidewall surface of the first trench, the two top ends being farther from a top surface of the semiconductor layer with respect to the recessed second dielectric layer and being isolated from direct contact with each other.

21. The semiconductor device according to claim 20, wherein

The second dielectric layer fills a portion of the open enclosures of the first dielectric layer, and

the third dielectric layer is between the top ends of the first dielectric layer.

22. The semiconductor device according to claim 20, wherein

The second dielectric layer fills a portion of the open enclosures of the first dielectric layer, and

the third dielectric layer is between and covers the top ends of the first dielectric layers.

23. The semiconductor device according to claim 20, wherein

The first dielectric layer comprises a dielectric material having a density greater than a density of each of the second and third dielectric layers, and

the second dielectric layer and the third dielectric layer have the same material composition.

24. The semiconductor device according to claim 19, wherein

The cell area is divided into a cell array area and an extension area,

the plurality of electrical vertical channels are on the cell array region,

the step structure is on the extension region, and

the first connection plug is on the cell array region of the cell regions and extends through the electrode stack.

25. The semiconductor device according to claim 24, further comprising:

a second gap filling layer surrounding a second connection plug that sequentially extends through the cell region and the peripheral region and is coupled to an individual wire of the plurality of wires,

wherein the second connection plug is on the extension area of the cell area.

Technical Field

The present inventive concept relates to semiconductors, and more particularly, to a gap filling layer, a method of forming the same, and/or a semiconductor device manufactured by the method of forming the same.

Background

Different types of dielectric layers may be used to effectively fill trenches having relatively large widths and depths, but cracks may occur when performing the annealing process and the planarization process. The cracks may cause defects in a subsequent patterning process and may negatively affect the operation of the semiconductor device.

Disclosure of Invention

Some example embodiments of the inventive concepts provide a gap filling layer configured to prevent occurrence of cracks when a trench is filled with different types of dielectric layers, a method of forming the same, and a semiconductor device manufactured by the method of forming the same.

According to some example embodiments of the inventive concepts, an apparatus may comprise: a lower layer; an upper layer on the lower layer defining a trench extending from a top surface of the upper layer toward the lower layer; and a gap filling layer filling the trench. The gap filling layer may have a multi-layer structure. The gap filling layer may include a first dielectric layer filling a first portion of the trench, a second dielectric layer filling a second portion of the trench, and a third dielectric layer filling the remaining portion of the trench. The first dielectric layer may have a top surface proximate to a top surface of the upper layer. The second dielectric layer may have a top surface proximate to a top surface of the upper layer. The top surface of the second dielectric layer may be recessed further toward the lower layer than the top surface of the first dielectric layer. The third dielectric layer may cover a top surface of the second dielectric layer.

According to some example embodiments of the inventive concepts, a method of forming a gap filling layer may include: forming an upper layer on the lower layer; forming a trench extending through the upper layer from a top surface of the upper layer toward the lower layer; forming a first dielectric layer extending along an inner sidewall surface of the trench; forming a second dielectric layer filling a portion of the trench in which the first dielectric layer is formed; recessing a top surface of the first dielectric layer and a top surface of the second dielectric layer away from a top surface of the upper layer and toward the lower layer, the top surface of the second dielectric layer being recessed further toward the lower layer than the top surface of the first dielectric layer; and forming a third dielectric layer overlying the top surface of the first dielectric layer and the top surface of the second dielectric layer.

According to some example embodiments of the inventive concepts, a semiconductor device may include a peripheral region including a peripheral circuit including a plurality of transistors on a substrate and a plurality of wires electrically connected to the plurality of transistors. The semiconductor device may include a cell region on the peripheral region, the cell region including: a semiconductor layer on the peripheral region; an electrode stack on the semiconductor layer and overlapping the peripheral circuit in a direction perpendicular to a top surface of the semiconductor layer, the electrode stack having a stepped structure; and a plurality of electrical vertical channels extending through the electrode stack in a direction perpendicular to a top surface of the semiconductor layer, the plurality of electrical vertical channels electrically connected to the semiconductor layer. The semiconductor device may include a first gap filling layer surrounding a first connection plug sequentially extending through the cell region and the peripheral region and coupled to one of the plurality of electric lines, wherein the first gap filling layer includes a first dielectric layer filling a first portion of a first trench having a depth extending through the cell region and the peripheral region and approaching the one electric line, a second dielectric layer filling a second portion of the first trench, a top surface of the second dielectric layer being adjacent to a top surface of the electrode stack, the top surface of the second dielectric layer being recessed toward the semiconductor layer more than the top surface of the first dielectric layer, and a third dielectric layer filling a remaining portion of the first trench and covering a top surface of the second dielectric layer.

Drawings

Fig. 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H and 1I illustrate cross-sectional views showing methods of forming a gap filling layer according to some example embodiments of the inventive concepts.

Fig. 2A, 2B, 2C, and 2D illustrate cross-sectional views showing methods of forming a gap filling layer according to some example embodiments of the inventive concepts.

Fig. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I, 3J, 3K, and 3L illustrate cross-sectional views showing methods of manufacturing a semiconductor device according to some example embodiments of the inventive concepts.

Fig. 3E and 3F illustrate enlarged cross-sectional views showing a portion P1 of fig. 3D.

Fig. 4A, 4B, 4C, 4D, 4E, and 4F illustrate cross-sectional views showing methods of manufacturing a semiconductor device according to some example embodiments of the inventive concepts.

Fig. 4C and 4D illustrate enlarged cross-sectional views showing a portion P2 of fig. 4B.

Detailed Description

Now, the gap filling method and the semiconductor device manufactured thereby will be described in detail below with reference to the accompanying drawings.

Fig. 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H and 1I illustrate cross-sectional views showing methods of forming a gap filling layer according to some example embodiments of the inventive concepts.

Referring to fig. 1A, a trench 13 may be formed in an upper layer 11 on a lower layer 10 (e.g., the trench 13 may be defined by the upper layer 11 formed on the lower layer 10). For example, the upper layer 11 may be formed on the lower layer 10, and the polishing stop layer 12 may be formed on the upper layer 11. The polish stop layer 12 may be formed on the upper layer 11 before the trenches 13 are formed. The lower layer 10 may comprise any material layer. For example, the lower layer 10 may be a dielectric layer, a conductive layer, a semiconductor layer, or a semiconductor wafer. The upper layer 11 may include a dielectric layer, a conductive layer, a semiconductor layer, or a combination thereof. In some example embodiments, the upper layer 11 may include a plurality of stacked layers sequentially stacked on the lower layer 10, wherein the plurality of stacked layers include dielectric layers, conductive layers, or a combination thereof. In some example embodiments, forming the upper layer 11 may include forming a dielectric layer, a conductive layer, a semiconductor layer, a sub-combination thereof, or a combination thereof on the lower layer 10.

As used herein, an element that is "on" another element can be "above" or "below" the other element. In addition, an element "on" another element may be "directly on" the other element such that the two elements are in direct contact with each other, or the element may be "indirectly on" the other element such that the two elements are isolated from direct contact with each other by one or more intervening elements and/or spaces.

When the upper layer 11 includes a plurality of stacked dielectric layers, the dielectric layers may be of the same or different types. For example, the upper layer 11 may include silicon oxide layers and silicon nitride layers that are alternately and repeatedly stacked. The upper layer 11 may further include a semiconductor layer and a lower dielectric layer disposed under the silicon oxide layer and the silicon nitride layer. For example, a lower dielectric layer may be disposed below the semiconductor layer.

The polish stop layer 12 may include a material deposited to have a relatively large thickness (e.g., about

To about

) Silicon nitride (e.g., SiN), polysilicon, or metal nitride (e.g., TiN). The trench 13 may be etched or drilledA hole process. The trench 13 may have a depth penetrating the polish stop layer 12 and the upper layer 11 and approaching the lower layer 10. It is to be reiterated that the trench 13 may extend from the top surface 11s of the upper layer 11 towards the lower layer 10. For example, the trench 13 may have a depth sufficient to expose the lower layer 10 such that the trench 13 extends from the top surface 11s of the upper layer to the bottom surface 11b of the upper layer 11.

Referring to fig. 1B, a plurality of dielectric materials may be deposited in the trench 13 to form a first dielectric layer 14 and a second dielectric layer 15 filling the trench 13. As shown in at least fig. 1B, the first dielectric layer 14 may fill a first portion of the trench 13 (which may be an outer lower portion of the trench 13), and the second dielectric layer 15 may fill a separate second portion of the trench 13 (which may be a central portion of the trench 13). For example, as shown in fig. 1B, the first dielectric layer 14 may be formed to extend along the inner sidewall surface 13s of the trench 13, and the second dielectric layer 15 may be formed to fill a portion of the trench 13 in which the first dielectric layer 14 is formed. As further shown in at least fig. 1B, the first dielectric layer 14 may have a U-shape extending along the inner sidewall surface 13s of the trench 13.

The density and deposition rate of the first dielectric layer 14 and the second dielectric layer 15 may be different. In some embodiments, the first dielectric layer 14 may be formed by depositing a high density dielectric material and the second dielectric layer 15 may be formed by depositing a low density dielectric material. Accordingly, the density of the first dielectric layer 14 (e.g., the average density of the entire first dielectric layer 14) may be greater than the density of the second dielectric layer 15 (e.g., the average density of the entire second dielectric layer 15). For example, the first dielectric layer 14 may be formed by depositing a High Density Plasma (HDP) oxide and patterning the HDP oxide. The first dielectric layer 14 may be formed to have a shape extending along the inner surface of the trench 13. For example, the first dielectric layer 14 may have an upwardly open tubular shape or U-shape (e.g., a U-shape defining an open enclosure 14e that is open toward the top surface 11s of the upper layer 11). Forming the first dielectric layer 14 may include depositing a dielectric material in the trench 13 having a density greater than a density of the second dielectric layer 15, and forming the second dielectric layer 15 may include depositing a dielectric material in the trench 13 and on the first dielectric layer 14 having a density less than a density of the first dielectric layer 14, wherein the second dielectric layer 15 fills the open enclosure 14e defined by the first dielectric layer 14. In some example embodiments, forming the second dielectric layer 15 may include depositing a dielectric material different from the dielectric material of the first dielectric layer 14, wherein the deposited dielectric material fills the trenches 13 and covers the upper layer 11, as shown in fig. 1B.

Since the first dielectric layer 14 has a high density, voids hardly occur in the first dielectric layer 14, and thus the occurrence of cracks originating from the voids can be avoided or significantly reduced when an annealing process is subsequently performed. The second dielectric layer 15 may include Tetraethylorthosilicate (TEOS) oxide deposited to have a thickness sufficient to cover the polish stop layer 12 and fill the trenches 13 formed with the first dielectric layer 14. The second dielectric layer 15 may be formed at a deposition rate higher than that of the first dielectric layer 14. Since the second dielectric layer 15 is deposited at a high rate, the trench 13 can be filled relatively quickly with the second dielectric layer 15.

Referring to fig. 1C, the second dielectric layer 15 may be partially removed so that the second dielectric layer 15 may remain on the trench 13. For example, the second dielectric layer 15 may undergo an open process in which a photolithography process and an etching process are performed to limit or open a certain position such as a cell memory region of the semiconductor device. Thus, the second dielectric layer 15 may be partially or completely removed on the polish stop layer 12 and may remain on the trench 13. Performing an open process may be optional, but not necessary.

Referring to fig. 1D, a planarization process may be performed on the second dielectric layer 15. For example, a Chemical Mechanical Polishing (CMP) process may be performed to planarize the second dielectric layer 15. The CMP process may continue until the polish stop layer 12 is revealed. After the second dielectric layer 15 is formed as shown in fig. 1B, a CMP process may be performed without performing the open process of fig. 1C. In this case, since the polishing stop layer 12 has a relatively flat surface or even if the polishing stop layer 12 has a non-flat surface, the degree of non-flatness is not heavy, the CMP process can be easily performed. Thus, in some example embodiments (including at least the example embodiments shown in fig. 1C-1D), the forming of the second dielectric layer 15 may include performing a polishing process to planarize the deposited dielectric material of the second dielectric layer 15.

Alternatively, after performing the open process of fig. 1C, a CMP process may be performed. In this case, since the etching amount of the second dielectric layer 15 becomes small, the etching load can be reduced. The top surface 15s of the second dielectric layer 15 may be concave due to sagging caused by the CMP process. Alternatively, the top surface 15s of the second dielectric layer 15 may be flat.

When an annealing process is subsequently performed after the CMP process, the top ends of the first and second dielectric layers 14 and 15 may be at different levels due to a difference in shrinkage rate between the first and second dielectric layers 14 and 15, wherein the "level" may be understood to mean a height with respect to the lower layer 10 and/or the top surface 10s of the lower layer 10. In addition, when voids occur when the first dielectric layer 14 and the second dielectric layer 15 discussed above with reference to fig. 1B are formed, the voids may serve as crack sources. In certain embodiments, the annealing process may not be performed after the CMP process, and instead, the processes discussed below with reference to fig. 1E may be performed to avoid or significantly reduce the occurrence of cracks.

Referring to fig. 1E, an etching process may be performed to partially remove the first dielectric layer 14 and the second dielectric layer 15. A wet etching process may be performed as the etching process. The partial removal may recess the first dielectric layer 14 and the second dielectric layer 15. In some embodiments, the first dielectric layer 14 and the second dielectric layer 15 may be etched to be insufficient to protrude beyond the upper layer 11. Thus, the top surface 14s of the recessed first dielectric layer 14 may be located at the same or similar level as the top surface 11s of the upper layer 11. It is to be reiterated that as shown in at least fig. 1E, the top surface 14s of the first dielectric layer 14 (which may include the top surface of each of the at least two top ends 14t of the first dielectric layer 14) may be at a level above the top surface 10s of the lower layer 10 that is equal to or less than the level of the top surface 11s of the upper layer 11. It will be understood that the top surface of each apex 14t may at least partially comprise the top surface 14s of the first dielectric layer 14. As a result, it will be understood with respect to at least fig. 1E that the etching process may include recessing the top surface 14s of the first dielectric layer 14 and the top surface 15s of the second dielectric layer 15 away from the top surface 11s of the upper layer 11 and toward the lower layer 10, the top surface 15s of the second dielectric layer being recessed further toward the lower layer 10 than the top surface 14s of the first dielectric layer 14.

The etching amount of the low-density second dielectric layer 15 may be greater than that of the high-density first dielectric layer 14. Due to this difference in etching amount, the top surface 15s of the recessed second dielectric layer 15 may be located at a lower level than the top surface 14s of the recessed first dielectric layer 14. Since the top surface 15s of the second dielectric layer 15 is located at a lower level than the top surface 14s of the first dielectric layer 14, the first dielectric layer 14 may have two separate top ends 14t protruding above the top surface 15s of the second dielectric layer 15. The top end 14t of the first dielectric layer 14 may be located at the same or similar level as the top surface 11s of the upper layer 11. Thus, as shown in at least fig. 1E, the first dielectric layer 14 may fill a first portion of the trench 13 and may have a top surface 14s proximate to the top surface 11s of the upper layer 11, while the second dielectric layer 15 may fill a separate second portion of the trench 13 and may have a top surface 15s proximate to the top surface 11s of the upper layer 11, and the top surface 15s of the second dielectric layer 15 may be recessed more toward the lower layer 10 than the top surface 14s of the first dielectric layer 14. As further shown in at least fig. 1E, the first dielectric layer 14 may have a U-shape such that the first dielectric layer 14 includes at least two top ends 14t, each on a separate respective inner sidewall surface 13s of the trench 13 and each adjacent to the top surface 11s of the upper layer 11.

As shown in at least fig. 1E, recessing first dielectric layer 14 and second dielectric layer 15 may include performing an etch process to remove respective upper portions 14x and 15x of first dielectric layer 14 and second dielectric layer 15, wherein recessed first dielectric layer 14 has a top end 14t that protrudes above a top surface 15s of recessed second dielectric layer 15 (e.g., with respect to top surface 15s of recessed second dielectric layer 15, top end 14t of recessed first dielectric layer 14 is farther from top surface 10s of lower layer 10, as shown in fig. 1E). As further shown in at least fig. 1E, the individual tips 14t of the first dielectric layer 14 may be isolated from direct contact with each other across the open enclosure 14E.

Referring to fig. 1F, a third dielectric layer 16 may be formed on the lower layer 10, and an annealing process may be performed. The third dielectric layer 16 may be formed by depositing the same or similar dielectric material as the second dielectric layer 15, e.g., Tetraethylorthosilicate (TEOS) oxide. Thus, in some example embodiments, the second dielectric layer 15 and the third dielectric layer 16 may have the same or substantially the same material composition (e.g., the same material composition within manufacturing tolerances and/or material tolerances), and forming the third dielectric layer 16 may include: depositing a dielectric material which is the same material as that of the second dielectric layer 15, the deposited dielectric material filling the trench 13 and covering the upper layer 11; and annealing the first dielectric layer, the second dielectric layer and the deposited dielectric material.

The third dielectric layer 16 may be formed to have a thickness sufficient to fill the trench 13 formed with the first and second dielectric layers 14 and 15 and cover the polishing stop layer 12. An annealing process may be performed after forming the third dielectric layer 16.

As discussed above with reference to fig. 1E, the etching process may cause the first dielectric layer 14 to have a protruding tip 14 t. The phrase "the first dielectric layer 14 may have a protruding tip 14 t" may mean that the etching process of fig. 1E may remove the tip interface formed between the first dielectric layer 14 and the second dielectric layer 15 and adjacent to the top surface 11s of the upper layer 11. When the first dielectric layer 14 does not have a protruding tip 14t and the third dielectric layer 16 is not formed, the annealing process may create a difference in shrinkage between the first dielectric layer 14 and the second dielectric layer 15, and the difference in shrinkage may cause the first dielectric layer 14 and the second dielectric layer 15 to separate from each other to create a breach at the tip interface from which a void may propagate. Accordingly, since the etching process of fig. 1E removes the tip interface that can serve as a crack source and forms the third dielectric layer 16 to cover the first dielectric layer 14 and the second dielectric layer 15, the occurrence of cracks may be suppressed in the trench 13.

Referring to fig. 1G, a planarization process may be performed on the third dielectric layer 16. For example, a Chemical Mechanical Polishing (CMP) process may be performed to planarize the third dielectric layer 16. Accordingly, forming the third dielectric layer 16 may include performing a polishing process to planarize the annealed dielectric material. The CMP process may continue until the polish stop layer 12 is revealed. The third dielectric layer 16 may have a top surface 16s that is concave due to a depression caused by the CMP process. Alternatively, the top surface 16s of the third dielectric layer 16 may be flat. As shown in at least fig. 1G, the second dielectric layer 15 and the third dielectric layer 16 may have an interface 19 therebetween defined by direct contact between a top surface 15s of the second dielectric layer 15 and a bottom surface 16b of the third dielectric layer 16 that is concave toward the lower layer 10.

Referring to fig. 1H, the polish stop layer 12 may be selectively removed. Therefore, the gap filling layer 17 may be formed to fill the trench 13 and cracks are unlikely to occur. The gap filling layer 17 may have a multi-layer structure including a first dielectric layer 14, a second dielectric layer 15, and a third dielectric layer 16. The third dielectric layer 16 may cover the first and second dielectric layers 14 and 15 and may protrude above the top surface 11s of the upper layer 11. As shown in fig. 1H, forming the third dielectric layer 16 may include removing the polish stop layer 12 after performing the polishing process such that the planarized dielectric material of the third dielectric layer protrudes above the upper layer 11.

Optionally, as shown in fig. 1I, a buffer chemical mechanical polishing process may be further performed to remove the third dielectric layer 16 protruding above the top surface 11s of the upper layer 11. Thus, as shown in fig. 1I, the formation of the third dielectric layer 16 may include polishing the dielectric material of the third dielectric layer 16 that protrudes above the upper layer 11. The gap filling layer 17 may have a shape in which the second dielectric layer 15 and the third dielectric layer 16 are sequentially stacked within the first dielectric layer 14 shaped like a tube or U. The top surface 14s of the first dielectric layer 14 may be exposed at the top surface 11s of the upper layer 11. For example, the top surface 14s of the first dielectric layer 14 may be located at the same or similar level as the top surface 11s of the upper layer 11. Thus, as shown in at least fig. 1I, while the first dielectric layer 14 may fill a first portion of the trench 13 and the second dielectric layer 15 may fill a separate second portion of the trench 13, the third dielectric layer 16 may fill a remaining portion of the trench 13, which is the entire portion of the trench 13 not filled by the first and second dielectric layers 14, 15, and the third dielectric layer 16 may cover the top surface 15s of the second dielectric layer 15. In some example embodiments (including the example embodiment shown in fig. 1I), each of the two top ends 14t of the first dielectric layer 14 is exposed at the top surface 11s of the upper layer 11.

In some example embodiments (including at least the example embodiment shown in fig. 1I), the first dielectric layer 14 has a U-shape defining an open enclosure 14e open toward the top surface 11s of the upper layer 11, the second dielectric layer 15 fills a portion 14I1 of the open enclosure 14e of the first dielectric layer 14, and the third dielectric layer 16 fills a remaining portion 14I2 of the open enclosure 14e of the first dielectric layer 14, including the third dielectric layer 16 being located between the top ends 14t of the first dielectric layer 14.

Fig. 2A, 2B, 2C, and 2D illustrate cross-sectional views showing methods of forming a gap filling layer according to some example embodiments of the inventive concepts.

Referring to fig. 2A, the same or similar process as discussed above with reference to fig. 1A through 1E may be performed to form a trench 13 in the upper layer 11 on the lower layer 10, form a first dielectric layer 14 and a second dielectric layer 15 in the trench 13, and then planarize the second dielectric layer 15. Thereafter, an etching process may be performed to recess the first dielectric layer 14 and the second dielectric layer 15. In some embodiments, the first dielectric layer 14 and the second dielectric layer 15 may be recessed to a level below the top surface 11s of the upper layer 11. Accordingly, the top surface 14s of the recessed first dielectric layer 14 may be located at a lower level than the top surface 11s of the upper layer 11. The top surface 15s of the recessed second dielectric layer 15 may be located at a lower level than the top surface 14s of the first dielectric layer 14. The top end 14t of the first dielectric layer 14 may be located at a level not close to the level of the top surface 11s of the upper layer 11. For example, the top surface 14s of the first dielectric layer 14 may be located at a lower level than the top surface 11s of the upper layer 11.

Referring to fig. 2B, as discussed above with reference to fig. 1F, the third dielectric layer 16 may be formed to have a thickness sufficient to fill the trench 13 and cover the polish stop layer 12, and then an annealing process may be performed. The etching process of fig. 2A may remove the top interface between the first dielectric layer 14 and the second dielectric layer 15, and the third dielectric layer 16 may cover the first dielectric layer 14 and the second dielectric layer 15, with the result that the occurrence of cracks in the trench 13 may be suppressed.

Referring to fig. 2C, the same or similar processes as those discussed above with reference to fig. 1G and 1H may be performed to planarize the third dielectric layer 16 and remove the polish stop layer 12, which may form a gap filling layer 17 having a multi-layer structure including the first, second, and third dielectric layers 14, 15, and 16. Optionally, as shown in fig. 2D, a buffer chemical mechanical polishing process may be further performed. In this case, the gap filling layer 17 may have a shape such that: a third dielectric layer 16 covers the tubular or U-shaped first dielectric layer 14, the first dielectric layer 14 filling the trench 13 and surrounding the second dielectric layer 15. As shown in fig. 2D, the third dielectric layer 16 may further cover the top end 14t of the first dielectric layer 14. Thus, in some example embodiments (including the example embodiment shown in fig. 2D), the third dielectric layer 16 may be formed to cover the top surface 14s of the first dielectric layer 14 and the top surface 15s of the second dielectric layer 15 in addition to being located between the top ends 14t of the first dielectric layer 14.

Fig. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I, 3J, 3K, and 3L illustrate cross-sectional views showing methods of manufacturing a semiconductor device according to some example embodiments of the inventive concepts. Fig. 3E and 3F illustrate enlarged cross-sectional views showing a portion P1 of fig. 3D.

Referring to fig. 3A, a substrate 90 may be provided thereon with a peripheral region PR including a peripheral circuit 94. Peripheral circuitry 94 may include a plurality of transistors 93 formed on substrate 90, a plurality of metal lines 97 electrically connected to plurality of transistors 93, and a plurality of metal contacts 95 between transistors 93 and metal lines 97 and between metal lines 97 themselves. The substrate 90 may be a semiconductor substrate such as a monocrystalline silicon wafer. The peripheral region PR may also include a lower dielectric layer 92 overlying the substrate 90 and peripheral circuitry 94.

Referring to fig. 3B, a semiconductor layer 100 may be formed on the peripheral region PR, and a mold 101 having a stepped structure 300 may be formed on the semiconductor layer 100. The semiconductor layer 100 may include a polysilicon layer. The semiconductor layer 100 may be divided into a cell array region CAR and an extension region EXT. The cell array region CAR and the extension region EXT may constitute a cell region CR disposed on the peripheral region PR. The stepped structure 300 may be formed by repeatedly performing an etching process on a portion of the molding 101 and also performing a trimming process on an etching mask. The stepped structure 300 may be formed on the extension area EXT.

The molding 101 may be formed by alternately and repeatedly stacking a plurality of molding sacrificial layers 110 and a plurality of molding dielectric layers 120 on the semiconductor layer 100. A dielectric buffer layer 105 may be further formed between the semiconductor layer 100 and the lowermost molding sacrificial layer 110. The molding sacrificial layer 110 and the molding dielectric layer 120 may be formed of dielectric materials having etch selectivity with respect to each other. The dielectric buffer layer 105 may be formed of the same or similar dielectric material as the molding dielectric layer 120. For example, the mold sacrificial layer 110 may include silicon nitride, and the mold dielectric layer 120 and the dielectric buffer layer 105 may include silicon oxide.

Referring to fig. 3C, one or more trenches 140 may be formed on the cell array region CAR. As shown in at least fig. 3C, the trench 140 (also referred to herein as a "first trench") may have a depth that penetrates the cell region CR and the peripheral region PR and approaches one of the metal lines 97. For example, a planarized dielectric layer 301 covering the stepped structure 300 may be formed on the semiconductor layer 100, and an etching process may be performed on the cell array region CAR. An etching process may be performed such that the mold 101, the semiconductor layer 100, and the lower dielectric layer 92 may be etched to form a trench 140 of the metal line 97 near the peripheral region PR. For example, each trench 140 may have a depth near the uppermost metal line 97.

Referring to fig. 3D, a gap filling layer 145 may be formed to fill the trench 140. The gap fill layer 145 may be formed by the gap fill layer forming methods discussed above with reference to fig. 1A-1I or fig. 2A-2D. The description of fig. 1A-1I or fig. 2A-2D may be incorporated into the description of fig. 3D.

For example, as shown in fig. 3E, each gap filling layer 145 may include a first dielectric layer 145a, a second dielectric layer 145b, and a third dielectric layer 145c disposed in the trench 140, the trench 140 penetrating the molding 101, the semiconductor layer 100, and the lower dielectric layer 92 and exposing the metal line 97. The first, second, and third dielectric layers 145a, 145b, and 145c may correspond to the first, second, and third dielectric layers 14, 15, and 16, respectively, of fig. 1I, and the molding 101 may correspond to the upper layer 11 of fig. 1I, and the semiconductor layer 100 may correspond to the lower layer 10 of fig. 1I. As shown in fig. 3E and 3F, the first dielectric layer 145a may fill a first portion of the trench 140, the top surface 145as of the first dielectric layer 145a is adjacent to the top surface 101s of the molding 101, the second dielectric layer 145b may fill a second portion of the trench 140, the top surface 145bs of the second dielectric layer 145b is adjacent to the top surface 101s of the molding 101, the top surface 145bs of the second dielectric layer 145b is recessed toward the semiconductor layer 100 more than the top surface 145as of the first dielectric layer 145a, and the third dielectric layer 145c may fill a remaining portion of the trench 140 and may cover the top surface 145bs of the second dielectric layer 145 b.

The gap filling layer 145 may have a shape in which a second dielectric layer 145b and a third dielectric layer 145c are sequentially stacked within a first dielectric layer 145a shaped like a tube or U (see also fig. 1I). The top surface 145as of the first dielectric layer 145a may be exposed. Alternatively, as shown in fig. 3F, each gap filling layer 145 may have a shape in which a third dielectric layer 145c covers a tube-shaped or U-shaped first dielectric layer 145a (the first dielectric layer 145a surrounds the second dielectric layer 145b) (see also fig. 2D).

Referring to fig. 3G, a plurality of vertical channel holes 150 and a plurality of dummy channel holes 250 may be formed to penetrate the molding 101. For example, the mold 101 may be subjected to an etching process to form the vertical channel hole 150 on the cell array region CAR and the dummy channel hole 250 on the extension region EXT. The vertical channel hole 150 and the dummy channel hole 250 may expose the semiconductor layer 100. One or more vertical channel holes 150 may be disposed between adjacent gap fill layers 145. The dummy channel hole 250 may penetrate the planarized dielectric layer 301 and the stepped structure 300 of the molding 101.

Referring to fig. 3H, an electrical vertical channel 350 may be formed in the vertical channel hole 150 on the cell array region CAR, and a dummy vertical channel 450 may be formed in the dummy channel hole 250 on the extension region EXT. Accordingly, the electrical vertical channels 350 may be on the cell array region CAR, and the dummy vertical channels 450 may be on the extension region EXT. Each electrical vertical channel 350 may include a channel layer 352 and a memory layer 354 surrounding channel layer 352. Memory layer 354 may include one or more dielectric layers. For example, memory layer 354 may include a tunnel dielectric layer surrounding channel layer 352, a blocking dielectric layer distal from memory layer 354, and a charge storage layer interposed between the tunnel dielectric layer and the blocking dielectric layer. Channel layer 352 may include polysilicon. The channel layer 352 may have a block shape or a hollow tube shape. When the channel layer 352 has a hollow tube shape, the dielectric layer may fill the hollow interior of the channel layer 352.

A pad 356 may be formed on top of each electrical vertical channel 350. The pad 356 may be a conductor or a doped region. For example, the semiconductor layer 100 and the pad 356 may have opposite conductivity types. The dummy vertical channel 450 may have the same structure as the electrical vertical channel 350. The electrical vertical channel 350 may be electrically connected to the semiconductor layer 100, and the dummy vertical channel 450 may not be electrically connected to the semiconductor layer 100. The dummy vertical channel 450 may serve as a support to suppress defects such as collapse of the stair-step structure 300 of the molding 101.

Referring to fig. 3I, molded wings 103 may be formed, wherein spaces 115 are provided between molded dielectric layers 120. For example, the molding sacrificial layer 110 may be removed by an etching process using an etchant capable of selectively etching the molding sacrificial layer 110, which may form spaces 115 between the molding dielectric layers 120. When the molding sacrificial layer 110 includes silicon nitride, it may be formed by including, for example, phosphoric acid (H)₃PO₄) To selectively remove the molding sacrificial layer 110. There may be cavities or spaces 115 between the molding dielectric layers 120, and accordingly, the stepped structure 300 of the molding wings 103 may have weak points such as sagging or collapse. However, since the dummy vertical channel 450 is used to support the stair-step structure 300, this weakness may be addressed.

Referring to fig. 3J, electrodes 400 may be disposed between the molding dielectric layers 120 to form an electrode stack 155 that is on the semiconductor layer 100 and overlaps the peripheral circuit 94 in a direction perpendicular to the top surface 100s of the semiconductor layer 100. As further shown in at least fig. 3J, electrode stack 155 has a stepped structure 300. For example, a conductive material may be deposited to form electrode 400 that fills space 115. The electrode 400 may include polysilicon or metal. For example, the electrode 400 may comprise tungsten. When a process is performed to fill the space 115 with the electrode 400, the dummy vertical channel 450 may support the stair structure 300, and as a result, the electrode stack 155 may have stable structural stability.

As shown in at least fig. 3J, the top surface 155s of the electrode stack 155 can be the same as the top surface 101s of the molding 101. Thus, as shown in at least fig. 3J, the first dielectric layer 145a may fill a first portion of the trench 140, the top surface 145as of the first dielectric layer 145a is proximate to the top surface 155s of the electrode stack 155, the second dielectric layer 145b may fill a second portion of the trench 140, the top surface 145bs of the second dielectric layer 145b is proximate to the top surface 155s of the electrode stack 155, the top surface 145bs of the second dielectric layer 145b is recessed more toward the semiconductor layer 100 than the top surface 145as of the first dielectric layer 145a, and the third dielectric layer 145c may fill a remaining portion of the trench 140 and may cover the top surface 145bs of the second dielectric layer 145 b.

The electrode 400 may constitute a ground select line, a word line, and a string select line. Each electrode 400 may include a pad 405 or an end portion disposed on the extension area EXT. The pads 405 at the respective ends of the electrode 400 may form the stepped structure 300 on the extended area EXT and may be supported by the dummy vertical channel 450.

Referring to fig. 3K, a connection plug 500 may be formed to be connected with the metal line 97. The length of the connection plug 500 may penetrate through the gap filling layer 145 and approach the metal line 97. The gap filling layer 145 may electrically separate the connection plug 500 from the electrode 400. The connection plug 500 may be electrically connected to the peripheral circuit 94 of the peripheral region PR through a metal line 97. For example, as shown in at least fig. 3K, the first gap filling layer 145 may surround the first connection plugs 500, the first connection plugs 500 sequentially extending through the cell region CR and the peripheral region PR and being coupled to one metal line 97 ("wire") of the plurality of metal lines 97. As shown in at least fig. 3K, the first connection plug 500 may be on the cell array region CAR and may extend through ("penetrate") the electrode stack 155. On the cell array region CAR, one or more electrical vertical channels 350 may be disposed between adjacent connection plugs 500. Thus, as shown in at least fig. 3K, each "first" connecting plug 500 may be interposed between a separate pair of adjacent electrical vertical channels 350. As shown in at least fig. 3K, electrical vertical channel 350 can extend through electrode stack 155 in a direction perpendicular to top surface 100s of semiconductor layer 100 and electrically connect to semiconductor layer 100.

Referring to fig. 3L, bit lines 630 and connection lines 640 may be formed on the cell array region CAR, and metal lines 650 may be formed on the extension region EXT. For example, a dielectric material may be deposited to form an interlayer dielectric layer 303 covering electrode stack 155 and planarized dielectric layer 301. On the cell array region CAR, a bit line contact 530 may be formed to penetrate the interlayer dielectric layer 303 and be coupled with the pad 356 of the electric vertical channel 350, and a connection contact 540 may be formed to be coupled with the connection plug 500. On the extension region EXT, a metal contact 550 may be formed to penetrate the interlayer dielectric layer 303 and the planarized dielectric layer 301 and to be coupled with the pad 405 of the electrode 400. Metal contact 550 may further penetrate through molded dielectric layer 120 on pad 405 of electrode 400. Thus, the metal contacts 550 may be coupled to separate respective pads 405 of the electrode 400.

A conductive material may be deposited on the interlayer dielectric layer 303 and patterned to form bit lines 630, connection lines 640, and metal lines 650. The bit line 630 may be electrically connected to the electrical vertical channel 350 through a bit line contact 530. The connection lines 640 (also referred to herein as "first connection lines") may be electrically connected to the respective connection plugs 500 through the connection contacts 540. The metal lines 650 may be electrically connected to the individual respective pads 405 of the electrode 400 through individual respective metal contacts 550.

Through the above process, the semiconductor device 1 can be manufactured. The semiconductor device 1 may be a three-dimensional vertical NAND flash memory device having a cell-on-peripheral (cell-on-peripheral) structure in which the cell regions CR are stacked on the peripheral region PR.

Although at least fig. 3L illustrates an example embodiment of a semiconductor device including a plurality of "first" connection plugs 500, it will be understood that in some example embodiments, the semiconductor device may include only a single, individual first connection plug 500.

Fig. 4A, 4B, 4C, 4D, 4E, and 4F illustrate cross-sectional views showing methods of manufacturing a semiconductor device according to some example embodiments of the inventive concepts. Fig. 4C and 4D illustrate enlarged cross-sectional views showing a portion P2 of fig. 4B.

Referring to fig. 4A, the same or similar process as that discussed above with reference to fig. 3A to 3C may be performed to form the semiconductor layer 100 on the peripheral region PR and to form the molding 101 having the stepped structure 300 on the semiconductor layer 100. A planarized dielectric layer 301 covering the stepped structure 300 may be formed on the semiconductor layer 100, one or more trenches 140 may be formed on the cell array region CAR, and additional trenches 142 may be formed on the extension region EXT. The additional grooves 142 may be provided in plurality. The additional trench 142 may have a depth that penetrates the planarized dielectric layer 301, the semiconductor layer 100 and the lower dielectric layer 92 and approaches the uppermost metal line 97 of the peripheral region PR. The additional trenches 142 may be formed simultaneously with the trenches 140.

Referring to fig. 4B, a gap filling layer 145 may be formed to fill the trench 140, and an additional gap filling layer 147 (also referred to herein as "second gap filling layer") may be formed to fill the additional trench 142. A gap filling layer 145 (also referred to herein as a "first gap filling layer") may be disposed on the cell array region CAR, and an additional gap filling layer 147 may be disposed on the extension region EXT. The gap fill layer 145 and the additional ("second") gap fill layer 147 can be formed by the gap fill layer formation methods discussed above with reference to fig. 1A-1I or fig. 2A-2D. The description of fig. 1A-1I or fig. 2A-2D may be incorporated into the description of fig. 4B.

Each gap filling layer 145 may have the shape shown in fig. 3E or 3F. As shown in fig. 4C, the additional gap-fill layer 147 may include a first dielectric layer 147a, a second dielectric layer 147b, and a third dielectric layer 147C disposed in an additional trench 142 (also referred to herein as a "second trench" with respect to the trench 140), the additional trench 142 penetrating the planarized dielectric layer 301, the semiconductor layer 100, and the lower dielectric layer 92 and exposing the metal line 97. The first dielectric layer 147a, the second dielectric layer 147b, and the third dielectric layer 147c may correspond to the first dielectric layer 14, the second dielectric layer 15, and the third dielectric layer 16 of fig. 1I, respectively. In some example embodiments, with respect to the first, second, and third dielectric layers 145a, 145b, and 145c, the first, second, and third dielectric layers 147a, 147b, and 147c may be referred to herein as fourth, fifth, and sixth dielectric layers, respectively. Accordingly, in some example embodiments, the additional gap filling layer 147 may include: a fourth dielectric layer 147a filling a first portion of the second trench 142, the second trench 142 having a depth extending through the cell region CR and the peripheral region PR and approaching the individual metal line 97, a top surface of the fourth dielectric layer 147a approaching a top surface 301s of the dielectric layer 301; a fifth dielectric layer 147b filling a second portion of the second trench 142, a top surface of the fifth dielectric layer 147b being adjacent to the top surface 301s of the dielectric layer 301, the top surface of the fifth dielectric layer 147b being recessed more toward the semiconductor layer 100 than the top surface of the fourth dielectric layer 147 a; and a sixth dielectric layer 147c filling the remaining portion of the second trench 142 and covering the top surface of the fifth dielectric layer 147 b.

The additional gap filling layer 147 may have a shape in which a second dielectric layer 147b and a third dielectric layer 147c are sequentially stacked within a first dielectric layer 147a shaped like a tube or U (see also fig. 1I). The top surface 147as of the first dielectric layer 147a may be exposed. Alternatively, as shown in fig. 4D, the additional gap filling layer 147 may have a shape of: the third dielectric layer 147c covers the tubular or U-shaped first dielectric layer 147a surrounding the second dielectric layer 147b (see also fig. 2D).

Referring to fig. 4E, the same or similar process as discussed above with reference to fig. 3G through 3K may be performed to replace the molded sacrificial layer 110 with the electrode 400 to form the electrode stack 155. The electrical vertical channels 350 and the connection plugs 500 may be formed on the cell array region CAR, and the dummy vertical channels 450 and the additional connection plugs 502 may be formed on the extension region EXT.

The electrical vertical channel 350 may penetrate the electrode stack 155 and be electrically connected with the semiconductor layer 100, and the connection plug 500 may penetrate the gap filling layer 145 and be electrically connected with the metal line 97 of the peripheral region PR. The dummy vertical channel 450 may penetrate the stair-step structure 300 of the electrode stack 155 and is not electrically connected with the semiconductor layer 100. The additional connection plug 502 may penetrate the additional gap filling layer 147 and be electrically connected with the metal line 97 of the peripheral region PR.

Referring to fig. 4F, the same or similar process as that discussed above with reference to fig. 3L may be performed to form a bit line 630 electrically connected to the electrical vertical channel 350, form a connection line 640 electrically connected to the connection plug 500, and form an additional connection line 642 electrically connected to the additional connection plug 502. Through the process discussed above, the semiconductor device 1 may include an additional connection plug 502 (also referred to herein as a "second connection plug") in addition to the connection plug 500 (also referred to herein as a "first connection plug"). For example, as shown in at least fig. 4F, the second gap filling layer 147 may surround the second connection plugs 502, the second connection plugs 502 sequentially extending through the cell region CR and the peripheral region PR, and coupled to individual metal lines 97 ("wires") of the plurality of metal lines 97 with respect to one metal line 97 described with respect to the first gap filling layer 145 and the first connection plug 500 as shown in at least fig. 3K. As shown in at least fig. 4F, the second connecting plug 500 may be on the extension area EXT.

According to the inventive concept, different types of dielectric layers may be deposited in the trench, and an etching process may be performed to recess the dielectric layers, with the result that there may be no interface between the dielectric layers that serves as a crack source. In conclusion, a gap filling layer free from cracks can be obtained.

The advantages of the inventive concept compared to the prior art will be apparent from the appended claims and the description discussed with reference to the figures. The inventive concept is clearly claimed and particularly pointed out in the claims. The inventive concept, however, may best be understood by reference to the following description taken in conjunction with the accompanying drawings. In the description, like reference numerals refer to like elements throughout the drawings.

This detailed description of the inventive concept should not be construed to be limited to the example embodiments set forth herein, but is intended to cover various combinations, modifications, and variations of the inventive concept without departing from the spirit and scope of the inventive concept. The appended claims should be construed to include other example embodiments.