阅读说明：本技术 一种时钟频率检测电路 (Clock frequency detection circuit ) 是由 吴延科 舒海军 赵贵勇 孟得光 于 2019-11-11 设计创作，主要内容包括：本发明公开了一种时钟频率检测电路。首先,待测时钟通过分频单元1,分频后经过同步单元同步到高频单元分频后的时钟域；其次,经过上升沿产生单元得到脉冲信号；然后,将高频时钟单元产生的高频时钟经过分频单元2得到标尺时钟,经过标尺计数单元计数,储存到计数值存储单元；最后计数值单元存储的标尺计数值分别与期望值对比,分别将结果输出。利用本发明,解决模拟电路检测时钟电路复杂,可配置性低、不灵活的缺点。(The invention discloses a clock frequency detection circuit. Firstly, a clock to be tested passes through a frequency division unit 1, and is synchronized to a clock domain subjected to frequency division by a high-frequency unit through a synchronization unit after frequency division; secondly, obtaining a pulse signal through a rising edge generating unit; then, the high-frequency clock generated by the high-frequency clock unit passes through the frequency division unit 2 to obtain a scale clock, and the scale clock is counted by the scale counting unit and stored in the counting value storage unit; and finally, comparing the scale count values stored in the count value unit with expected values respectively, and outputting the results respectively. The invention solves the defects of complex detection clock circuit, low configurability and inflexibility of the analog circuit.)

1. A clock frequency detection circuit, the clock to be measured is through 1 frequency division unit to synchronous unit rise edge effect scale clock unit and count value memory cell through rising edge production unit production, high frequency reference clock exports scale clock count unit to count value memory cell again through frequency division unit 2, count value memory cell to contrast unit and frequency upper limit settlement unit and frequency lower limit settlement unit contrast, its characterized in that mainly includes: a frequency dividing unit 1, a synchronizing unit, a rising edge pulse generating unit, a frequency dividing unit 2, a scale clock counting unit, a count value storage unit, a frequency upper limit setting unit, a frequency lower limit setting unit and a comparing unit; wherein:

frequency dividing unit 1: the frequency division processing module is used for carrying out frequency division processing on the clock to be detected;

a synchronization unit: the clock synchronization device is connected with the frequency division unit 1 and used for synchronizing the clock to be tested after frequency division by the frequency division unit 1 into a scale clock domain;

rising edge pulse generating unit: the synchronous unit is connected with the scale clock counting unit and the counting value storage unit and is used for generating rising edge pulse signals and outputting the rising edge pulse signals to the scale clock counting unit and the counting value storage unit;

frequency dividing unit 2: the scale clock signal is generated by dividing the frequency of the high-frequency reference clock signal;

scale clock counting unit: the frequency dividing unit 2 is connected with the clock signal generator and is used for counting the clock to be measured according to the scale clock;

count value storage means: the scale clock counting unit is connected with the scale clock counting unit and is used for storing the count value generated by the scale clock to the clock counting unit to be measured;

the frequency upper limit setting unit is used for storing a high-frequency clock upper limit expected count value of the clock to be measured according to the scale clock;

the lower frequency limit setting unit is used for storing a lower frequency clock lower limit expected count value of the clock to be measured according to the scale clock;

and a comparison unit for comparing the count value generated by the scale clock with the expected value in the upper frequency limit expectation unit, and comparing the count value generated by the scale clock with the expected value in the lower frequency limit expectation unit.

2. The clock frequency detection circuit according to claim 1, wherein the frequency division unit 1 divides the clock to be measured so as to improve accuracy, and can configure the division coefficient as required so as to better match the scale clock.

3. The clock frequency detection circuit according to claim 2, wherein the synchronization unit divides the frequency of the clock to be detected and synchronizes the divided frequency of the clock to be detected to the scale clock domain through the synchronization unit, and the divided frequency of the clock to be detected passes through the first stage register, the second stage register and the third stage register and is removed by the scale clock.

4. The clock frequency detection circuit of claim 3, wherein the rising edge pulse generating unit generates the rising edge pulse signal when the output value of the second stage register is high and the output value of the third stage register is low by using the second stage register and the third stage register of the synchronization unit.

5. The clock frequency detection circuit according to claim 4, wherein the frequency division unit 2 divides the frequency by the high-frequency reference clock signal via the frequency division unit 2 to generate the scale clock for detection.

6. The clock frequency detection circuit according to claim 6, wherein the scale clock counting unit generates the scale clock by the frequency dividing unit 2 to count the divided clock to be measured.

7. The clock frequency detection circuit according to claim 7, wherein the count value storage unit stores the scale clock count value generated by the scale clock count unit in a count value register.

8. The clock frequency detection circuit according to claim 1, wherein the frequency upper limit setting unit configures an upper limit count value desired for clock frequency detection for comparing whether the detection frequency exceeds an upper limit range.

9. The clock frequency detection circuit according to claim 1, wherein the frequency lower limit setting unit configures a clock frequency detection desired lower limit count value for comparing whether the detection frequency exceeds a lower limit range.

10. The clock frequency detection circuit according to claim 1, wherein the comparison unit compares the count value of the count storage unit with an upper frequency limit expected value to obtain a low frequency detection result, and compares the count value with a lower frequency limit low frequency expected value to obtain a high frequency detection result.

Technical Field

The invention relates to the technical field of chip detection, monitoring and self-regulation, in particular to a clock frequency detection circuit.

Background

In the communication system neighborhood, a clock is an important component of the whole system, the whole system works under the driving of the clock, the problem of the clock frequency can cause the whole system to be incapable of working, and the safety and the stability of the system can be influenced. Real-time detection of the clock frequency is particularly important.

At present, a clock frequency detection design is mainly realized by an analog circuit, a monostable trigger circuit is used for realizing frequency detection, the high frequency or the low frequency of an external clock is subjected to frequency detection, and a simple analog circuit is complex in frequency detection, greatly influenced by a process, low in configurability, inflexible and poor in universality.

The clock frequency detection circuit provided by the invention has the advantages of simple structure, no process influence, strong configurability, high flexibility and strong universality.

Disclosure of Invention

The invention aims to solve the technical problems that a clock frequency detection circuit is influenced by a process, low in configurability, poor in flexibility and poor in universality.

In order to solve the above problems, the present invention provides a clock frequency detection circuit, which includes a frequency division unit 1, a synchronization unit, a rising edge pulse generation unit, a frequency division unit 2, a scale clock counting unit, a count value storage unit, a frequency upper limit setting unit, a frequency lower limit designing unit, and a comparison unit; as seen from the circuit structure, the circuit is a pure digital circuit, so that the circuit is not influenced by the process; the frequency dividing unit 1, the frequency dividing unit 2, the upper frequency limit setting unit and the lower frequency limit setting unit can be configured according to different systems according to different requirements of the clock to be tested and the high-frequency reference clock, and the circuit can be transplanted to different chip systems; therefore, the circuit has the advantages of high configurability, strong flexibility and strong universality.

And the frequency division unit 1 is used for dividing the frequency of the clock to be measured so that the difference between the clock to be measured and the scale clock is not large, so that the counting value is reduced.

And the synchronization unit is used for synchronizing the frequency-divided clock to be measured into the scale clock so as to generate a rising edge for the subsequent rising edge pulse generation unit, and the rising edge acts in the scale clock, so that synchronization is needed.

And the rising edge pulse generating unit is used for generating a rising edge pulse signal, acting on the counting value storage unit and the scale counting unit, resetting the stored value and determining a resetting point of the scale counting.

And the frequency division unit 2 is used for generating a scale clock signal by dividing the frequency of the generated high-frequency clock signal so as to carry out frequency detection on the clock to be detected, and the frequency division can be configured according to the clock to be detected so that the clock to be detected is close to the scale clock.

And the scale clock counting unit is used for counting the clock to be measured by the scale clock, and resetting the counting to 0 at a reset point of the counting according to the rising edge pulse signal, wherein the two rising edge pulses are the clock period signal to be measured after frequency division.

And the counting value storage unit is used for storing the counting value of the scale counting in real time so as to be used for clock comparison detection.

And the comparison unit is used for comparing the actual value obtained by counting through the scale clock with the expected value to obtain a result.

And a frequency upper limit setting unit for configuring a high frequency clock upper limit value expected according to the scale clock count.

And a lower frequency limit setting unit for configuring a lower frequency clock limit value expected according to the scale clock count.

The invention provides a clock frequency detection circuit, a clock to be detected is divided by a frequency dividing unit 1, a high-frequency reference clock generates a scale clock by a frequency dividing unit 2, a synchronizing unit synchronizes the divided clock to be detected to the scale clock, a rising edge pulse signal generating unit generates a rising edge, the scale clock continuously counts the divided clock to be detected, a count value is set to be 0 according to a rising edge pulse, after the previous rising edge is set to be 0, a count value is continuously increased according to the scale clock before the next rising edge arrives, the count value is stored in a count storage unit, and a comparison unit compares the count value with an expected value stored in a frequency upper limit setting unit and a frequency lower limit setting unit in real time to judge whether the clock frequency is normal or not. The clock frequency detection circuit provided by the invention has a simple structure, can configure frequency division and expected values according to requirements, is flexible and changeable, and has a wide application range. Therefore, the problems that an analog circuit is complex in circuit realization, influenced by processes, low in configurability, poor in flexibility and poor in universality are solved.

Drawings

FIG. 1 is a circuit configuration diagram of a clock frequency detection circuit;

FIG. 2 is a block diagram of rising edge pulse signal generation;

FIG. 3 is a waveform diagram of a count of the clock detection circuit;

Detailed Description

The invention will be described in further detail with reference to the following detailed description and accompanying drawings:

the circuit structure diagram of a clock frequency detection circuit of the present invention is shown in fig. 1, and includes a frequency dividing unit 1, a synchronizing unit, a rising edge pulse generating unit, a high frequency clock unit, a frequency dividing unit 2, a scale clock counting unit, a count storage unit, a frequency upper limit setting unit, a frequency lower limit setting unit, and a comparing unit. The distribution unit 1, the synchronization unit and the rising edge pulse generation unit are sequentially connected, the high-frequency clock unit, the distribution unit 2, the scale clock counting unit and the count value storage unit are sequentially connected, the rising edge generation unit is connected with the scale clock unit and the count value storage unit, the count value storage unit is connected with the comparison unit, and the frequency upper limit setting unit and the frequency lower limit setting unit are respectively connected with the comparison unit.

When the clock frequency detection circuit starts to work, a clock to be detected is firstly connected into the clock frequency detection circuit, a frequency division coefficient of a frequency division unit 1 is configured, then a frequency division coefficient of a frequency division unit 2 is configured according to a high-frequency clock generated by the high-frequency clock unit and the clock to be detected after frequency division, so that the generated high-frequency clock is reasonably divided to obtain a scale clock, the scale clock is enabled to be close to the clock to be detected, if the frequency of the scale clock is far higher than the clock to be detected, the counting of the scale clock is increased, if the frequency of the scale clock is far lower than the clock to be detected, the clock to be detected needs to be divided with great force, a high-frequency expected value is calculated and configured according to the scale clock and the expected high-frequency clock; and calculating a configuration low-frequency expected value and matching frequency lower limit setting unit according to the scale clock and the expected low-frequency clock so as to be used for low-frequency clock detection and comparison.

In this embodiment, referring to fig. 2, the rising edge pulse signal generating circuit structure includes a clock divider for dividing a clock to be measured, a scale clock for sampling the divided clock by three stages of registers, a rising edge generator for generating a rising edge pulse by using an output value of a second stage register and an output value of a third stage register, and a rising edge pulse signal generated when the second stage register is high and the third stage register is low.

In this embodiment, the clock to be measured clk _ t is divided by the frequency dividing unit 1 to obtain clk _ tf, the clk _ tf is divided by the synchronizing unit to obtain clk _ tf _ d2, according to clk _ tf _ d1 and clk _ tf _ d2, when clk _ tf _ d1 is high, clk _ tf _ d2 is low to obtain clk _ flag signal, the count value is continuously counted along with the scale clock clk _ rule clock, the count value is reset according to the clk _ flag signal, between two adjacent clk _ flag signals, namely, the clock after frequency division of the clock to be measured, the count value should meet the requirement of an expected value, that is, the larger the n value is, the lower the corresponding clock frequency to be measured is, and the smaller the n value is, the higher the corresponding clock frequency to be measured is. As fig. 3, a count waveform diagram of the clock detection circuit is described. The obtained n value is compared with a value configured by the frequency upper limit setting unit in real time, a high-frequency alarm signal fd _ h is output when the n value is smaller than the configured upper limit value, the real-time n value is compared with a value configured by the frequency lower limit setting unit, a low-frequency alarm signal fd _ l is output when the n value is larger than the configured lower limit value, and the output fd _ h and fd _ l signals can be used for judging that the clock frequency is not in a range value, can be used for chip self-checking calibration, and can also be used for judging the basis of chip failure.

The present invention has been described in detail with reference to the specific embodiments and examples, but these are not intended to limit the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.