阅读说明：本技术 一种半导体存储器及其制备方法 (Semiconductor memory and preparation method thereof ) 是由 不公告发明人 于 2018-09-07 设计创作，主要内容包括：本发明提供一种半导体存储器及其制备方法,在半导体衬底上形成多个间隔排布的有源区；在半导体衬底上沿预定方向形成位线接触窗；沿垂直于预定方向的方向形成字线,以将位线接触窗切断,两条字线中间形成独立的位线接触窗。减小了黄光对准形成位线接触窗的难度,避免了现有技术中形成位线接触孔对准偏差造成的电阻过大的问题。在位线接触窗上方形成位线；允许其与位线接触窗之间具有一定的偏移量,这样既可以实现良好的接触,又能减小电阻。沿字线的平行方向在有源区之间形成隔离线介质层；在字线、位线及所述隔离线介质层之间填充第二导电材料形成导电层。通过字线隔离层和位线隔离层作为侧壁实现存储接触窗之间的自对准隔离,可操作性强。(The invention provides a semiconductor memory and a preparation method thereof.A plurality of active regions which are arranged at intervals are formed on a semiconductor substrate; forming a bit line contact window along a predetermined direction on a semiconductor substrate; word lines are formed in a direction perpendicular to the predetermined direction to cut off the bit line contacts, and an independent bit line contact is formed between the two word lines. The difficulty of forming a bit line contact window by yellow light alignment is reduced, and the problem of overlarge resistance caused by alignment deviation of a bit line contact hole in the prior art is solved. Forming a bit line above the bit line contact window; and a certain offset is allowed between the contact window and the bit line contact window, so that good contact can be realized, and the resistance can be reduced. Forming an isolation line dielectric layer between the active regions along the parallel direction of the word lines; and filling a second conductive material among the word lines, the bit lines and the isolation line dielectric layer to form a conductive layer. Self-alignment isolation between the storage contact windows is achieved by using the word line isolation layer and the bit line isolation layer as side walls, and operability is high.)

1. A method for manufacturing a semiconductor memory, the method at least comprising the following steps:

s01, providing a semiconductor substrate, and forming a plurality of active regions arranged at intervals on the semiconductor substrate, wherein the active regions comprise first contact regions and second contact regions positioned at two sides of the first contact regions;

s02, forming a bit line contact window, and forming the bit line contact window along a preset direction on the semiconductor substrate;

s03, forming word lines, forming the word lines on the semiconductor substrate along a direction perpendicular to the predetermined direction, the word lines cutting off the bit line contacts, and forming the independent bit line contacts between the two word lines; and

and S04, forming a bit line, and forming the bit line above the bit line contact window.

2. The method of manufacturing according to claim 1, further comprising the steps of:

s05, forming isolation line dielectric layers, and forming the isolation line dielectric layers between the active regions along the extending direction of the word lines; and

and S06, forming capacitor contacts, and filling a second conductive material among the word lines, the bit lines and the isolation line dielectric layer to form the capacitor contacts.

3. The method of claim 1 or 2, wherein in step S01, STI is performed using a shallow trench isolation technique

And forming an isolation structure on the semiconductor substrate, wherein the isolation structure isolates the plurality of active regions arranged at intervals on the semiconductor substrate.

4. The method of claim 2, wherein the step of forming the bit line contact at step S02 comprises the steps of:

s02-1, growing a first dielectric layer on the semiconductor substrate to protect the active region, wherein the first dielectric layer comprises one or a combination of silicon nitride, silicon oxide and silicon oxynitride;

s02-2, sequentially growing a first hard mask and coating a photoresist layer on the first dielectric layer, and forming a bit line contact window pattern on the photoresist layer;

s02-3, forming a bit line contact window pattern on the first hard mask through etching;

s02-4, removing the photoresist layer, and simultaneously transferring the bit line contact window pattern to the first dielectric layer and the semiconductor substrate to form a bit line contact window groove;

s02-5, filling a first interval insulating layer in the bit line contact window groove, and simultaneously forming the first interval insulating layer on the hard mask;

s02-6, etching back the first interval insulating layer, and reserving the first interval insulating layer on the side wall of the bit line contact window groove; and

and S02-7, filling a first conductive material in the bit line contact window groove with the first interval insulating layer on the side wall, and removing the first hard mask to form the bit line contact window along the preset direction.

5. The method according to claim 4, wherein the first conductive material comprises one of tungsten, titanium, nickel, aluminum, titanium oxide, titanium nitride, or a combination thereof.

6. The method of claim 4, wherein the step S03, forming the word line comprises the steps of:

s03-1, forming a word line mask on the semiconductor substrate on which the bit line contact is formed, and forming a word line trench on the semiconductor substrate along a direction perpendicular to the predetermined direction, wherein the word line trench cuts the bit line contact, and an independent bit line contact is formed between two word lines;

s03-2, sequentially filling a gate oxide layer and a word line conductor in the word line groove, and then carrying out back etching to form a required word line; and

s03-3, filling a word line isolation layer above the word line in self-alignment to protect the word line.

7. The method of claim 6, wherein the step S04, forming the bit line comprises the steps of:

s04-1, defining a bit line pattern along the preset direction, and etching a bit line groove through a second hard mask with a groove pattern;

s04-2, depositing a second isolation insulating layer in the bit line trench, etching back the second isolation insulating layer, and only reserving the second isolation insulating layer at the position of the side wall of the bit line trench; and

and S04-3, depositing a bit line conductor in the middle of the insulating layer at the side wall position of the bit line groove, and etching back to obtain the bit line.

8. The method according to claim 7, wherein the step S04 further comprises the steps of:

s04-4, filling a bit line isolation layer over the bit line in self-alignment, then removing the hard mask and either through a chemical mechanical mask or etching back the bit line isolation layer to the word line mask location.

9. The production method according to claim 1, 2 or 7, wherein the bit line has a wavy pattern.

10. The method of claim 9, wherein the bit line and the bit line contact window have an offset therebetween.

11. The method of claim 10, wherein the bitline width is greater than the bitline contact width.

12. The method according to claim 7, wherein the step S05 includes the steps of:

s05-1, removing the word line mask, etching to expose the first dielectric layer, and removing the bit line contact window material outside the first contact area;

s05-2, depositing a second dielectric layer on the upper portion of the surface of the formed structure, etching back the second dielectric layer, and reserving the second dielectric layer on the word line isolation layer and the bit line isolation layer side wall to form an isolation groove; and

and S05-3, filling a third dielectric layer above the structure formed in the previous step and in the isolation trench, etching back the third dielectric layer, and only keeping the third dielectric layer in the isolation trench to form the isolation line dielectric layer.

13. The method of claim 12, wherein the step S06 of forming the capacitor contact comprises the steps of:

s06-1, realizing self-alignment isolation between storage contact windows through the second dielectric layers on the side walls of the word line isolation layer and the bit line isolation layer, selectively etching the second dielectric layers on the side walls of the word line isolation layer and the bit line isolation layer and the first dielectric layers below the second dielectric layers, exposing the active region of the semiconductor substrate, and forming a capacitor contact window groove;

s06-2, filling a second conductive material above the structure formed in the previous step and in the capacitor contact window groove, and connecting the second conductive material to the second contact region of the active region; and

and S06-3, removing the redundant second conductive material and only keeping the second conductive material in the contact window groove.

14. A semiconductor memory, characterized in that the semiconductor memory comprises at least:

the semiconductor device comprises a semiconductor substrate, a first electrode and a second electrode, wherein the semiconductor substrate is provided with a plurality of active regions which are arranged at intervals, and the active regions comprise first contact regions and second contact regions which are positioned on two sides of the first contact regions;

bit line contact windows formed in a predetermined direction on the semiconductor substrate;

word lines formed on the semiconductor substrate in a direction perpendicular to the predetermined direction, the word lines cutting off the bit line contact windows, and an independent bit line contact window being formed between the two word lines; and

bit lines formed over the bit line contacts;

the semiconductor substrate is provided with an isolation structure, and the isolation structure isolates the plurality of active regions on the semiconductor substrate; and is

And a first dielectric layer is grown on the semiconductor substrate to protect the active region, and the first dielectric layer comprises one or the combination of silicon nitride, silicon oxide and silicon oxynitride.

15. The semiconductor memory according to claim 14, further comprising:

the isolation line dielectric layer is positioned between the active regions along the parallel direction of the word lines; and

and the conductive material layer is positioned among the word lines, the bit lines and the isolation line dielectric layer and is connected to the second contact region of the active region.

16. The semiconductor memory according to claim 14 or 15, wherein the bit line contact comprises a first spacer insulating layer on sidewalls of the bit line contact and a first conductive layer in between the first spacer insulating layer.

17. The semiconductor memory according to claim 16, wherein the first conductive layer comprises one of tungsten, titanium, nickel, aluminum, titanium oxide, titanium nitride, or a combination thereof.

18. The semiconductor memory according to claim 14 or 15,

the word line comprises a gate oxide layer, a word line conductor and a word line isolation layer, wherein the gate oxide layer and the word line conductor are formed through deposition in sequence, and the word line isolation layer is formed above the word line conductor in a self-alignment filling mode.

19. The semiconductor memory according to claim 14 or 15, wherein the bit line comprises a second isolation insulating layer, a bit line conductor and a bit line isolation layer filled in self-alignment over the second isolation insulating layer and the bit line conductor, the second isolation insulating layer forming sidewalls of the bit line, the bit line conductor being located in the middle of the second isolation insulating layer.

20. The semiconductor memory according to claim 19, wherein the bit lines have a wavy pattern.

21. The semiconductor memory according to claim 14 or 15, wherein the bit line and the bit line contact window have an offset therebetween.

22. The semiconductor memory according to claim 21, wherein the bit line width is larger than a width of the bit line contact window.

Technical Field

The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a semiconductor memory and a preparation method thereof.

Background

As the size of memory devices continues to shrink, the feature sizes of the various components in the memory devices shrink, which is a significant challenge for current photolithography processes.

When a multi-pass photolithography process is performed, the mask has a problem of alignment deviation, which may affect electrical connection and isolation between some components in the memory. In a conventional method for fabricating a memory, the mask for the bit line contact and the storage node contact is a contact mask. When the bit line contact window and the storage node contact window are directly defined by using a photolithography process, a large displacement deviation is likely to be generated between the formed contact window and the contact area, and further, the contact resistance is too large or a large parasitic capacitance is generated with other conductors in the device. The above problems not only affect the performance of the subsequently formed memory, but also do not facilitate the reduction of the device size.

Disclosure of Invention

Accordingly, the present invention provides a semiconductor memory and a method for fabricating the same, which reduces the yellow light process, solves the problem of the alignment offset of the bit line contacts, and achieves the self-aligned isolation between the memory contacts.

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, the method comprising at least the steps of:

s01, providing a semiconductor substrate, and forming a plurality of active regions arranged at intervals on the semiconductor substrate, wherein the active regions comprise first contact regions and second contact regions positioned at two sides of the first contact regions;

s02, forming a bit line contact window, and forming the bit line contact window along a preset direction on the semiconductor substrate;

s03, forming word lines, forming the word lines on the semiconductor substrate along a direction perpendicular to the predetermined direction, the word lines cutting off the bit line contacts, and forming an independent bit line contact between the two word lines; and

and S04, forming a bit line, and forming the bit line above the bit line contact window.

Optionally, the preparation method further comprises the following steps:

s05, forming isolation line dielectric layers, and forming the isolation line dielectric layers between the active regions along the extending direction of the word lines; and

and S06, forming capacitor contacts, and filling a second conductive material among the word lines, the bit lines and the isolation line dielectric layer to form the capacitor contacts.

Optionally, in step S01, an isolation structure is formed on the semiconductor substrate by using a Shallow Trench Isolation (STI) technique, where the isolation structure isolates a plurality of active regions arranged at intervals on the semiconductor substrate.

Optionally, in step S02, the forming the bit line contact window includes the following steps:

s02-1, growing a first dielectric layer on the semiconductor substrate to protect the active region, wherein the first dielectric layer comprises one or a combination of silicon nitride, silicon oxide and silicon oxynitride;

s02-2, sequentially growing a first hard mask and a photoresist layer on the first dielectric layer, and forming a bit line contact window pattern on the photoresist layer;

s02-3, forming a bit line contact window pattern on the first hard mask through etching;

s02-4, removing the photoresist layer, and simultaneously transferring the bit line contact window pattern to the first dielectric layer and the semiconductor substrate to form a bit line contact window groove;

s02-5, filling a spacing insulating layer in the bit line contact window groove, and simultaneously forming the spacing insulating layer on the hard mask;

s02-6, etching back the spacing insulating layer, and reserving the spacing insulating layer on the side wall of the bit line contact window groove; and

s02-7, the bit line contact trench having the spacer insulating layer on the sidewall is filled with a first conductive material, and the first hard mask is removed to form a bit line contact along a predetermined direction.

Optionally, the first conductive material is one of tungsten, titanium, nickel, aluminum, titanium oxide, titanium nitride, or a combination thereof.

Alternatively, in step S03, forming the word line includes the following steps:

s03-1, forming a word line mask on the semiconductor substrate with the bit line contact window, manufacturing a word line groove on the semiconductor substrate along the direction vertical to the preset direction, cutting off the bit line contact window by the word line groove, and forming an independent bit line contact window between two word lines;

s03-2, sequentially filling the gate oxide layer and the word line conductor in the word line structure, and then carrying out back etching to form the required word line; and

s03-3, filling the word line isolation layer above the word line in self-alignment to protect the word line.

Optionally, in step S04, forming the bit line includes the following steps:

s04-1, defining the wave-shaped pattern of the bit line along the preset direction, and etching the bit line groove by a second hard mask with a groove pattern;

s04-2, depositing an interval insulating layer in the bit line groove, etching back the interval insulating layer, and only reserving the insulating layer at the side wall position of the bit line groove; and

and S04-3, depositing a bit line conductor in the middle of the insulating layer at the side wall position of the bit line groove, and etching back to obtain the bit line.

Optionally, step S04 further includes S04-4 filling the bit line isolation layer self-aligned over the bit lines, then removing the second hard mask and either chemical mechanical masking or etching back the bit line isolation layer to the word line mask locations.

Optionally, the bit lines have a wavy pattern.

Optionally, the bit line and the bit line contact window have an offset therebetween.

Optionally, the bit line width is greater than the width of the bit line contact.

Optionally, step S05 specifically includes the following steps:

s05-1, removing the word line mask, etching to expose the first dielectric layer, and removing the bit line contact material outside the first contact region;

s05-2, depositing a second dielectric layer on the upper portion of the surface of the formed structure, etching back the second dielectric layer, and reserving the second dielectric layer on the word line isolation layer and the bit line isolation layer side wall to form an isolation groove; and

s05-3, filling a third dielectric layer above the structure formed in the previous step and in the isolation trench, etching back the third dielectric layer, and only keeping the third dielectric layer in the isolation trench to form an isolation line dielectric layer.

Optionally, in step S06, the forming the capacitor contact includes the following steps:

s06-1, realizing self-alignment isolation between the storage contact windows through the second dielectric layers on the side walls of the word line isolation layer and the bit line isolation layer, selectively etching the second dielectric layers on the side walls of the word line isolation layer and the bit line isolation layer and the first dielectric layer below the second dielectric layers, exposing the active region of the semiconductor substrate, and forming a capacitor contact window groove;

s06-2, filling a second conductive material above the structure formed in the previous step and in the capacitor contact window groove, and connecting the second conductive material to the active region; and

and S06-3, removing the redundant second conductive material and only keeping the second conductive material in the contact window groove.

According to a second aspect of the present application, the present invention provides a semiconductor memory including at least:

the semiconductor device comprises a semiconductor substrate, a first contact layer and a second contact layer, wherein the semiconductor substrate is provided with a plurality of active regions which are arranged at intervals, and the active regions comprise first contact regions and second contact regions which are positioned at two sides of the first contact regions;

bit line contact windows formed in a predetermined direction on the semiconductor substrate;

word lines formed on the semiconductor substrate in a direction perpendicular to the predetermined direction, the word lines cutting off the bit line contact windows, and an independent bit line contact window being formed between the two word lines; and

bit lines formed above the bit line contact windows;

the semiconductor substrate is provided with an isolation structure, and the isolation structure isolates the plurality of active regions on the semiconductor substrate; and is

And a first dielectric layer is grown on the semiconductor substrate to protect the active region, and the first dielectric layer comprises one or the combination of silicon nitride, silicon oxide and silicon oxynitride.

Optionally, the semiconductor memory further comprises:

the isolation line dielectric layer is positioned between the active regions along the parallel direction of the word lines; and

and the conductive material layer is positioned among the word lines, the bit lines and the isolation line dielectric layer and is connected to the second contact region of the active region.

Optionally, the bit line contact includes an insulating spacer layer and a first conductive layer, the insulating spacer layer is located on a sidewall of the bit line contact, and the first conductive layer is located in the middle of the insulating spacer layer.

Optionally, the first conductive layer comprises one of tungsten, titanium, nickel, aluminum, titanium oxide, titanium nitride, or a combination thereof.

Optionally, the word line comprises a gate oxide layer, a word line conductor and a word line isolation layer formed by self-aligned filling above the word line conductor, wherein the gate oxide layer and the word line conductor are formed by deposition in sequence.

Optionally, the bit line includes a second spacer insulator, a second conductive layer, and a bit line isolation layer formed by filling in self-alignment above the spacer insulator and the second conductive layer, the spacer insulator is located on a sidewall of the bit line, and the second conductive layer is located in the middle of the spacer insulator.

Optionally, the bit lines have a wavy pattern.

Optionally, the bit line and the bit line contact window have an offset therebetween.

Optionally, the bit line width is greater than the width of the bit line contact.

As described above, the semiconductor memory and the manufacturing method thereof of the present invention have the following technical effects:

1. the invention relates to a semiconductor memory and a preparation method thereof.A bit line contact window is formed on a semiconductor substrate along a preset direction; and forming word lines along a direction perpendicular to the preset direction, cutting off the bit line contact windows by the word lines, and forming an independent bit line contact window between the two word lines, so that the difficulty of forming the bit line contact windows by yellow light alignment is reduced. Meanwhile, the bit line contact window is cut off, so that the problem of overlarge resistance caused by alignment deviation of bit line contact holes in the prior art is solved.

2. When the bit line groove is formed, a certain offset is allowed to be arranged between the bit line groove and the bit line contact window, so that the subsequently formed bit line can also have a certain offset between the bit line contact window and the bit line. For example, the bit line width is allowed to be larger than the width of the bit line contact window. This can achieve both good contact and reduced electrical resistance.

3. The bit line is made into a wave shape, and the wave-shaped bit line can isolate the storage contact windows of the upper and lower active regions and can be separated from the bit line contact window material of the isolation region, so that the bit line can be removed conveniently in the follow-up process.

4. The word line isolation layer and the bit line isolation layer are used as side walls, self-alignment isolation between the storage contact windows is achieved, and operability is high.

Drawings

The features and advantages of the present invention will be more clearly understood by reference to the accompanying drawings, which are illustrative and not to be construed as limiting the invention in any way, and in which:

FIG. 1 is a flow chart illustrating a method for fabricating a semiconductor memory according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram illustrating a structure obtained in step S01 in the method for manufacturing a semiconductor memory according to one embodiment of the present invention;

FIG. 3 is a schematic cross-sectional view taken along line A-A' of FIG. 2;

fig. 4 is a schematic structural diagram illustrating a structure obtained in step S02 in the method for manufacturing a semiconductor memory according to one embodiment of the present invention;

FIGS. 5-6 are schematic views showing cross-sectional structures taken along the line A-A' in FIG. 4;

fig. 7 is a schematic structural diagram illustrating a structure obtained in step S03 in the method for manufacturing a semiconductor memory according to one embodiment of the present invention;

FIGS. 8-9 are schematic cross-sectional views along A-A' of FIG. 7;

fig. 10 is a schematic structural diagram illustrating a structure obtained in step S04 in the method for manufacturing a semiconductor memory according to one embodiment of the present invention;

FIGS. 11-12 are schematic cross-sectional views along A-A' of FIG. 10;

fig. 13 is a schematic diagram illustrating a structure obtained by forming a bit line isolation layer during the step S04 in the method for manufacturing a semiconductor memory according to one embodiment of the present invention.

Fig. 14-15 are schematic cross-sectional views along a-a' direction in fig. 13.

Fig. 16 is a schematic diagram illustrating a structure obtained by removing the word line mask and the bit line contact material outside the first contact region area during the step S05 in the method for manufacturing a semiconductor memory according to one embodiment of the present invention.

Fig. 17 is a schematic sectional view taken along a-a' direction in fig. 16.

Fig. 18 is a schematic structural diagram illustrating a structure obtained by depositing a second dielectric layer during step S05 in the method for manufacturing a semiconductor memory according to one embodiment of the present invention.

Fig. 19 is a schematic sectional view taken along a-a' direction in fig. 18.

Fig. 20 is a schematic diagram illustrating a structure obtained by forming an isolation line dielectric layer in step S05 in the method for manufacturing a semiconductor memory according to one embodiment of the present invention.

Fig. 21-22 are schematic cross-sectional views along a-a' in fig. 20.

Fig. 23 is a schematic structural diagram illustrating a structure obtained in step S06 in the method for manufacturing a semiconductor memory according to one embodiment of the present invention;

fig. 24 is a schematic sectional view taken along a-a' direction in fig. 23.

Reference numerals

100 semiconductor substrate

110 active region

111 bit line contact region

112 storage node contact area

120 isolation structure

130 first dielectric layer

131 hard mask

140' bit line contact trench

140a first spacer insulating layer

140b first conductive material

140 bit line contact window

220 word line

210' word line trench

210 word line mask

220a word line conductor

220b word line isolation layer

300 bit line

310 second hard mask

310' bit line trench

300a second isolation insulating layer

300b bit line conductor

300c bit line isolation layer

410 second dielectric layer

410a second dielectric layer structure

420 isolating line dielectric layer

420' isolation trench

500 second conductive material

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The invention provides a semiconductor memory and a preparation method thereof, which solve the problems that in the prior art, alignment deviation exists in a photomask, and the reduction of the size of a component is not facilitated.