阅读说明：本技术 使用管理数据输入/输出接口将外部phy设备连接到mac设备 (Connecting an external PHY device to a MAC device using a management data input/output interface ) 是由 J·福纳尔 Z·福多尔 于 2019-08-12 设计创作，主要内容包括：示例包括通过确定外部物理层设备与介质访问控制设备之间的通信链路的模式来将外部物理层设备连接到介质访问控制设备；以及当通信链路的模式是串行千兆比特介质无关接口(SGMII)时,启用外部物理层设备与介质访问控制设备之间的集成电路间(I2C)接口,并且将管理数据输入/输出(MDIO)事务的目的地设置为外部物理层设备。(Examples include connecting an external physical layer device to a media access control device by determining a mode of a communication link between the external physical layer device and the media access control device; and when the mode of the communication link is Serial Gigabit Media Independent Interface (SGMII), enabling an inter-integrated circuit (I2C) interface between the external physical layer device and the media access control device and setting a destination of a management data input/output (MDIO) transaction as the external physical layer device.)

1. A method, comprising:

determining a mode of a communication link between an external physical layer device and a medium access control device; and

when the mode of the communication link is Serial Gigabit Media Independent Interface (SGMII), enabling an inter-integrated circuit (I2C) interface between the external physical layer device and the media access control device and setting a destination for management data input/output (MDIO) transactions as the external physical layer device.

2. The method of claim 1, comprising setting a media type to copper when the mode is SGMII.

3. The method of claim 1 including setting an SGMII activity variable to true when the pattern is SGMII.

4. The method of claim 1, comprising performing an MDIO transaction between the external physical layer device and the media access control device in SGMII mode using an MDIO protocol when the mode is SGMII.

5. The method of claim 1, wherein the media access control device comprises an ethernet Network Interface Controller (NIC).

6. The method of claim 1, comprising transmitting Audio Video Bridge (AVB) packets between the external physical layer device and the media access control device.

7. A processing system, comprising:

a network input/output (I/O) device coupled with at least one external physical layer device; and

a network I/O device driver to determine a mode of a communication link between the network I/O device and the at least one external physical layer device; and when the mode of the communication link is Serial Gigabit Media Independent Interface (SGMII), enabling an inter-integrated circuit (I2C) interface between the external physical layer device and the network I/O device and setting a destination of a management data input/output (MDIO) transaction as the external physical layer device.

8. The processing system of claim 7, comprising the network I/O device driver to set a media type to copper when the mode is SGMII.

9. The processing system of claim 7, comprising the network I/O device driver to set an SGMII activity variable to true when the mode is SGMII.

10. The processing system of claim 7, wherein the network I/O device comprises MDIO circuitry to perform an MDIO transaction between the external physical layer device and the network I/O device in SGMII mode using an MDIO protocol when the mode is SGMII.

11. The processing system of claim 7, wherein the network I/O device comprises an ethernet Network Interface Controller (NIC) having media access control circuitry.

12. The processing system of claim 7, comprising an operating system including the network I/O device driver.

13. The processing system of claim 12, wherein the operating system is Linux^TM。

14. The processing system of claim 7, comprising the network I/O device to control sending Audio Video Bridge (AVB) packets between the external physical layer device and the network I/O device.

15. At least one machine readable medium comprising a plurality of instructions that in response to being executed by a system, cause the system to carry out a method according to any one of claims 1 to 6.

16. An apparatus comprising means for performing the method of any of claims 1-6.

Background

The Open Systems Interconnection (OSI) model is a conceptual framework that characterizes and standardizes the communication functions of a telecommunications or computing system, regardless of its underlying internal structure and technology. The model divides the communication system into abstraction layers.

The physical layer (PHY) is responsible for transmitting and receiving unstructured raw data between the device and the physical transmission medium. The layer specification defines characteristics such as voltage level, timing of voltage changes, physical data rate, maximum transmission distance, and physical connectors. These characteristics include pin layout, voltage, line impedance, cable specifications, signal timing and frequency of the wireless device. The components of the physical layer may be described in terms of network topology. An example of a protocol using the physical layer is ethernet (as defined by the Institute of Electrical and Electronics Engineers (IEEE)802.3 standard, described at standards.

The data link layer provides node-to-node data transfer — a link between two directly connected nodes. The data link layer defines the protocol used to establish and terminate a connection between two physically connected devices. The data link layer also defines a protocol for flow control between two physically connected devices. In one example, the IEEE 802.3 ethernet standard divides the data link layer into two sub-layers: a) media Access Control (MAC) layer-responsible for controlling how devices in the network gain access to the medium and permission to transfer data; and b) Logical Link Control (LLC) layer, responsible for identifying and encapsulating network layer protocols, and controlling error checking and frame synchronization.

In some cases, there are difficulties in connecting an external PHY device to a MAC device (e.g., an ethernet Network Interface Controller (NIC)). One approach is to integrate PHY devices into MAC devices (referred to as internal PHY methods). However, this approach introduces various limitations on the ability to be delivered by the PHY module. Notably, internal PHY approaches fail to provide the ability to switch to a different, more suitable PHY device (e.g., in terms of better supported connections, better supported temperature ranges, etc.).

Another approach is to use an external PHY device but with a connection through a serializer/deserializer (SERDES) interface. The SERDES interface includes a pair of functional blocks that are typically used for high speed communications to compensate for limited input/output. These blocks convert data in each direction between the serial data and parallel interfaces. The primary purpose of SerDes is to provide data transmission over a single line or differential pair in order to minimize the number of I/O pins and interconnects. In this approach, the connection to the external PHY device is achieved by using an integrated circuit capable of converting parallel data into the serial equivalent of data (and vice versa). Unfortunately, some external PHY devices do not support SERDES connections. Therefore, a better method is needed.

Drawings

FIG. 1 illustrates an example computing system.

FIG. 2 illustrates an example network I/O device.

FIG. 3 illustrates an example software stack for network I/O processing.

Fig. 4 illustrates an example flow diagram of a process for connecting an external PHY device to a MAC device using a management data I/o (mdio) interface.

Fig. 5 shows an example flow diagram of a process for establishing a media type.

Fig. 6 shows an example of a storage medium.

FIG. 7 illustrates another example computing platform.

Detailed Description

Embodiments of the present invention disclose an improved device driver for a network I/O device (e.g., an Ethernet NIC) to successfully establish full link functionality for a hardware configuration including one or more external PHY devices using a management data I/O (MDIO) interface. In an embodiment, the full link functionality provides the ability to send and receive Audio Video Bridge (AVB) packets in accordance with the IEEE802.1 BA Standard, known as the Local and Metropolitan area network IEEE Standard-Audio Video Bridging (AVB) System (IEEE Standard for Local and metropolian area networks-Audio-Visual Bridging (AVB) System, which is available at www.ieee802.org/1/pages/802.1BA.

FIG. 1 illustrates an example computing system 100. As shown in fig. 1, computing system 100 includes a computing platform 101 coupled to a network 170 (which may be the internet, for example). In some examples, as shown in fig. 1, computing platform 101 is coupled to network 170 via network communication channel 175 and through network I/O device 110 (e.g., a Network Interface Controller (NIC)), which network I/O device 110 has one or more ports connected to or coupled to network communication channel 175. In an embodiment, the network communication channel 175 includes a PHY device (not shown). In an embodiment, network I/O device 110 is an ethernet NIC. Network I/O device 110 sends data packets from computing platform 101 to other destinations over network 170 and receives data packets from other destinations for forwarding to computing platform 101.

According to some examples, computing platform 101 as shown in fig. 1 includes circuitry 120, main memory 130, Network (NW) I/O device driver 140, Operating System (OS)150, at least one application 160, andone or more storage devices 165. In one embodiment, OS 150 is Linux^TM. In another embodiment, OS 150 is

And (4) a server. The network I/O device driver 140 operates to initialize and manage I/O requests executed by the network I/O device 110. In an embodiment, packets and/or packet metadata sent to and/or received from network I/O device 110 are stored in one or more of main memory 130 and/or storage 165. In at least one embodiment, the storage 165 may be one or more of a Hard Disk Drive (HDD) and/or a Solid State Drive (SSD). In an embodiment, storage 165 may be a non-volatile memory (NVM). In some examples, as shown in fig. 1, circuitry 120 may be communicatively coupled with network I/O device 110 via a communication link 155. In one embodiment, the communication link 155 is a peripheral component interface express (PCIe) bus compliant with the PCIe version 3.0 or other version of the PCIe standard promulgated by the PCI special interest group (PCI-SIG) at PCI. In some examples, the operating system 150, NW I/O device drivers 140, and applications 160 are implemented, at least in part, via cooperation between one or more memory devices included in the main memory 130 (e.g., volatile or non-volatile memory devices), the storage 165, and elements of the circuitry 120 (e.g., the processing cores 122-1 through 122-m, where "m" is any positive integer greater than 2). In an embodiment, the OS 150, NW I/O device drivers 140, and applications 160 are executed by one or more processing cores 122-1 through 122-m.

In some examples, computing platform 101 includes, but is not limited to, a server array or server farm, a web server, a network server, an internet server, a workstation, a minicomputer, a mainframe computer, a supercomputer, a network appliance, a web appliance, a distributed computing system, multiprocessor systems, processor-based systems, laptop computers, tablet computers, smart phones, or combinations thereof. In one example, computing platform 101 is a disaggregated server. A decomposed server is a server that decomposes components and resources into subsystems. The disaggregated server may be adapted as needed to alter storage or computing load without replacing or disrupting the entire server for an extended period of time. For example, a server may be broken down into modular computing modules, I/O modules, power modules, and storage modules that may be shared among other nearby servers. In an embodiment, computing platform 101 is an infotainment system residing in a vehicle (e.g., automobile, truck, motorcycle, etc.), ship, airplane, or spacecraft.

The circuitry 120 having the processing cores 122-1 through 122-m may include various commercially available processors, including but not limited to

Core i3、Core i5、Core i7、

Or Xeon

Processors, ARM processors, and the like. The circuit 120 may include at least one cache 135 to store data.

According to some examples, main memory 130 may be comprised of one or more memory devices or dies that may include various types of volatile and/or non-volatile memory. Volatile types of memory may include, but are not limited to, Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), thyristor ram (tram), or zero capacitor ram (zram). The non-volatile type of memory may include a byte or block addressable type of non-volatile memory having a three-dimensional (3-D) cross-point memory structure that includes a chalcogenide phase change material (e.g., chalcogenide glass), hereinafter referred to as "3-D cross-point memory. The non-volatile type of memory may also include other types of byte or block addressable non-volatile memory, such as, but not limited to, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), Magnetoresistive Random Access Memory (MRAM) incorporating memristor technology, spin-torque-transfer MRAM (STT-MRAM), or a combination of any of the above. In another embodiment, main memory 130 may include one or more hard disk drives within computing platform 101 and/or accessible by computing platform 101.

FIG. 2 illustrates an example network I/O device 110. On the host side, network I/O device 110 is connected to computing platform 101 through a communication link 155 (e.g., a PCIe bus). On the network side, the network I/O device 110 is connected to a PHY device 220, the PHY device 220 forming at least a portion of the network communication channel 175 shown in fig. 1. PHY device 220 is any circuitry for implementing physical layer functions for networking. The PHY device connects the link layer device (i.e., network I/O device 110) to a physical medium (e.g., fiber optic or copper cable). PHY devices typically include both Physical Coding Sublayer (PCS) and Physical Medium Dependent (PMD) layer functions. PHY chips (also known as phyreceivers and embodied in PHY device 220) are common in ethernet devices. One purpose of the PHY device 220 is to provide analog signal physical access to the link. The PHY device 220 is used in conjunction with a Media Independent Interface (MII)222 communication link or interfaced with a microcontroller responsible for higher layer functions. When the PHY device 220 is an ethernet PHY chip, the PHY device implements hardware transmission and reception functions for ethernet frames. The PHY device 220 interfaces between the analog domain of ethernet line modulation and the digital domain of link layer packet signaling.

The MII222 is defined as a standard interface for connecting gigabit ethernet (MAC) blocks to PHY chips. MII is defined by IEEE 802.3 (available at standards. ee. org) and connects different types of PHY to MAC. The media independent representation may use different types of PHY devices for connection to different media (i.e., twisted pair, fiber, etc.) without redesigning or replacing the MAC hardware (i.e., network I/O device 110). Thus, any MAC may be used with any PHY independent of the network signaling medium. The MII may be used to connect the MAC to an external PHY using a pluggable connector, or directly to an internal PHY chip located on the same Printed Circuit Board (PCB).

Management data I/O (MDIO)218 serial bus circuitry is associated with the MII, which is used to communicate management information between the MAC and PHY components. Auto-negotiation is used at system power-up, unless settings are changed via the MDIO interface, the PHY device adapts to any MAC device it is connected to. Serial Gigabit Media Independent Interface (SGMII) is a variant of MII. SGMII is used for gigabit Ethernet, but can also carry 10/100 Mbit/s Ethernet. In an embodiment, the MII222 comprises an SGMII. SGMII uses differential pairs at 625 MHz clock frequency Double Data Rate (DDR) for Transmit (TX) and Receive (RX) data and TX and RX clocks. SGMII provides a serial 8b/10b encoded interface with low power and low pin count. The transmit path and the receive path each use one differential pair for data and the other differential pair for a clock. The TX/RX clock must be generated at the device output but is optional at the device input. In an embodiment, the MII222 is a SERDES interface. In an embodiment, the MII222 includes capabilities for both the SGMII interface and the SERDES interface.

Network I/O device 110 includes communication link 202 circuitry (e.g., PCIe bus circuitry) to communicate with communication link 155 of computing platform 101. The network I/O device 110 includes PHY interface circuitry 216 to communicate with PHY device 220 via an interface 222 (e.g., SGMII in an embodiment). Traffic and queue management circuitry 204 is included to manage the traffic flow of transmitted packets and received packets. A plurality of queues (e.g., Q1(206), Q2(208), Q3(210), and Q4(212)) are included to store incoming and outgoing packets and associated metadata. In an embodiment, at least one queue is used to store AVB packets. In other embodiments, any number of queues may be used. MAC circuit 214 is a processing unit within network I/O device 110 for processing transmit packets and/or receive packets.

In an embodiment, the network I/O device 110 is coupled with the external PHY device 220 using SGMII to send and receive AVB packets using MDIO 218 connections.

In an embodiment, the network I/O device 110 includes a plurality of registers including an extended device control register (CTRL _ EXT)224, a media dependent interface control register (MDIC)226, and an MDC/MDIO configuration register (MDICNFG) 228.

FIG. 3 illustrates an example software stack 300 for network I/O processing. Application 160 performs any processing desired by a user of the computing platform. In an embodiment, the application is an infotainment cockpit program for controlling and/or managing the operation of one or more functions of a vehicle (e.g., an automobile, truck, motorcycle, etc.), a ship, an aircraft, or a spacecraft. In an embodiment, the software stack 300 includes an AVB stream application 302, the AVB stream application 302 to manage the sending and receiving of AVB data streams in the computing platform 101. In an embodiment, the AVB streaming application 302 is part of the application 160. In another embodiment, the AVB streaming application 302 is part of the OS 150.

The software stack 300 includes at least three components for facilitating processing of AVB streams. Timing service component 304 synchronizes clocks (not shown) used in computing platform 101 and network 170. In an embodiment, timing service component 304 implements one or more of the following: published in 2018 as IEEE1588-2008, Precision Time Protocol (PTP) entitled "Precision Clock Synchronization protocol Standard for Networked Measurement and Control Systems" (available at Standard for a Precision Clock Synchronization protocol for Networked Measurement and Control Systems), and IEEE 802.as 1-2011 entitled "Local and metric Area Networks-Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks" (part of the IEEE (avb) Standard group), which is further extended by the IEEE802.1 Time-Sensitive networking (TSN) task group. IEEE802.1AS-2011 specifies the use of IEEE1588 + 2008 for time synchronization over virtual bridged lans. In particular, 802.1AS-2011 defines how IEEE 802.3 (ethernet), IEEE 802.11(WiFi), and multimedia over coax alliance (MoCA) implementations can all be part of the same PTP timing domain.

Flow reservation component 306 implements a flow reservation protocol for an ethernet implementation. In an embodiment, the flow reservation component 306 implements what is entitled "local and metropolitan area network standards-virtual bridged local area network-revision: 9: IEEE 802.1Q-2011 (available at www.ieee802.org/1/pages/802.1at. html) for Stream Reservation Protocol (SRP) (Standard for Local and Metapolitan Area Networks-Virtual bridge Area Networks-interpretation: 9: Stream Reservation Protocol (SRP)) ". SRP defines the concept of flows at layer 2 of the OSI model. Flow reservation component 306 provides a mechanism for end-to-end management of the resources of a flow to ensure quality of service (QoS).

The bandwidth control component 308 controls time-sensitive, loss-sensitive real-time AV transport. In an embodiment, bandwidth control component 308 implements the protocol entitled "local and metropolitan area network IEEE standard-virtual bridged local area network-revision: IEEE802.1 QAV (available at www.ieee802.org) for time-Sensitive stream Forwarding and Queuing Enhancements (IEEE Standard for Local and Metropolitan Area Networks- -virtual bridge Local Area Networks- -instructions: Forwarding and Queuing Enhancements for time-Sensitive Streams).

The network I/O library 310 is middleware software that provides low-level functionality to AVB stream processing applications. The network I/O library 310 should be understood as a proxy between the physical hardware (in this case the network I/O device 110) and the upper layer software application 160, enabling the physical hardware and upper layer software application 160 to communicate with registers, memory areas, etc. controlled by the network I/O device 110. At the lowest level of the software stack 300 is a network I/O device driver 140, the network I/O device driver 140 operates and/or controls the network I/O device 110. The network I/O device driver provides a software interface to the network I/O device 110, enabling the OS 150 and applications 160 to access network I/O hardware functions without needing to know the precise details about how the network I/O device operates. In an embodiment, the network I/O device driver 140 resides in the kernel space of the OS 150. In another embodiment, one or more of timing service 304, stream reservation 306, bandwidth control 308, network I/O library 310, and network I/O device drivers are part of OS 150.

FIG. 4 shows an example of a process for connecting an external PHY device to a MAC device using a management data I/O (MDIO) interfaceExample flow diagram 400. In an embodiment, the flow 400 is implemented as part of the network I/O device driver 140. In one embodiment, when OS 150 is Linux^TMBy using Linux pair^TMAn "insert module" (insmod) call by the OS installs the network I/O device driver 140 as a kernel module in the OS. During system initialization of the computing platform 101, the OS makes an "I/O control" (ioctl) call that is processed by ioctl handler functionality within the network I/O device driver 140 to instruct the driver to initialize itself (as shown at block 402). In an embodiment, initialization of the device driver includes actions such as allocating kernel memory, requesting PCIe driver space, notifying the PCIe device of status, setting up to handle interrupts, and the like. At block 404, the network I/O device driver 140 selects a setup function. From the driver's perspective, this is a step of selecting which piece of initialization code for the function pointer will be used throughout the lifetime of the network I/O device driver, depending on the MAC type. At block 406, the network I/O device driver 140 initializes a function pointer for the network I/O device 110. At block 408, the network I/O device driver 140 initializes a function pointer for the shared code. In an embodiment, blocks 406 and 408 are implemented by initializing a function pointer to the appropriate address of the method implementation. In this step, the network I/O device driver assigns selected physical segments of code specific to the network I/O device 110. This includes, for example, ensuring that the function responsible for setting network I/O device-specific non-volatile memory parameters is initialized (via the function pointer mechanism) to the appropriate memory address. In addition to performing this operation, this step initializes the pointers associated with the shared code; this is necessary for all network I/O devices that implement 1000 megabytes per second (Mb/s) functionality. In an embodiment, block 406 may be considered a superset that incorporates the operations that are completed next in block 408. In one scenario, multiple network I/O devices may use a 1 gigabyte per second (Gb/s) network I/O device driver 140. Thus, the generic function pointer calls are narrowed to the appropriate segment of code specific to that particular HW configuration. In a fruitIn an embodiment, blocks 404, 406, and 408 are considered to be a complete initialization stream (dependent on each other) that has been divided into multiple parts to increase the clarity of the operations performed. At block 410, the network I/O device driver 140 establishes the media type for future communications through the MII 222. The media type indicates information on characteristics of an interface between the PHY and the MAC.

Fig. 5 shows an example flow diagram 500 of a process for establishing a media type. At block 502, if the link mode of the MII222 is not an MDIO-based SGMII, then at block 510 the media type is set to one of a plurality of options depending on the configuration. In most cases, there are small form factor pluggable transceiver (SFP) modules that plug into the computing platform. This means that the network I/O device driver establishes the appropriate media type based on querying the module itself (via inter-integrated circuit (I2C) read transactions). Depending on the type of transceiver, the media type may be initialized to intra _ SERDES, copper, or unknown if an undefined connection is detected that is not supported. Another possibility is in a configuration that includes an SGMII based on I2C. In this case, the same code segment as in SERDES is called, but with some specific changes. The media type is set to copper connections. Within an implementation, the code changes between the two SGMII options, thus ensuring full clarity. The SERDES connection should be considered as a separate link mode.

SGMII provides two options-an internal MDIO and an external MDIO. Embodiments of the present invention use external MDIO. In an embodiment, the link mode is obtained by reading the value from CTRL _ EXT 224. If the link mode is SGMII (which controls the interface over the communication link between the MAC and PHY), processing continues to block 504 where the network I/O device driver 140 enables an inter-integrated circuit (I2C) interface. The I2C interface is opened so that the network I/O device driver 140 can access the external PHY device 220 using the MDIO connection 222 and the MDIO circuitry 218. In an embodiment, this step includes changing the state of CTRL _ EXT in the register memory space (referred to as the programming interface in one embodiment) of the network I/O device at an offset of 0x 0018. This requires querying network I/O device 110 for the current value of the CTRL _ EXT register and setting bit number 25(I2C enabled) to 1. At block 506, the network I/O device driver 140 sets an external destination, which represents accessing the external PHY device 220 using an external media dependent input/output (MDIO) transaction (as opposed to an internal MDIO transaction). In an embodiment, this step includes setting bit number 31 to 1 in MDICNFG register 228 in the network I/O device register memory space. This indicates that the MDIO transaction is to be performed using the MDIC interface and the MDIO transaction is redirected to the external PHY device 220 using the MDIO protocol.

In an embodiment, a query mechanism is implemented within the network I/O device driver to query the MDIC registers for available values of the PHY register Address field and the PHY _ Address field within MDIC nfg registers 228. The MDIC nfg register 228 is responsible for configuring the settings for establishing the correct MDIO connection (which are directly accessed by the MDIC register 226 at the read/write level). This is used to read out the PHY _ ID number used in the device driver initialization process. In OS 150, Linux^TMIn the embodiment of (1), the printk () mechanism is used to print the desired information under "dmesg" to Linux^TMIn the terminal.

The following is example pseudo code for this query mechanism.

In an embodiment, a module parameter is introduced that specifies the PHY _ Address to be used when loading the network I/O device driver. Linux^TMThe MODULE _ PARAM _ DESC macro defined in (1) enables this feature. The arguments specified by the user to load the network I/O device driver module into the OS are then used in the initialization process of the device driver.

Sudo insmod device_driver PHY_Addr＝<specified_PHY_Address>

At block 508, the network I/O device driver 140 sets the media type variable to copper and the SGMII activity variable to true as an act of ending establishing the media type stream. From now on, the network I/O device driver knows that operation with the external PHY device is in SGMII mode through MDIO. Further actions include cooperation between the MAC and PHY or exchange of general information during reception/transmission of data between MAC and PHY devices in the course of network I/O device 110 implementing full link functionality.

Fig. 6 shows an example of a storage medium 600. The storage medium 600 may comprise an article of manufacture. In some examples, storage medium 600 may include any non-transitory computer-readable or machine-readable medium, such as an optical, magnetic, or semiconductor storage device. Storage medium 600 may store various types of computer-executable instructions, such as instructions 602 for implementing logic flow 400 of fig. 4 and logic flow 500 of fig. 5, respectively. Examples of a computer-readable or machine-readable storage medium may include any tangible medium capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. Examples of computer-executable instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, object-oriented code, visual code, and the like. The examples are not limited in this context.

FIG. 7 illustrates an example computing platform 700. In some examples, as shown in fig. 7, computing platform 700 may include a processing component 702, other platform components 704, and/or a communication interface 706. In an embodiment, computing platform 700 is an infotainment system residing in a vehicle (e.g., automobile, truck, motorcycle, etc.), ship, aircraft, or spacecraft.

According to some examples, processing component 702 may execute processing operations or logic directed to instructions stored on storage medium 600. The processing component 702 may include various hardware elements, software elements, or a combination of both. Examples of hardware elements may include devices, logic devices, components, processors, microprocessors, circuits, processor circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, Application Specific Integrated Circuits (ASIC), Programmable Logic Devices (PLD), Digital Signal Processors (DSP), Field Programmable Gate Array (FPGA), memory units, logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. Examples of software elements may include software components, programs, applications, computer programs, application programs, device drivers, system programs, software development programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, Application Program Interfaces (API), instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining example implementation using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints, as desired for a given example.

In some examples, other platform components 704 may include common computing elements, such as one or more processors, multi-core processors, co-processors, memory units, chipsets, controllers, peripherals, interfaces, oscillators, timing devices, video cards, audio cards, multimedia input/output (I/O) components (e.g., digital displays), power supplies, and so forth. Examples of memory units may include, but are not limited to, various types of computer-readable and machine-readable storage media in the form of one or more higher speed memory units, such as Read Only Memory (ROM), Random Access Memory (RAM), dynamic RAM (dram), double data rate dram (ddram), synchronous dram (sdram), static RAM (sram), programmable ROM (prom), erasable programmable ROM (eprom), electrically erasable programmable ROM (eeprom), types of non-volatile memory such as 3-D cross-point memory that may be byte or block addressable. The non-volatile type of memory may also include other types of byte or block addressable non-volatile memory, such as, but not limited to, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level PCM, resistive memory, nanowire memory, FeTRAM, MRAM in conjunction with memristor technology, STT-MRAM, or a combination of any of the above. Other types of computer-readable and machine-readable storage media may also include magnetic or optical cards, arrays of devices such as Redundant Array of Independent Disks (RAID) drives, solid state memory devices (e.g., USB memory), Solid State Drives (SSDs), and any other type of storage media suitable for storing information.

In some examples, the communication interface 706 may include logic and/or features to support a communication interface. For these examples, communication interface 706 may include one or more communication interfaces operating according to various communication protocols or standards to communicate over direct or network communication links or channels. Direct communication may occur via use of communication protocols or standards (e.g., those associated with the PCIe specification) described in one or more industry standards, including progeny and variants. Network communication may occur via use of communication protocols or standards such as those described in one or more of the IEEE published ethernet standards. For example, one such ethernet standard may include IEEE 802.3. Network communications may also occur in accordance with one or more OpenFlow specifications, such as the OpenFlow switch specification.

The components and features of computing platform 700, including the logic represented by the instructions stored on storage medium 600, may be implemented using any combination of discrete circuitry, ASICs, logic gates and/or single-chip architectures. Furthermore, the features of computing platform 700 may be implemented using microcontrollers, programmable logic arrays and/or microprocessors or any combination of the foregoing where suitably appropriate. It should be noted that hardware, firmware, and/or software elements may be collectively or individually referred to herein as "logic" or "circuitry".

It should be appreciated that the exemplary computing platform 700 shown in the block diagram of FIG. 7 may represent one functionally descriptive example of many potential implementations. Thus, division, omission or inclusion of block functions depicted in the accompanying figures does not infer that the hardware components, circuits, software and/or elements for implementing these functions would be divided, omitted, or included in the embodiments.

Various examples may be implemented using hardware elements, software elements, or a combination of both. In some examples, hardware elements may include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, ASICs, Programmable Logic Devices (PLDs), Digital Signal Processors (DSPs), FPGAs, memory units, logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. In some examples, a software element may include a software component, a program, an application, a computer program, an application, a system program, a machine program, operating system software, middleware, firmware, a software module, a routine, a subroutine, a function, a method, a procedure, a software interface, an Application Program Interface (API), an instruction set, computing code, computer code, a code segment, a computer code segment, a word, a value, a symbol, or any combination thereof. Determining example implementation using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints, as desired for a given implementation.

Some examples may include an article of manufacture or at least one computer-readable medium. The computer-readable medium may include a non-transitory storage medium for storing logic. In some examples, a non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. In some examples, logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.

Some examples may be described using the expression "in one example" or "an example" and derivatives thereof. The terms mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one example. The appearances of the phrase "in one example" in various places in the specification are not necessarily all referring to the same example.

Included herein are logical flows or schemes representing example methods for performing novel aspects of the disclosed architecture. While, for purposes of simplicity of explanation, the one or more methodologies shown herein are shown and described as a series of acts, those skilled in the art will understand and appreciate that the methodologies are not limited by the order of acts. Some acts may occur in different orders and/or concurrently with other acts from that shown and described herein. For example, those skilled in the art will understand and appreciate that a methodology could alternatively be represented as a series of interrelated states or events, such as in a state diagram. Moreover, not all acts illustrated in a methodology may be required for a novel implementation.

The logic flows or schemes may be implemented in software, firmware, and/or hardware. In software and firmware embodiments, the logic flows or schemes may be implemented by computer-executable instructions stored on at least one non-transitory computer-readable medium or machine-readable medium (e.g., optical, magnetic, or semiconductor memory devices). The embodiments are not limited in this context.

Some examples are described using the expression "coupled" and "connected" along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, descriptions using the terms "connected" and/or "coupled" may indicate that two or more elements are in direct physical or electrical contact with each other. The term "coupled," however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

It should be emphasized that the abstract of the present disclosure is provided to comply with section 1.72(b) of the 37 c.f.r. requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Additionally, in the foregoing detailed description, it can be seen that various features are grouped together in a single example for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed examples require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed example. Thus the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate example. In the appended claims, the terms "including" and "in which" are used as the plain-english equivalents of the respective terms "comprising" and "in which", respectively. Furthermore, the terms "first," "second," "third," and the like are used merely as labels, and are not intended to impose numerical requirements on their objects.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.