Three-dimensional memory device having support structures located in a slot structure and method for forming the same
阅读说明:本技术 具有位于缝隙结构中的支撑结构的三维存储器件和用于形成其的方法 (Three-dimensional memory device having support structures located in a slot structure and method for forming the same ) 是由 霍宗亮 杨号号 徐伟 严萍 黄攀 周文斌 于 2019-08-23 设计创作,主要内容包括:提供了用于形成三维(3D)存储器件的结构和方法的实施例。在一个示例中,3D存储器件包括堆叠层结构和至少一个源极结构,所述至少一个源极结构在纵向和横向上延伸,并且将所述堆叠层结构划分成多个存储块区域。所述堆叠层结构可以包括被交织在衬底上的多个导体层和多个绝缘层。所述至少一个源极结构包括沿所述纵向方向延伸到所述衬底的至少一个支撑结构,所述至少一个支撑结构与所述相应的源极结构的至少侧壁接触。(Embodiments of structures and methods for forming three-dimensional (3D) memory devices are provided. In one example, a 3D memory device includes a stacked layer structure and at least one source structure extending in longitudinal and lateral directions and dividing the stacked layer structure into a plurality of memory block regions. The stacked layer structure may include a plurality of conductor layers and a plurality of insulation layers interleaved on a substrate. The at least one source structure includes at least one support structure extending to the substrate along the longitudinal direction, the at least one support structure being in contact with at least a sidewall of the respective source structure.)
1. A three-dimensional (3D) memory device, comprising:
a stacked layer structure comprising a plurality of conductor layers and a plurality of insulation layers interleaved on a substrate; and
at least one source structure extending in a longitudinal direction and a lateral direction and dividing the stacked layer structure into a plurality of memory block regions,
wherein the at least one source structure comprises at least one support structure extending to the substrate along the longitudinal direction, the at least one support structure being in contact with at least one adjacent memory block region.
2. The 3D memory device of claim 1, wherein the at least one support structure is each in contact with both adjacent memory block regions.
3. The 3D memory device of claim 2, wherein each of the at least one source structure comprises at least one support structure extending to the substrate along the longitudinal direction.
4. The 3D memory device of claim 3, wherein the sidewalls of the at least one support structure each contact a respective source structure.
5. The 3D memory device of claim 4, wherein a width of each of the at least one support structure is greater than or equal to a width of the source structure in another lateral direction perpendicular to the one lateral direction along which the at least one support structure extends.
6. The 3D memory device of any one of claims 1-5, wherein the at least one support structure comprises at least one of silicon dioxide or polysilicon.
7. The 3D memory device of claim 6, further comprising at least one channel structure in at least one of the plurality of memory block regions extending in the longitudinal direction in the stacked layer structure, wherein the at least one channel structure comprises:
an extension portion in contact with and conductively connected to the substrate, a top surface of the extension portion being located between a top surface and a bottom surface of the bottom insulating layer;
a semiconductor channel in contact with and conductively connected to the epitaxial portion, the semiconductor channel comprising a barrier layer, a storage layer, a tunneling layer, a semiconductor layer, and a dielectric core disposed radially from a sidewall of the semiconductor channel to a center of the semiconductor channel; and
a drain structure in contact with and conductively connected to the semiconductor channel.
8. The 3D memory device of claim 7, further comprising at least one support pillar in the at least one of the plurality of memory block regions extending in the longitudinal direction in the stacked layer structure, wherein the at least one support pillar comprises a same material as the at least one support structure.
9. A method for forming a three-dimensional (3D) memory device, comprising:
forming a dielectric stack layer comprising a plurality of initial insulating layers and a plurality of initial sacrificial layers interleaved on a substrate;
forming at least one slot structure extending in the dielectric stack layer in a longitudinal direction and a lateral direction, the at least one slot structure dividing the dielectric stack layer into a plurality of memory block regions, wherein the at least one slot structure comprises at least one support structure extending to the substrate along the longitudinal direction and contacting at least one adjacent memory block region; and
a source structure is formed in each of the at least one slot structure.
10. The method of claim 9, wherein forming the at least one slot structure comprises:
forming at least one support hole extending in a longitudinal direction in the dielectric stack and into the substrate;
filling the at least one support hole with a support material to form the at least one support structure; and
removing portions of the stacked layered structure to form the at least one slit structure extending in a longitudinal direction, each of the at least one support structure having a width greater than or equal to a width of the respective slit structure in another lateral direction perpendicular to the one lateral direction along which the slit structure extends, a sidewall of the at least one slit structure being in contact with the at least one slit structure.
11. The method of claim 10, wherein forming the source structure comprises:
forming an insulating structure in each of the at least one slot structure, the insulating structure exposing the substrate; and
forming a source contact in the insulating structure, the source contact being in contact with the substrate and conductively connected.
12. The method of claim 10 or 11, further comprising:
forming at least one channel hole in the plurality of memory block regions by the same operation as the forming of the at least one support hole; and
filling the at least one channel hole with a sacrificial material.
13. The method of claim 12, further comprising:
forming at least one post hole by the same operation as the forming of the at least one support hole; and
filling the at least one post hole with the support material by the same operation as filling the at least one support hole.
14. The method of claim 13, further comprising:
removing the sacrificial material in the at least one channel hole to expose the substrate; and
a channel structure is formed in each of the at least one channel hole.
15. The method of claim 9, wherein
Forming the dielectric stack layer includes: forming a first dielectric stack layer and a second dielectric stack layer; and is
Forming the at least one support structure comprises:
forming at least one first support hole extending longitudinally in the first dielectric stack layers and into the substrate prior to forming the second dielectric stack;
filling the at least one first support hole with a sacrificial material;
forming the second dielectric stack layer on the first dielectric stack layer;
forming at least one second support hole extending in the longitudinal direction in the second dielectric stack layer and exposing the sacrificial material in the respective first support hole;
removing the sacrificial material to expose the substrate and form at least one support hole; and
filling the at least one support hole with a support material.
16. The method of claim 15, further comprising:
forming at least one first channel hole in the plurality of memory block regions by the same operation as the formation of the at least one first support hole;
filling the at least one first channel hole with the sacrificial material by the same operation as filling the at least one first support hole;
forming at least one second channel hole extending in the longitudinal direction in the second dielectric stack layer and exposing the sacrificial material in the respective first channel hole; and
filling the at least one second channel hole with another sacrificial material.
17. The method of claim 15 or 16, further comprising:
forming at least one first pillar hole by the same operation as the forming of the at least one first support hole;
filling the at least one first pillar hole with the sacrificial material by the same operation as filling the at least one first support hole;
forming at least one second pillar hole extending in a longitudinal direction in the second dielectric stack layer and exposing the sacrificial material in the respective first pillar hole;
removing the sacrificial material to expose the substrate and form at least one post hole; and
filling the at least one post hole with the support material by the same operation as filling the at least one support hole.
18. The method of claim 17, further comprising:
removing the another sacrificial material in the at least one second channel hole and the sacrificial material in the at least one first channel hole to expose the substrate and form at least one channel hole; and
a channel structure is formed in each of the at least one channel hole.
19. The method of claim 14 or 18, further comprising:
removing the plurality of sacrificial layers in each of the plurality of memory block regions to form a plurality of lateral recesses; and
a plurality of conductor layers are formed in the plurality of lateral recesses.
20. The method of claim 19, wherein forming the source structure comprises:
forming an insulating structure in each of the at least one slot structure; and
forming a source contact in the insulating structure and in contact with the substrate.
21. A method for forming a three-dimensional (3D) memory device, comprising:
forming a dielectric stack layer comprising a plurality of initial insulating layers and a plurality of initial sacrificial layers interleaved on a substrate;
forming at least one support structure in each of a plurality of source regions extending to the substrate along the longitudinal direction;
forming a plurality of slot structures extending in the dielectric stack layer in a longitudinal direction and a lateral direction, the plurality of slot structures dividing the dielectric stack layer into a plurality of memory block regions, wherein the plurality of slot structures include the at least one support structure, and wherein the at least one support structure is in contact with at least one adjacent memory block region; and
a source structure is formed in each of the at least one slot structure.
22. The method of claim 21, wherein forming the at least one support structure and forming the plurality of slot structures comprises:
forming at least one support hole extending in a longitudinal direction in the dielectric stack and into the substrate;
filling the at least one support hole with a support material to form the at least one support structure; and
removing portions of the stacked layer structure to form the at least one slit structure extending in a lateral direction, a width of each of the at least one support structure being greater than or equal to a width of a corresponding slit structure in another lateral direction perpendicular to the one lateral direction along which the slit structure extends, the at least one support structure being in contact with the at least one adjacent memory block region.
23. The method of claim 22, wherein forming the source structure comprises:
forming an insulating structure in each of the at least one slot structure, the insulating structure exposing the substrate; and
forming a source contact in the insulating structure, the source contact being in contact with the substrate and conductively connected.
24. The method of claim 22 or 23, further comprising:
forming at least one channel hole in the plurality of memory block regions by the same operation as the forming of the at least one support hole; and
filling the at least one channel hole with a sacrificial material.
25. The method of claim 24, further comprising:
forming at least one post hole by the same operation as the forming of the at least one support hole; and
filling the at least one post hole with the support material by the same operation as filling the at least one support hole.
26. The method of claim 25, further comprising:
removing the sacrificial material in the at least one channel hole to expose the substrate; and
a channel structure is formed in each of the at least one channel hole.
27. The method of claim 21, wherein
Forming the dielectric stack layer includes: forming a first dielectric stack layer and a second dielectric stack layer; and is
Forming the at least one support structure comprises:
forming at least one first support hole extending longitudinally in the first dielectric stack layers and into the substrate prior to forming the second dielectric stack;
filling the at least one first support hole with a sacrificial material;
forming the second dielectric stack layer on the first dielectric stack layer;
forming at least one second support hole extending in the longitudinal direction in the second dielectric stack layer and exposing the sacrificial material in the corresponding first support hole;
removing the sacrificial material to expose the substrate and form at least one support hole; and
filling the at least one support hole with a support material.
28. The method of claim 27, further comprising:
forming at least one first channel hole in the plurality of memory block regions by the same operation as the formation of the at least one support hole;
filling the at least one first channel hole with the sacrificial material by the same operation as filling the at least one first support hole;
forming at least one second channel hole extending in the longitudinal direction in the second dielectric stack layer and exposing the sacrificial material in the respective first channel hole; and
filling the at least one second channel hole with another sacrificial material.
29. The method of claim 27 or 28, further comprising:
forming at least one first pillar hole by the same operation as the forming of the at least one first support hole;
filling the at least one first pillar hole with the sacrificial material by the same operation as filling the at least one first support hole;
forming at least one second pillar hole extending in a longitudinal direction in the second dielectric stack layer and exposing the sacrificial material in the respective first pillar hole;
removing the sacrificial material to expose the substrate and form at least one post hole; and
filling the at least one post hole with the support material by the same operation as filling the at least one support hole.
30. The method of claim 29, further comprising:
removing the another sacrificial material in the at least one second channel hole and the sacrificial material in the at least one first channel hole to expose the substrate and form at least one channel hole; and
a channel structure is formed in each of the at least one channel hole.
31. The method of claim 26 or 30, further comprising:
removing the plurality of sacrificial layers in each of the plurality of memory block regions to form a plurality of lateral recesses; and
a plurality of conductor layers are formed in the plurality of lateral recesses.
32. The method of claim 31, wherein forming the source structure comprises:
forming an insulating structure in each of the at least one slot structure; and
forming a source contact in the insulating structure and in contact with the substrate.
Technical Field
Embodiments of the present disclosure relate to a three-dimensional (3D) memory device having a support structure located in a gate slit (GLS) and a method for forming the 3D memory device.
Background
Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches a lower limit, planar processes and fabrication techniques become challenging and expensive. Therefore, the storage density of the planar memory cell approaches the upper limit.
The 3D memory architecture can address density limitations in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.
Disclosure of Invention
Embodiments of a 3D memory device and a method for forming the 3D memory device are provided.
In one example, a 3D memory device includes a stacked layer structure and at least one source structure extending in longitudinal and lateral directions and dividing the stacked layer structure into a plurality of memory block regions. The stacked layer structure may include a plurality of conductor layers and a plurality of insulation layers interleaved on a substrate. The at least one source structure includes at least one support structure extending to the substrate along the longitudinal direction, the at least one support structure being in contact with at least a sidewall of the respective source structure.
In another example, a method for forming a 3D memory device includes: forming a dielectric stack layer comprising a plurality of initial insulating layers and a plurality of initial sacrificial layers interleaved on a substrate; forming at least one slot structure extending in the dielectric stack layer in a longitudinal direction and a lateral direction, the at least one slot structure dividing the dielectric stack layer into a plurality of memory block regions, wherein the at least one slot structure comprises at least one support structure extending to the substrate along the longitudinal direction and contacting at least one adjacent memory block region; and forming a source structure in each of the at least one slot structure.
In still another example, a method for forming a 3D memory device includes: forming a dielectric stack layer comprising a plurality of initial insulating layers and a plurality of initial sacrificial layers interleaved on a substrate; forming at least one support structure in each of a plurality of source regions extending to the substrate along the longitudinal direction; forming a plurality of slot structures extending in the dielectric stack layer in a longitudinal direction and a lateral direction, the plurality of slot structures dividing the dielectric stack layer into a plurality of memory block regions, wherein the plurality of slot structures include the at least one support structure, and wherein the at least one support structure is in contact with at least one adjacent memory block region; and forming a source structure in each of the at least one slot structure.
Drawings
The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the pertinent art to make and use the disclosure.
FIG. 1A illustrates a plan view of one exemplary 3D memory device having support structures in a slotted structure, according to some embodiments of the present disclosure.
FIG. 1B illustrates a cross-sectional view of the 3D memory device illustrated in FIG. 1A along the C-D direction, according to some embodiments of the present disclosure.
FIG. 1C illustrates a cross-sectional view of the 3D memory device illustrated in FIG. 1A along the A-B direction, according to some embodiments of the present disclosure.
Fig. 2A illustrates a plan view of an exemplary 3D memory device at one stage of the fabrication process, according to some embodiments of the present disclosure.
FIG. 2B illustrates a cross-sectional view of the 3D memory device illustrated in FIG. 2A along the C-D direction, according to some embodiments of the present disclosure.
FIG. 2C illustrates a cross-sectional view of the 3D memory device illustrated in FIG. 2A along the A-B direction, according to some embodiments of the present disclosure.
Fig. 3A illustrates a plan view of an exemplary 3D memory device at another stage of the fabrication process, according to some embodiments of the present disclosure.
FIG. 3B illustrates a cross-sectional view of the 3D memory device illustrated in FIG. 3A along the C-D direction, according to some embodiments of the present disclosure.
FIG. 3C illustrates a cross-sectional view of the 3D memory device illustrated in FIG. 3A along the A-B direction, according to some embodiments of the present disclosure.
Fig. 4A illustrates a plan view of an exemplary 3D memory device at another stage of the fabrication process, according to some embodiments of the present disclosure.
FIG. 4B illustrates a cross-sectional view of the 3D memory device illustrated in FIG. 4A along the C-D direction, according to some embodiments of the present disclosure.
FIG. 4C illustrates a cross-sectional view of the 3D memory device illustrated in FIG. 4A along the A-B direction, according to some embodiments of the present disclosure.
Fig. 5A illustrates another stage of the fabrication process in a cross-sectional view of the 3D memory device illustrated in fig. 4B, in accordance with some embodiments of the present disclosure.
Fig. 5B illustrates another stage of the fabrication process in a cross-sectional view of the 3D memory device illustrated in fig. 5A, in accordance with some embodiments of the present disclosure.
Fig. 5C illustrates a plan view of an exemplary 3D memory device at another stage of the fabrication process, according to some embodiments of the present disclosure.
FIG. 5D illustrates a cross-sectional view of the 3D memory device illustrated in FIG. 5A along the C-D direction, according to some embodiments of the present disclosure.
Fig. 6 illustrates a plan view of an exemplary 3D memory device at another stage of the fabrication process, according to some embodiments of the present disclosure.
Fig. 7A illustrates a cross-sectional view of the 3D memory device illustrated in fig. 6 along the C-D direction at another stage of the fabrication process, according to some embodiments of the present disclosure.
Fig. 7B illustrates a cross-sectional view of the 3D memory device illustrated in fig. 6 along the a-B direction at another stage of the fabrication process, according to some embodiments of the present disclosure.
Fig. 7C illustrates a plan view of an exemplary 3D memory device at another stage of the fabrication process, according to some embodiments of the present disclosure.
FIG. 7D illustrates a cross-sectional view of the 3D memory device illustrated in FIG. 7C along the C-D direction, in accordance with some embodiments of the present disclosure.
FIG. 7E illustrates a cross-sectional view of the 3D memory device illustrated in FIG. 7C along the A-B direction, according to some embodiments of the present disclosure.
Fig. 8A illustrates a plan view of another exemplary 3D memory device with support structures in the GLS according to some embodiments of the present disclosure.
FIG. 8B illustrates a cross-sectional view of the 3D memory device illustrated in FIG. 8A along the C-D direction, according to some embodiments of the present disclosure.
FIG. 8C illustrates another stage of the fabrication process in a cross-sectional view of the 3D memory device illustrated in FIG. 8A along the A-B direction, in accordance with some embodiments of the present disclosure.
FIG. 8D illustrates another stage of the fabrication process in a cross-sectional view of the 3D memory device illustrated in FIG. 8A along the C-D direction, in accordance with some embodiments of the present disclosure.
FIG. 8E illustrates another stage of the fabrication process in a cross-sectional view of the 3D memory device illustrated in FIG. 8A along the C-D direction, in accordance with some embodiments of the present disclosure.
FIG. 8F illustrates another stage of the fabrication process in a cross-sectional view of the 3D memory device illustrated in FIG. 8A along the C-D direction, in accordance with some embodiments of the present disclosure.
Fig. 9 illustrates an enlarged view of one exemplary support structure according to some embodiments of the present disclosure.
Fig. 10A illustrates a flow diagram of an exemplary fabrication process for forming a 3D memory device having support structures in a slotted structure, according to some embodiments of the present disclosure.
Fig. 10B illustrates a flow diagram of another exemplary fabrication process for forming a 3D memory device having support structures in a slotted structure, according to some embodiments of the present disclosure.
Embodiments of the present disclosure will be described with reference to the accompanying drawings.
Detailed Description
While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the relevant art will recognize that other configurations and arrangements can be used without parting from the spirit and scope of the disclosure. It should be apparent to those skilled in the relevant art that the present disclosure may also be used in many other applications.
It should be noted that references in this specification to "one embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it will be understood by those skilled in the relevant art that such feature, structure, or characteristic is capable of being implemented in connection with other embodiments whether or not explicitly described.
In general terms may be understood at least in part from the context in which they are used. For example, the term "one or more" as used herein may be used to describe a feature, structure, or characteristic in any singular sense, or may be used to describe a combination of features, structures, or characteristics in plural senses, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" again may be understood to convey a singular use or to convey a plural use, depending at least in part on the context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, again depending at least in part on context, but may instead allow for the presence of additional factors not necessarily explicitly described.
As used herein, the term "nominal" refers to a desired or target value of a characteristic or parameter for the operation of a component or process, and a range of values above and/or below the desired value, set during a design phase of the product or process. The range of values may be due to small variations or tolerances in the manufacturing process. As used herein, the term "about" indicates a given amount of value that may vary based on the particular technology node associated with the subject semiconductor device. The term "about" may indicate a value of a given amount that varies, for example, within 10-30% of the value (e.g., ± 10%, ± 20% or ± 30% of the value), based on the particular technology node.
As used herein, a stair-step structure refers to a collection of surfaces that includes at least two lateral surfaces (e.g., along an x-y plane) and at least two (e.g., first and second) longitudinal surfaces (e.g., along a z-axis) such that each lateral surface is contiguous with a first longitudinal surface extending upward from a first edge of the lateral surface and contiguous with a second longitudinal surface extending downward from a second edge of the lateral surface. "step" or "step" refers to a longitudinal shift in the height of a collection of abutting surfaces. In the present disclosure, the term "step" and the term "step" refer to a stage of a stepped structure and are used interchangeably. In the present disclosure, a lateral direction may refer to a direction (e.g., x-axis or y-axis) parallel to a top surface of a substrate (e.g., a substrate that provides a fabrication platform for forming structures thereon), and a longitudinal direction may refer to a direction (e.g., z-axis) perpendicular to the top surface of the structures.
NAND flash memory devices, which are widely used in various electronic products, are nonvolatile, lightweight memory devices having low power consumption and good performance. Currently, planar NAND flash memory devices have reached their storage limits. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory device has been proposed. A process for forming an existing 3D NAND memory device generally includes the following operations. First, a stacked layer structure having a plurality of interleaved sacrificial layers and insulating layers is formed on a substrate. Channel holes are formed extending in the stacked layer structure. The bottom of the channel hole is etched to form a recess in the substrate. An epitaxial portion is formed at the bottom of the channel hole by selective epitaxial growth. A semiconductor channel conductively connected to the epitaxial portion is formed in the channel hole. The sacrificial layer may be removed and replaced with a conductor layer. The conductor layer serves as a word line in the 3D NAND memory device.
Existing 3D NAND memory devices typically include a plurality of memory blocks. Adjacent memory blocks are typically separated by a gate slit (GLS) where the Array Common Source (ACS) is formed. In a manufacturing method for forming an existing 3D NAND memory device, the characteristic size of the GLS is susceptible to fluctuations, potentially affecting the performance of the 3D NAND memory device.
The present disclosure provides a 3D memory device (e.g., a 3D nand memory device) having a support structure in a slot structure (e.g., a GLS) and a method for forming the 3D memory device. The 3D memory device uses one or more support structures in contact with at least the sidewalls of the slot structures. For example, the width of the support structure is equal to or greater than the width of the slot structure. Thus, the support structure provides support for the entire structure during 3D storage during formation of the conductor layer/portion and the source contact. The 3D memory device is therefore less susceptible to deformation or damage during the manufacturing process. In some embodiments, the support structure is filled with an insulating material (such as silicon dioxide or polysilicon) comprising a different material than the sacrificial layer, such that the support structure is little or no damage during the gate replacement process in which the sacrificial layer is etched away. By applying the structure and method of the present disclosure, adjacent memory blocks are in contact with each other through the support structure during formation of the slit structure and the source contact, and the 3D memory device is therefore less likely to be deformed during the manufacturing process. The characteristic size of the slot structure is less susceptible to fluctuations.
FIG. 1A illustrates a plan view of an exemplary 3D memory device 150, according to some embodiments. FIG. 1B illustrates a cross-sectional view of the 3D memory device 150 shown in FIG. 1A along the direction C-D. FIG. 1C illustrates a cross-sectional view of the 3D memory device 150 shown in FIG. 1A along the A-B direction. As shown in fig. 1A, the 3D memory device 150 may be divided into a core region and a staircase region (not shown), for example, in the y-direction. Channel structures and support pillars may be formed in the core region. A step and an electrical connection between the conductor layer and an external circuit (e.g., a contact plug) may be formed in the step region. The core region may include one or
As shown in fig. 1A-1C, the 3D memory device 150 may include a
A source structure may be formed in the
The
As shown in fig. 1B, the
In some embodiments, the
In some embodiments, the
As shown in fig. 1A, the
In some embodiments, the source structure includes
At least one
As shown in fig. 1A-1C, the plurality of
In some embodiments, the
The width of
The 3D memory device 150 may be part of a monolithic 3D memory device. The term "monolithic" means that elements (e.g., peripheral devices and memory array devices) of a 3D memory device are formed on a single substrate. For monolithic 3D memory devices, manufacturing suffers from additional limitations due to the wrap-around of peripheral device processing and memory array device processing. For example, the fabrication of memory array devices (e.g., NAND channel structures) is limited by the thermal budget associated with peripheral devices that have been or will be formed on the same substrate.
Alternatively, the 3D memory device 150 may be part of a non-monolithic 3D memory device, in which elements (e.g., a peripheral device and a memory array device) may be separately formed on different substrates and then bonded, for example, in a face-to-face manner. In some embodiments, the memory array device substrate (e.g., substrate 100) remains as the substrate of the bonded non-monolithic 3D memory device, and the peripheral devices (e.g., including any suitable digital, analog, and/or mixed signal peripheral circuits such as page buffers, decoders, and latches; not shown) that are used to facilitate operation of the 3D memory device 150 are flipped and face down the memory array device (e.g., NAND memory string) for hybrid bonding. It should be understood that in some embodiments, the memory array device substrate (e.g., substrate 100) is flipped and faced toward a peripheral device (not shown) for hybrid bonding such that in a bonded non-monolithic 3D memory device, the memory array device is located over the peripheral device. The memory array device substrate (e.g., substrate 100) may be a thinned substrate (which is not a substrate of a bonded non-monolithic 3D memory device) and back end of line (BEOL) interconnects of the non-monolithic 3D memory device may be formed on a backside of the thinned memory array device substrate.
Fig. 2-7 illustrate a fabrication process for forming the 3D memory device 150 shown in fig. 1A-1C. Fig. 10A is a flow chart of the method 1000 illustrated in fig. 2-7. For ease of illustration, identical or similar parts are labeled with the same reference numerals as in fig. 1-7 of the present disclosure.
At the start of the process, a stacked layer structure is formed with a plurality of initial insulating layers and a plurality of initial sacrificial layers interleaved (operation 1002). Fig. 2A-2C illustrate a corresponding structure 200.
As shown in fig. 2A-2C, a
The stacked
The insulating material layer and the sacrificial material layer may have different etch selectivity during a subsequent gate replacement process. In some embodiments, the layer of insulating material and the layer of sacrificial material comprise different materials. In some embodiments, the layer of insulating material comprises silicon dioxide, and the deposition of the layer of insulating material comprises one or more of Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), and sputtering. In some embodiments, the sacrificial material layer comprises silicon nitride and the deposition of the insulating material layer comprises one or more of CVD, PVD, ALD, and sputtering. In some embodiments, the etching of the layers of sacrificial material and insulating material includes one or more suitable anisotropic etching processes (e.g., dry etching).
Referring back to fig. 10A, at least one support hole, at least one channel hole, and at least one post hole are formed. In some embodiments, the at least one channel hole and the at least one post hole are formed by the same operation as the at least one support hole is formed (operation 1004). Fig. 3A-3C illustrate a
In some embodiments, at least one
At least one
Referring back to fig. 10A, a
Referring back to fig. 10A, support structures and support posts are formed in the support holes and post holes, respectively (operation 1008). The support structures and support posts may be formed by depositing support material into the support holes and post holes, respectively. Fig. 4A-4C illustrate a
Referring back to fig. 10A, the sacrificial material in the channel hole is removed and a channel structure is formed in the at least one channel hole (operation 1010). Fig. 5A-5D illustrate a
In some embodiments,
In some embodiments, a
In some embodiments, a
In some embodiments, operations 1008 and 1010 may be performed in a different order. For example, operation 1010 may be performed before operation 1008. For example, the channel structure in each of the at least one channel hole may be formed prior to forming the support structure and the support posts. For example, at 1006, a sacrificial structure may be formed in each of the at least one
Referring back to fig. 10A, a portion of the stacked layer structure in the source region may be removed to form at least one slit structure extending in the lateral and longitudinal directions (operation 1012). Fig. 6 illustrates a
Referring back to fig. 10A, a source structure is formed in each of the slit structures, and a plurality of conductor layers and a plurality of memory blocks are formed (operation 1014). Fig. 7A-7E illustrate a
In some embodiments, the initial sacrificial layers (e.g., 103i, 106i, and 145i) in the
The conductor material may include one or more of tungsten, aluminum, copper, cobalt, silicide, and polysilicon. A suitable isotropic etch process (e.g., a wet etch) may be performed to remove the sacrificial layer and sacrificial portion and form a plurality of lateral recesses. A suitable deposition process, such as CVD, PVD, ALD, and/or sputtering, may be performed to deposit a conductive material into the lateral recesses to form a conductive layer (e.g., 131-.
As shown in fig. 7C-7E, an insulating
Figures 8A-8F illustrate another
At the start of the process, a first
At operation 1054, at least one
At an operation 1056, a
At operation 1058, a second
At operation 1060, at least one
At operation 1062, a
The sacrificial material in the at least one
At operation 1064,
At operation 1066, in an operation similar to operations 1012 and 1014, at least one slot structure, a source structure in each of the at least one slot structure, a plurality of conductor layers, and a plurality of memory blocks are formed.
In some embodiments, a 3D memory device includes a stacked layer structure and at least one source structure extending in longitudinal and lateral directions and dividing the stacked layer structure into a plurality of memory block regions. The stacked layered structure may include a plurality of conductor layers and a plurality of insulation layers interleaved on the substrate. The at least one source structure includes at least one support structure extending to the substrate along the longitudinal direction, the at least one support structure being in contact with at least a sidewall of the respective source structure.
In some embodiments, the at least one support structure is each in contact with both adjacent memory block regions.
In some embodiments, each of the at least one source structure comprises at least one support structure extending to the substrate along the longitudinal direction.
In some embodiments, the sidewalls of the at least one support structure each contact a respective source structure.
In some embodiments, a width of each of the at least one support structure in another lateral direction perpendicular to the one lateral direction along which the at least one support structure extends is greater than or equal to a width of the source structure.
In some embodiments, the at least one support structure comprises at least one of silicon dioxide or polysilicon.
In some embodiments, the 3D memory device further includes at least one channel structure extending in a stacked layer structure in a longitudinal direction in at least one of the plurality of memory block regions, wherein the at least one channel structure includes an epitaxial portion, a semiconductor channel, and a drain structure. The epitaxial portion is in contact with and conductively connected to the substrate, and a top surface of the epitaxial portion is located between the top surface and the bottom surface of the bottom insulating layer. A semiconductor channel is in contact with and conductively connected to the epitaxial portion, the semiconductor channel including a barrier layer, a storage layer, a tunneling layer, a semiconductor layer, and a dielectric core disposed radially from a sidewall of the semiconductor channel to a center of the semiconductor channel. The drain structure is in contact with the semiconductor channel and is conductively connected.
In some embodiments, the 3D memory device further includes at least one support pillar extending in a stacked layer structure in a longitudinal direction in at least one of the plurality of memory block regions, wherein the at least one support pillar comprises the same material as the at least one support structure.
In some embodiments, a method for forming a 3D memory device includes: forming a dielectric stack layer comprising a plurality of initial insulating layers and a plurality of initial sacrificial layers interleaved on a substrate; forming at least one slot structure extending in the dielectric stack layer in a longitudinal direction and a lateral direction, the at least one slot structure dividing the dielectric stack layer into a plurality of memory block regions, wherein the at least one slot structure comprises at least one support structure extending to the substrate in the longitudinal direction and contacting at least one adjacent memory block region; and forming a source structure in each of the at least one slot structure.
In some embodiments, forming the at least one slit structure comprises: forming at least one support hole extending in the longitudinal direction in the dielectric stack and into the substrate; filling the at least one support hole with a support material to form at least one support structure; and removing portions of the stacked layer structure to form at least one slit structure extending in a lateral direction, each of the at least one support structure having a width greater than or equal to a width of the corresponding slit structure in another lateral direction perpendicular to the one lateral direction along which the slit structure extends, a sidewall of the at least one slit structure being in contact with the at least one slit structure.
In some embodiments, forming the source structure comprises: forming an insulating structure in each of the at least one slot structure, the insulating structure exposing the substrate; and forming a source contact in the insulating structure, the source contact being in contact with the substrate and conductively connected.
In some embodiments, the method for forming 3D further comprises: forming at least one channel hole in the plurality of memory block regions by the same operation as the forming of the at least one support hole; and filling the at least one channel hole with a sacrificial material.
In some embodiments, the method for forming 3D further comprises: forming at least one post hole by the same operation as the forming of the at least one support hole; and filling the at least one pillar hole with a support material by the same operation as the filling of the at least one support hole.
In some embodiments, the method for forming 3D further comprises: forming the dielectric stack layer includes forming a first dielectric stack layer and a second dielectric stack layer; and forming at least one support structure. Forming at least one support structure further comprises: forming at least one first support hole extending in a longitudinal direction in the first dielectric stack layer and into the substrate before forming the second dielectric stack; filling the at least one first support hole with a sacrificial material; forming a second dielectric stack layer on the first dielectric stack layer; forming at least one second support hole extending in the longitudinal direction in the second dielectric stack layer and exposing the sacrificial material in the corresponding first support hole; removing the sacrificial material to expose the substrate and form at least one support hole; and filling the at least one support hole with a support material.
In some embodiments, the method for forming 3D further comprises: forming at least one first channel hole in the plurality of memory block regions by the same operation as the formation of the at least one first support hole; filling the at least one first channel hole with a sacrificial material by the same operation as filling the at least one first support hole; forming at least one second channel hole extending in the longitudinal direction in the second dielectric stack layer and exposing the sacrificial material in the respective first channel hole; and filling the at least one second channel hole with another sacrificial material.
In some embodiments, the method for forming 3D further comprises: forming at least one first pillar hole by the same operation as forming at least one first support hole; filling the at least one first pillar hole with a sacrificial material by the same operation as filling the at least one first support hole; forming at least one second pillar hole extending in a longitudinal direction in the second dielectric stack layer and exposing the sacrificial material in the respective first pillar hole; removing the sacrificial material to expose the substrate and form at least one post hole; and filling the at least one post hole with a support material by the same operation as filling the at least one support hole.
In some embodiments, the method for forming 3D further comprises: removing the another sacrificial material in the at least one second channel hole and the sacrificial material in the at least one first channel hole to expose the substrate and form at least one channel hole; and forming a channel structure in each of the at least one channel hole.
In some embodiments, the method for forming 3D further comprises: removing the plurality of sacrificial layers in each of the plurality of memory block regions to form a plurality of lateral recesses; and forming a plurality of conductor layers in the plurality of lateral recesses.
In some embodiments, forming the source structure further comprises: forming an insulating structure in each of the at least one slot structure; and forming a source contact in the insulating structure and in contact with the substrate.
In some embodiments, a method for forming a 3D memory device includes: forming a dielectric stack layer comprising a plurality of initial insulating layers and a plurality of initial sacrificial layers interleaved on a substrate; forming at least one support structure in each of the plurality of source regions extending to the substrate in a longitudinal direction; forming a plurality of slot structures extending in the dielectric stack layer in a longitudinal direction and a lateral direction, the plurality of slot structures dividing the dielectric stack layer into a plurality of memory block regions, wherein the plurality of slot structures include the at least one support structure, and wherein the at least one support structure is in contact with at least one adjacent memory block region; and forming a source structure in each of the at least one slot structure.
In some embodiments, forming at least one support structure and forming a plurality of slot structures further comprises: forming at least one support hole extending in the longitudinal direction in the dielectric stack and into the substrate; filling the at least one support hole with a support material to form the at least one support structure; and removing portions of the stacked layer structure to form the at least one slit structure extending in a lateral direction, a width of each of the at least one support structure being greater than or equal to a width of a corresponding slit structure in another lateral direction perpendicular to the one lateral direction along which the slit structure extends, the at least one support structure being in contact with the at least one adjacent memory block region.
In some embodiments, the method for forming a 3D memory device further includes: forming an insulating structure in each of the at least one slot structure, the insulating structure exposing the substrate; and forming a source contact in the insulating structure, the source contact being in contact with the substrate and conductively connected.
In some embodiments, the method for forming a 3D memory device further includes: forming at least one channel hole in the plurality of memory block regions by the same operation as the forming of the at least one support hole; and filling the at least one channel hole with a sacrificial material.
In some embodiments, the method for forming a 3D memory device further includes: forming at least one post hole by the same operation as the forming of the at least one support hole; and filling the at least one pillar hole with a support material by the same operation as the filling of the at least one support hole.
In some embodiments, the method for forming a 3D memory device further includes: removing the sacrificial material in the at least one channel hole to expose the substrate; and forming a channel structure in each of the at least one channel hole.
In some embodiments, the method for forming a 3D memory device further includes: forming the dielectric stack layer includes forming a first dielectric stack layer and a second dielectric stack layer; and forming at least one support structure. Forming at least one support structure further comprises: forming at least one first support hole extending in a longitudinal direction in the first dielectric stack layer and into the substrate before forming the second dielectric stack; filling the at least one first support hole with a sacrificial material; forming a second dielectric stack layer on the first dielectric stack layer; forming at least one second support hole extending in the longitudinal direction in the second dielectric stack layer and exposing the sacrificial material in the corresponding first support hole; removing the sacrificial material to expose the substrate and form at least one support hole; and filling the at least one support hole with a support material.
In some embodiments, the method for forming a 3D memory device further includes: forming at least one first channel hole in the plurality of memory block regions by the same operation as the formation of the at least one first support hole; filling the at least one first channel hole with a sacrificial material by the same operation as filling the at least one first support hole; forming at least one second channel hole extending in the longitudinal direction in the second dielectric stack layer and exposing the sacrificial material in the respective first channel hole; and filling the at least one second channel hole with another sacrificial material.
In some embodiments, the method for forming a 3D memory device further includes: forming at least one first pillar hole by the same operation as forming at least one first support hole; filling the at least one first pillar hole with a sacrificial material by the same operation as filling the at least one first support hole; forming at least one second pillar hole extending in a longitudinal direction in the second dielectric stack layer and exposing the sacrificial material in the respective first pillar hole; removing the sacrificial material to expose the substrate and form at least one post hole; and filling the at least one post hole with a support material by the same operation as filling the at least one support hole.
In some embodiments, the method for forming a 3D memory device further includes: removing the another sacrificial material in the at least one second channel hole and the sacrificial material in the at least one first channel hole to expose the substrate and form at least one channel hole; and forming a channel structure in each of the at least one channel hole.
In some embodiments, the method for forming a 3D memory device further includes: removing the plurality of sacrificial layers in each of the plurality of memory block regions to form a plurality of lateral recesses; and forming a plurality of conductor layers in the plurality of lateral recesses.
In some embodiments, the method for forming a 3D memory device further includes: forming an insulating structure in each of the at least one slot structure; and forming a source contact in the insulating structure and in contact with the substrate.
The foregoing description of the specific embodiments will so reveal the general nature of the disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents based on the teachings and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.
Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. For convenience of description, the boundaries of these functional component blocks have been arbitrarily defined herein. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.
The abstract section may set forth one or more, but not all exemplary embodiments of the disclosure as contemplated by the inventors, and is therefore not intended to limit the disclosure and the appended claims in any way.
The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
- 上一篇:一种医用注射器针头装配设备
- 下一篇:三维存储器件及其制作方法