阅读说明：本技术 抗老化装置 (Anti-aging device ) 是由 K·恩斯 D·内达尔格 V·德什潘德 L·海斯 A·K·斯里瓦斯塔瓦 于 2018-06-14 设计创作，主要内容包括：提供了一种装置,该装置包括：相同导电类型的晶体管的堆叠,该堆叠包括第一晶体管和第二晶体管,第一晶体管和第二晶体管串联耦合并具有公共节点；和相同导电类型的反馈晶体管,耦合到该公共节点和该堆叠中的第一晶体管的栅极端子。(There is provided an apparatus comprising: a stack of transistors of a same conductivity type, the stack comprising a first transistor and a second transistor, the first and second transistors being coupled in series and having a common node; and a feedback transistor of the same conductivity type coupled to the common node and to a gate terminal of the first transistor in the stack.)

1. An apparatus, comprising:

a stack of transistors of a same conductivity type, the stack comprising a first transistor and a second transistor, the first and second transistors coupled in series and having a common node; and

feedback transistors of a same conductivity type coupled to the common node and a gate terminal of a first transistor in the stack.

2. The apparatus of claim 1, wherein the feedback transistor comprises a gate terminal coupled to a first transistor in the stack.

3. The apparatus of any preceding claim, wherein the gate terminal of the first transistor and the gate terminal of the second transistor are controllable by two separate control nodes.

4. The apparatus of any preceding claim, wherein the feedback transistor is smaller in size than one of the first transistor or the second transistor.

5. An apparatus, comprising:

a NAND gate; and

a feedback transistor coupled to the two n-type transistors of the NAND gate and the two p-type transistors of the NAND gate.

6. The apparatus of claim 5, wherein a gate terminal of the feedback transistor is coupled to drain terminals of two p-type transistors of the NAND gate.

7. The apparatus of claim 5, wherein the feedback transistor is coupled to a gate terminal of one of the two n-type transistors.

8. The apparatus of claim 5, wherein the feedback transistor is an n-type transistor.

9. The apparatus of any of claims 5-8, wherein a gate terminal of the feedback transistor is coupled to an output of the NAND gate.

10. The apparatus of any of claims 5-9, wherein the feedback transistor is smaller in size than one of the two n-type transistors.

11. An apparatus, comprising:

a NOR gate; and

a feedback transistor coupled to the two n-type transistors of the NOR gate and the two p-type transistors of the NOR gate.

12. The apparatus of claim 11, wherein a gate terminal of the feedback transistor is coupled to drain terminals of two n-type transistors of the NOR gate.

13. The apparatus of claim 11, wherein the feedback transistor is coupled to a gate terminal of one of the two p-type transistors.

14. The apparatus of claim 11, wherein the feedback transistor is a p-type transistor.

15. The apparatus of any of claims 11-15, wherein a gate terminal of the feedback transistor is coupled to an output of the NOR gate.

16. The apparatus of any of claims 11-15, wherein the feedback transistor is smaller in size than one of the two p-type transistors.

17. A system, comprising:

a memory;

a processor coupled to the memory, the processor comprising the apparatus of any of claims 1-4; and

a wireless interface to allow the processor to communicate with another device.

18. A system, comprising:

a memory;

a processor coupled to the memory, the processor comprising the apparatus of any of claims 5-10; and

a wireless interface to allow the processor to communicate with another device.

19. A system, comprising:

a memory;

a processor coupled to the memory, the processor comprising the apparatus of any of claims 11-16; and

a wireless interface to allow the processor to communicate with another device.

20. An apparatus, comprising:

means for clamping a high impedance node in a transistor stack to a fixed voltage.

21. The apparatus of claim 20, comprising means for controlling transistors in the stack through two separate control nodes.

22. The apparatus of claim 20, wherein a size of the means for clamping is smaller than one of the transistors in the stack.

23. A method, comprising:

the high impedance node in the transistor stack is clamped to a fixed voltage.

24. The method of claim 23, comprising:

the transistors in the stack are controlled by two separate control nodes.

25. The method of claim 23, wherein a size of a transistor used for clamping is smaller than one of the transistors in the stack.

Background

Complementary Metal Oxide Semiconductor (CMOS) transistors developed in FinFET (fin field effect transistor) technology typically suffer from enhanced aging degradation compared to transistors developed in planar technology. Digital circuit performance degrades with aging in two ways: (1) functional degradation due to the aging circuit stopping working or significantly degrading during the lifetime (lifetime); and (2) device failure, due to excessive aging triggering irreversible dielectric breakdown of the transistor, resulting in transient failure of the corresponding circuit. Since aging is exponential with voltage, digital circuits age in the event that the transistors are exposed to voltages that exceed the operational limits of the CMOS device. One of the digital circuit topologies where the internal nodes are exposed to voltages exceeding the device target limits is a stacked transistor configuration.

Drawings

Embodiments of the present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

Fig. 1A shows a stacked circuit configuration.

FIG. 1B shows the stacked circuit configuration when a transistor in the stack is off, which may cause the transistor to over age and fail.

Fig. 2 illustrates a stacked circuit configuration with aging resistance devices according to some embodiments of the present disclosure.

Fig. 3 illustrates an "N" stacked circuit configuration with aging resistance devices according to some embodiments of the present disclosure.

FIG. 4A shows a NAND logic gate circuit that suffers from aging failures.

Fig. 4B illustrates a NAND logic gate circuit with an aging resistance device, according to some embodiments of the present disclosure.

Figure 5 shows a set of graphs comparing the transient behavior of the NAND logic gate circuit of figures 4A-B, in accordance with some embodiments of the present disclosure.

Figure 6 shows a set of graphs comparing the transient behavior of the NAND logic gate circuit of figures 4A-B over a number of years, in accordance with some embodiments of the present disclosure.

FIG. 7 illustrates a graph showing Ring Oscillator (RO) frequency degradation versus lifetime, in accordance with some embodiments.

Fig. 8 shows a graph illustrating drive current degradation of the transistor MN2 of fig. 1A and 2, in accordance with some embodiments.

Fig. 9 illustrates an aging resistant NOR logic gate circuit according to some embodiments of the present disclosure.

FIG. 10 illustrates an anti-aging selection circuit according to some embodiments of the present disclosure.

Fig. 11 illustrates an anti-aging multiplexer circuit, according to some embodiments of the present disclosure.

Fig. 12 illustrates a smart device or computer system or SoC (system on a chip) having an anti-aging apparatus, according to some embodiments of the present disclosure.

Detailed Description

Some embodiments describe an anti-aging circuit that clamps a high impedance node to a well-defined fixed voltage. Some embodiments use aging resistant circuit techniques for "N" stacked transistors, and the techniques are also applicable to all digital circuits using stacked N-type and p-type devices. Some embodiments ensure that in the event that a signal at an intermediate node in a transistor stack is affected by noise and/or coupling, an alternative charge/discharge path exists to clamp the voltage on that node to a specified voltage.

There are many technical effects of the various embodiments. For example, the aging resistance circuit or apparatus of some embodiments prevents the device operating voltage from exceeding the voltage specified by the process of stacking n-type and/or p-type transistor configurations by clamping all affected internal nodes to a specified voltage level. The aging resistant circuit or device of some embodiments avoids excessive degradation of transistors, digital circuits, and circuit failures. In some embodiments, for a Ring Oscillator (RO) circuit using a stack of transistors, the frequency degradation with the anti-aging circuit may be much lower than the frequency degradation without the anti-aging circuit.

For example, the frequency degradation of the RO without the anti-aging circuit may be 45% in 10 years, and 14% in 10 years with the anti-aging circuit. In another example, the drive current reduction for RO may be much lower than without the anti-aging circuit. For example, for a stacked RO, the drive current reduction after 10 years may be 80% without using an anti-aging circuit, while for the same period, with an anti-aging circuit, the drive current reduction is 28%. Other technical effects will be apparent from the various embodiments and drawings.

In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

Note that in the corresponding drawings of the embodiments, signals are represented by lines. Some lines may be thicker to indicate more constituent signal paths and/or have arrows at one or more ends to indicate primary information flow. Such indication is not intended to be limiting. Rather, these lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or logic unit. Any represented signal may actually comprise one or more signals that may propagate in either direction and may be implemented with any suitable type of signal scheme, as dictated by design needs or preferences.

Throughout the specification and in the claims, the term "connected" means directly connected, such as electrically, mechanically or magnetically, between the connected objects, without any intervening devices. The term "coupled" refers to a direct connection or an indirect connection, such as a direct electrical, mechanical, or magnetic connection between the connected objects, or an indirect connection through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components arranged to cooperate with each other to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a", "an" and "the" includes plural forms. The meaning of "in.

The term "scaling" generally refers to the conversion of a design (schematic and layout) from one process technology to another, followed by a reduction in layout area. The term "scaling" also generally refers to shrinking layouts and devices within the same technology node. The term "scaling" may also refer to adjusting (e.g., slowing down or speeding up, i.e., zooming in or out, respectively) the signal frequency relative to another parameter (e.g., the power supply level). The terms "substantially", "close", "approximately", "close" and "approximately" generally refer to being within +/-10% of a target value.

Unless otherwise specified the use of the ordinal adjectives "first", "second", and "third", etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

For the purposes of this disclosure, the phrases "a and/or B" and "a or B" mean (a), (B), or (a and B). For the purposes of this disclosure, the phrase "A, B and/or C" refers to (a), (B), (C), (a and B), (a and C), (B and C), or (A, B and C).

The terms "left," "right," "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes only and not necessarily for describing permanent relative positions. For the purposes of this disclosure, the terms "spin" and "magnetic moment" are used equivalently. More strictly speaking, the direction of the spin is opposite to the direction of the magnetic moment, and the charge of the particle is negative (for example, in the case of electrons).

For purposes of the embodiments, the transistors in the various circuits and logic blocks described herein are Metal Oxide Semiconductor (MOS) transistors or derivatives thereof, where MOS transistors include a drain terminal, a source terminal, a gate terminal, and a bulk terminal. The transistors and/or MOS transistor derivatives further include Tri-Gate (Tri-Gate) and FinFET transistors, all-around Gate cylindrical transistors, tunnel fet (tfet), square wire or rectangular ribbon transistors, ferroelectric fet (fefet), or other devices that perform a transistor function, such as carbon nanotubes or spintronic devices. The symmetrical source and drain terminals of the MOSFET are the same terminal and may be used interchangeably herein. TFET devices, on the other hand, have asymmetric source and drain terminals. Those skilled in the art will appreciate that other transistors may be used, such as bipolar junction transistors (BJTs PNP/NPN), BiCMOS, CMOS, etc., without departing from the scope of the present disclosure.

Since aging is exponential with voltage, digital circuits age in the event that the transistors are exposed to voltages that exceed the operational limits of the CMOS device. One of the digital circuit topologies where the internal nodes are exposed to voltages exceeding the device target limits is a stacked transistor configuration.

Fig. 1A shows a stacked circuit configuration 100. The configuration 100 is widely used for circuits such as logic circuits, I/O (input/output) interfaces, DC-DC converters, power amplifiers, and the like. The stacked circuit configuration 100 includes two stacked n-type transistors, referred to as transistors MN1 and MN 2. Here, the n-type transistors are shown in a stacked configuration, however, the problem of aging also applies to stacked p-type transistors. To avoid excessive aging of the device, a voltage is applied between the two transistor terminals (e.g. gates)And source or drain and source) is limited to a maximum voltage V_max. In general, V_max＝1.1V_DD,nomIs used as a restriction, wherein V_DD,nomIs the nominal supply voltage of the corresponding device.

Fig. 1B shows the stacked circuit configuration 120 when a transistor in the stack is off, which may cause the transistor to over age and fail. During the design of the stack topology, special attention is paid to the drain-source voltage V of the upper transistor MN2_DS,2. When the transistor MN2 is turned off, for example, when the gate-source voltage V of the transistor MN2_GS,2Less than or equal to threshold voltage V of transistor MN2_th(e.g., V)_GS,2＜V_th) When, since node "Y" is a high impedance node (e.g., a floating node) susceptible to any coupling or noise, V_DS,2Will become higher than V_max(e.g., V)_DS,2>V_max). Here, the term "V_max"is the following voltage: if a voltage higher than this voltage is applied for a certain time, the transistor of the process node is damaged. Excessive voltages that exceed operating limits can cause device degradation due to aging, thereby causing transistor MN2 to fail and possibly limit circuit function.

As FinFET geometries shrink to 14nm or 10nm or 7nm, device geometries are more susceptible to aging than planar transistors. Even a moderate operating voltage, which exceeds the operating voltage specified by the process node, can cause the standard circuit topology to fail. Similar problems may exist for some external small geometry processes, whether planar or silicon-on-insulator (SOI) technologies. One solution to overcome the aging is to reduce the supply voltage to provide more operating voltage margin. However, lowering the supply voltage limits circuit operation and limits circuit drive capability, resulting in timing violations on an Integrated Circuit (IC) chip. Various embodiments provide an aging resistant circuit technique that mitigates aging on smaller process geometries.

Fig. 2 illustrates a stacked circuit configuration 200 with aging resistance devices according to some embodiments of the present disclosure. To be notedThose elements of fig. 2 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Here, the stacked circuit configuration 200 includes a first n-type transistor MN2 coupled in series with a second n-type transistor MN1 such that node "Y" is a common node. In some embodiments, the anti-aging means comprises a feedback transistor MNfb of the same conductivity type (e.g., n-type) coupled to the common node "Y" and the gate terminal of the stacked first transistor MN 2. In some embodiments, the gate terminal of the feedback transistor MNfb is coupled to the first transistor MN2 of the stack. In some embodiments, the gate terminal of the first transistor MN2 and the gate terminal of the second transistor MN2 may be controlled by two separate control nodes "G₂"and" G₁And respectively controlling. In some embodiments, the feedback transistor MNfb is smaller in size than one of the first transistor or the second transistor. For example, the width of the feedback transistor MNfb is 75% of the width of the first transistor MN2 or the second transistor MN 2. In some embodiments, the size of the feedback transistor may also be larger than the size of the stacked transistor.

In some embodiments, the aging resistance circuit maintains internal nodes of the stacked circuit topology within a specified operating voltage range. In some embodiments, feedback transistor MNfb is coupled at node "G₂And "Y" and the gate is coupled to node "X". In some embodiments, feedback transistor MNfb will V_DS,2Restricted to less than V_maxAnd thus prevents excessive degradation and failure of transistor MN 2. Two operating scenarios of the circuit are described herein.

In the first case, transistor MN2 is off (e.g., V_GS,2＜V_th) And V is_DS,2＞V_maxIs possible. In this case, once V_DS,2Begin to exceed V_thTransistor MNfb turns on. Transistor MNfb now provides an additional charge/discharge path for node "Y" according to some embodiments. This may raise the voltage at node "Y" to the voltage at the gate of transistor MN2, thereby reducingV_DS,2＝V_X-V_YAnd limit it to below V_maxThe value of (c).

In the second case, transistor MN2 is on (e.g., V_GS,2＞V_th) And V is_DS,2＞V_maxIs not possible. In this case, V_DS,2＝V_GS,PAt 0, the transistor MNfb is turned off, which does not further affect the overall circuit function.

Fig. 3 illustrates an "N" stacked circuit configuration 300 with aging protection, according to some embodiments of the present disclosure. It is pointed out that those elements of fig. 3 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. The "N" stacked circuit configuration 300 includes "N" transistors MN1 through MNN coupled in series. In some embodiments, a feedback transistor is associated with each transistor in the stack. Here, as shown, "N" feedback transistors MNfb 1-MNfbN are shown coupled to the internal node. For example, feedback transistor MNfbN has its gate coupled to node "N-1", its drain coupled to gate GN, and its source coupled to node "N".

Fig. 4A shows a NAND logic gate circuit 400 that suffers from burn-in failures. The NAND logic gate circuit 400 includes p-type transistors MP1 and MP2 and n-type transistors MN1 and MN2 coupled together as shown, such that transistors MP1 and MN2 are controlled by node "a" providing signal "a" and transistors MP2 and MN1 are controlled by node "B" providing signal "B". For example, NAND gate 400 may be part of a Ring Oscillator (RO) designed for industrial applications requiring a lifetime in the range of 5 to 10 years. Here, the stack of transistors MN2 and MN1 is similar to the stack shown in fig. 1A-B and suffers from the same problems.

NAND logic gate circuit 400 depicts a schematic of a single NAND RO stage, which is prior art (state-of-the-art). In prior art solutions, transistor MN2 may operate in excess of the device voltage limit, which would result in excessive aging of the entire RO.

Fig. 4B illustrates a NAND logic gate circuit 420 with aging resistance devices according to some embodiments of the present disclosure. It is pointed out that those elements of fig. 4B having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. As shown, NAND logic gate circuit 420 includes an anti-aging device comprising a transistor MNfb coupled to nodes "Y" and "a" and controllable by node "X". Transistor MNfb in NAND logic gate 420 behaves the same as transistor MNfb in fig. 2.

Figure 5 illustrates a set of graphs 500 comparing the transient behavior of the NAND logic gate circuit of figures 4A-B, in accordance with some embodiments of the present disclosure. It is pointed out that those elements of fig. 5 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Graph 501 shows the inputs at nodes "a" and "B" over time. Graph 502 shows the output voltage on node "X" for fig. 4A (prior art NAND) and fig. 4B (robust NAND). Graph 503 shows the voltage on node "Y" for fig. 4A (prior art NAND) and fig. 4B (robust NAND). Graph 504 shows V for transistor MN2 of fig. 4A (prior art NAND) and 4B (robust NAND)_DS。

Considering the waveforms of the prior art solutions, the following are observed: when the input signal is from V_DDSwitch to V_SSResulting in the output "X" from V_SSTransition to V_DDWhile the voltage at node "Y" drops to V_SSThe following. In the example considered, the negative voltage is caused by a capacitive voltage divider formed by the gate-source capacitance C of the transistor MN2_GSAnd a capacitance C at node "Y_YForming:thus, as shown in graph 504, the drain-source voltage V of transistor MN2_DSExceeds V_DD(V_DS＝V_out-V_Y>V_DD)。It can be seen that V_DSExceeding the maximum voltage level (usually V)_max＝1.05*V_DD–1.1*V_DD) Up to 50% of the time, thus posing a high reliability risk to transistor MN 2.

According to some embodiments, this situation in a stacked transistor configuration may be avoided when applying anti-aging means. When the input is from V_DDSwitch to V_SSWhen it is time, it causes the output node "X" to be driven from V_SSTransition to V_DDAt this time, the additional transistor MNfb is turned on. As can be seen from the transient waveform of FIG. 5, transistor MNfb charges node "Y" to V_SSThereby setting V of transistor MN2_DSRestricted to V_DD. Note that according to some embodiments, the waveform at the NAND gate output is completely unaffected (or negligible) by the anti-aging device.

Figure 6 shows a set of graphs comparing the transient behavior of the NAND logic gate circuit of figures 4A-B over a number of years, in accordance with some embodiments of the present disclosure. Graph 601 shows transient behavior at output node "X" of the NAND of fig. 4A, while graph 602 shows transient behavior at output node "X" of the NAND of fig. 4B. With the prior art solution (as shown in fig. 4A), the fall time increases significantly with the use period. For example, after 8 years (yrs), the increase in fall time is so great that the output no longer reaches a low level during one clock cycle (200 MHz in this example), resulting in a logic output level error (e.g., circuit failure). In contrast, with the anti-aging device, the degradation of the output falling edge is significantly reduced. For example, even after 10 years of operation, a robust NAND gate works normally, with an increase in output fall time of the order of only 1%, which is negligible.

Fig. 7 illustrates a graph 700 showing Ring Oscillator (RO) frequency degradation versus lifetime, in accordance with some embodiments. Graph 700 compares RO frequency degradation due to transistor aging versus time for the prior art design solution of fig. 4A and the aging protection circuit solution of fig. 4B. In this example, the RO frequency with the prior art solution deteriorated by 45% after 10 years, while the frequency with the proposed solution deteriorated by 14% after 10 years.

Fig. 8 shows a graph 800 illustrating drive current degradation of the transistor MN2 of fig. 1A and 2, in accordance with some embodiments. Here, the drive current reduction of the transistor MN2 in a single RO stage is plotted against time. In the technology used, the drive current reduction must be below 50% to prevent breakdown of the corresponding transistor. With prior art solutions, this threshold limit has been reached after about one year. Thus, the prior art solutions do not meet the demand for products requiring a lifetime of more than 1 year. In contrast, with the aging resistant circuit technique of some embodiments, the maximum current degradation after 10 years is 28%, leaving sufficient margin for the 50% threshold limit. The performance and area impact of the shown anti-aging circuit is negligible. According to some embodiments, in the case of NAND RO, adding an anti-aging circuit to the prior art solution results in an increase of only 2.5% in the active gate area.

Table 1 summarizes and compares the performance of the prior art solution with the performance of the proposed solution.

Parameter(s)	Current solutions	Anti-aging solution
			Service life
	1 year	More than 10 years
			Area effect
	0	+2.5％
			RO frequency degradation after 10 years	45％	Less than 14 percent
Drive current decreased after 10 years	80％	28％

The anti-aging circuit or device of various embodiments is not limited to NAND circuits. For example, the aging resistance circuit or device of various embodiments may also be implemented in other digital circuits having various stacked n-type or p-type transistors.

Fig. 9 illustrates an anti-aging NOR logic gate circuit 900 according to some embodiments of the present disclosure. A conventional NOR logic gate circuit includes p-type transistors MP1 and MP2 and n-type transistors MN1 and MN2 coupled together as shown, having input nodes "a" and "B" and an output node OUTB. Here, the transistor stack is formed by p-type transistors MP1 and MP 2. As discussed with reference to the NAND gate of fig. 4A, here, without the feedback p-type transistor MPfb, the transistor in the stack (here, transistor MP2) suffers from excessive aging (like transistor MN2 in fig. 4A). Referring back to fig. 9, to mitigate aging, in some embodiments, a feedback transistor MPbf coupled to transistors MP2, MP1, MN1, and MN2 is added as shown.

In some embodiments, a feedback p-type transistor MPfb is provided that is coupled to the two n-type transistors of the NOR gate (MN1 and MN2) and the two p-type transistors of the NOR gate (MP1 and MP 2). In some embodiments, the gate terminal of feedback transistor MPfb is coupled to the drain terminals of two n-type transistors MN1 and MN2 of the NOR gate. In some embodiments, feedback transistor MPfb is coupled to the gate terminal of one of the two p-type transistors (e.g., transistor MP 2). In some embodiments, the feedback transistor MPfb is a p-type transistor. In some embodiments, the gate terminal of feedback transistor MPfb is coupled to the output node OUTB of the NOR gate. In some embodiments, the feedback transistor MPfb is smaller in size than one of the two p-type transistors. For example, feedback transistor MPfb may occupy only 2.5% of the total area of NOR gate 900, and may be 75% to 80% of the width of transistor MP2 or MP 1.

Fig. 10 illustrates an anti-aging selection circuit 1000 according to some embodiments of the present disclosure. In some embodiments, the aging resistant selection circuit 1000 includes p-type devices MP1, MP2, and MPfb (first feedback devices) and n-type transistors MN1, MN2, and MNfb (second feedback devices) coupled together as shown. The related art selection circuit includes transistors MP1, MP2, MN1, and MN2 without an anti-aging device (e.g., feedback transistors MPfb and MNfb). The selection circuit is designed to provide an inverted version of the signal on node "a" to the output node OUTB when the signal on the SEL node is high and the signal on SELB is low.

Referring to fig. 10, there are two stacks of the same conductivity type. The first stack includes p-type transistors MP1 and MP2, where transistor MP1 is controlled by SELB (the inverse of SEL) and transistor MP2 is controlled by node "a". The second stack includes n-type transistors MN1 and MN2, where transistor MN1 is controlled by SEL and transistor MN2 is controlled by node "a". Just as transistors MN2 of fig. 1A-B experience aging stress, transistors MP2 and MN2 in their respective stacks are also subject to aging stress. To mitigate or reduce aging stress, a first feedback p-type transistor MPfb is coupled to transistors MP1 and MP2 and node OUTB, and a second feedback n-type transistor MNfb is coupled to transistors MN1 and MN2 and node OUTB, as shown.

Fig. 11 illustrates an anti-aging Multiplexer (MUX) circuit 1100 according to some embodiments of the present disclosure. It is pointed out that those elements of fig. 11 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. The anti-aging multiplexer circuit 1100 includes two instances of the anti-aging selection circuit 1000 of fig. 10, and thus includes four feedback devices including p-type transistors MPfba and MPfbb and n-type transistors MNfba and MNfbb. In some embodiments, MUX circuit 1100 includes p-type transistors MP1a, MP1b, MP2a, and MP2b, MPfba, and MPfbb, and n-type transistors MN1a, MN1b, MN2a, MN2b, MNfba, and MNfbb, coupled together as shown. The two instances of the anti-aging selection circuit 1000 of fig. 10 are coupled together such that the output node OUTB is shared while the selection inputs for one of the anti-aging selection circuits are swapped.

For example, transistor MP1b is controlled by the SEL node, transistor MP1a is controlled by the SELB node, transistor MN1a is controlled by the SEL node, and transistor MN1b is controlled by the SELB node. The two input nodes are nodes "a" and "B" that are selectively provided to the output node OUTB according to the logic levels of the signals on the select nodes SEL and SELB (which are the inverse of SEL). In some embodiments, the feedback devices MPfba, MPfbb, MNfba, and MNfbb provide aging resistance to the transistors MP2a, MP2b, MN2a, and MN2b, respectively.

Fig. 12 illustrates a smart device or computer system or SoC (system on a chip) having an anti-aging apparatus, according to some embodiments of the present disclosure. It is pointed out that those elements of fig. 12 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

FIG. 12 shows a block diagram of an embodiment of a mobile device that may use a flat interface connector. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, mobile phone or smartphone, wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, but not all components of such a device are shown in the computing device 1600.

In some embodiments, the computing device 1600 includes a first processor 1610 with anti-aging means according to some embodiments discussed. According to some embodiments, other modules of the computing device 1600 may also include the device 300, anti-aging means. Various embodiments of the present disclosure may also include a network interface (e.g., a wireless interface) within 1670 such that system embodiments may be incorporated into a wireless device (e.g., a cellular telephone or personal digital assistant).

In some embodiments, processor 1610 may include one or more physical devices, such as a microprocessor, application processor, microcontroller, programmable logic device, or other processing module. The processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. Processing operations include operations related to I/O (input/output) of a human user or other device, operations related to power management, and/or operations related to connecting the computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

In some embodiments, computing device 1600 includes audio subsystem 1620, which represents hardware (e.g., audio hardware and audio circuitry) and software (e.g., drivers, codecs) components associated with providing audio functionality to the computing device. The audio functions may include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands, which are received and processed by processor 1610.

In some embodiments, computing device 1600 includes a display subsystem 1630. Display subsystem 1630 represents hardware (e.g., display device) and software (e.g., drivers) components that provide visual and/or tactile displays for a user to interact with computing device 1600. Display subsystem 1630 includes a display interface 1632, which includes the particular screen or hardware device used to provide the display to the user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.

In some embodiments, computing device 1600 includes I/O controller 1640. I/O controller 1640 represents hardware devices and software components related to user interaction. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. In addition, I/O controller 1640 illustrates connection points for additional devices that connect to computing device 1600, through which a user may interact with the system. For example, devices that may be attached to the computing device 1600 may include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, or an I/O device for use with a particular application (e.g., a card reader or other device).

As described above, I/O controller 1640 can interact with audio subsystem 1620 and/or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. In addition, audio output may be provided instead of or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which may be managed, at least in part, by I/O controller 1640. Additional buttons or switches may also be present on computing device 1600 to provide I/O functions managed by I/O controller 1640.

In some embodiments, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors, or other environmental sensors, or other hardware that may be included in computing device 1600. The input may be part of direct user interaction, as well as providing environmental input to the system to affect its operation (e.g., filtering noise, adjusting display for brightness detection, applying a flash or other feature for the camera).

In some embodiments, computing device 1600 includes power management 1650, which power management 1650 manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1660 includes storage devices for storing information in computing device 1600. The memory may include a non-volatile memory device (the state does not change if power to the memory device is interrupted) and/or a volatile memory device (the state is indeterminate if power to the memory device is interrupted). Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of computing device 1600.