阅读说明：本技术 辐射检测装置及其制备方法 (Radiation detection device and method of making same ) 是由 刘雨润 曹培炎 于 2019-03-29 设计创作，主要内容包括：本文公开了一种用于检测辐射的装置及其制备方法。该方法包括在半导体衬底(102)中形成凹部(104),其中所述半导体衬底(102)的一部分(107)延伸到所述凹部(104)中并且被所述凹部(104)包围；将半导体纳米晶体(106)沉积到所述凹部(104)中,所述半导体纳米晶体(106)具有与所述半导体衬底(102)不同的组成；在所述半导体衬底(102)中形成第一掺杂半导体区(108)；在所述半导体衬底(102)中形成第二掺杂半导体区(109)；其中所述第一掺杂半导体区(108)和所述第二掺杂半导体区(109)形成将所述部分(107)与所述半导体衬底(102)的其余部分分开的p-n结。(Disclosed herein are devices for detecting radiation and methods of making the same. The method comprises forming a recess (104) in a semiconductor substrate (102), wherein a portion (107) of the semiconductor substrate (102) extends into the recess (104) and is surrounded by the recess (104); depositing semiconductor nanocrystals (106) into the recesses (104), the semiconductor nanocrystals (106) having a different composition than the semiconductor substrate (102); forming a first doped semiconductor region (108) in the semiconductor substrate (102); forming a second doped semiconductor region (109) in the semiconductor substrate (102); wherein the first doped semiconductor region (108) and the second doped semiconductor region (109) form a p-n junction separating the portion (107) from the rest of the semiconductor substrate (102).)

1. A method, comprising:

forming a recess in a semiconductor substrate, wherein a portion of the semiconductor substrate extends into and is surrounded by the recess;

depositing semiconductor nanocrystals into the recesses, the semiconductor nanocrystals having a different composition than the semiconductor substrate;

forming a first doped semiconductor region in the semiconductor substrate;

forming a second doped semiconductor region in the semiconductor substrate;

wherein the first doped semiconductor region and the second doped semiconductor region form a p-n junction separating the portion of the semiconductor substrate from a remainder of the semiconductor substrate.

2. The method of claim 1, wherein the first doped semiconductor region surrounds the second doped semiconductor region.

3. The method of claim 1 wherein said second doped semiconductor region is in electrical contact with said portion of said semiconductor substrate.

4. The method of claim 1, wherein said forming said second doped semiconductor region comprises doping a portion of said first doped semiconductor region.

5. The method of claim 1, wherein the first doped semiconductor region extends from a surface of the semiconductor substrate to an interface between the recess and the semiconductor substrate.

6. The method of claim 1, wherein the second doped semiconductor region is coextensive with the first doped semiconductor region.

7. The method of claim 1, wherein said forming said recess comprises forming a mask on said semiconductor substrate and etching an area of said semiconductor substrate not covered by said mask.

8. The method of claim 7, wherein the mask comprises a metal, silicon nitride, silicon dioxide, or carbon.

9. The method of claim 7, wherein said etching said region is by wet etching, dry etching, or a combination thereof.

10. The method of claim 1, wherein the semiconductor substrate comprises silicon, germanium, GaAs, or a combination thereof.

11. The method of claim 1, wherein the semiconductor nanocrystals are cadmium zinc telluride (CdZnTe) nanocrystals, cadmium telluride (CdTe) nanocrystals, cadmium selenide (CdSe) nanocrystals, cadmium sulfide (CdS) nanocrystals, or lead sulfide (PbS) nanocrystals.

12. The method of claim 1, wherein the recess has a shape of a frustum, a prism, a pyramid, a cuboid, or a cylinder.

13. The method of claim 1, wherein the semiconductor nanocrystals have a diameter of 10 nanometers or less.

14. The method of claim 1, further comprising bonding the semiconductor substrate to another substrate including an electronic system therein or thereon, wherein the electronic system is electrically connected to the second doped semiconductor region and is configured to process an electrical signal generated in the semiconductor substrate.

15. A method, comprising:

forming a via in a semiconductor layer supported directly on an electrically insulating layer, wherein a portion of the semiconductor layer remains in and is surrounded by the via;

depositing semiconductor nanocrystals into the vias, the semiconductor nanocrystals having a different composition than the semiconductor layer;

forming an opening through the electrically insulating layer such that the portion of the semiconductor layer is exposed in the opening;

forming an electrode in the opening, the electrode in electrical contact with the portion of the semiconductor layer.

16. The method of claim 15, wherein said forming said via comprises forming a mask on said semiconductor layer and etching regions of said semiconductor layer not covered by said mask.

17. The method of claim 16, wherein the mask comprises a metal, silicon nitride, silicon dioxide, or carbon.

18. The method of claim 16, wherein said etching said region is by wet etching, dry etching, or a combination thereof.

19. The method of claim 15, wherein the semiconductor layer comprises silicon, germanium, GaAs, or a combination thereof.

20. The method of claim 15, wherein the electrically insulating layer comprises an oxide, nitride, or oxynitride.

21. The method of claim 15, wherein the semiconductor nanocrystals are cadmium zinc telluride (CdZnTe) nanocrystals, cadmium telluride (CdTe) nanocrystals, cadmium selenide (CdSe) nanocrystals, cadmium sulfide (CdS) nanocrystals, or lead sulfide (PbS) nanocrystals.

22. The method of claim 15, wherein the via is shaped as a frustum, prism, pyramid, cuboid, or cylinder.

23. The method of claim 15, wherein the semiconductor nanocrystal has a diameter of 10 nanometers or less.

24. The method of claim 15, further comprising bonding the electrically insulating layer to an electronic layer that is electrically connected to the electrode and configured to process an electrical signal generated in the semiconductor layer.

25. A radiation detector, comprising:

a semiconductor substrate;

a recess in the semiconductor substrate, wherein a portion of the semiconductor substrate extends into and is surrounded by the recess;

a semiconductor nanocrystal in the recess, the semiconductor nanocrystal having a different composition than the semiconductor substrate;

a first doped semiconductor region in the semiconductor substrate; and

a second doped semiconductor region in the semiconductor substrate;

wherein the first doped semiconductor region and the second doped semiconductor region form a p-n junction separating the portion of the semiconductor substrate from a remainder of the semiconductor substrate.

26. The radiation detector of claim 25, wherein the radiation detector is configured to absorb radiation particles incident on the semiconductor nanocrystal and generate charge carriers.

27. The radiation detector of claim 25, wherein the first doped semiconductor region surrounds the second doped semiconductor region.

28. The radiation detector of claim 25, wherein the second doped semiconductor region is in electrical contact with the portion of the semiconductor substrate.

29. The radiation detector of claim 25, wherein the first doped semiconductor region extends from a surface of the semiconductor substrate to an interface between the recess and the semiconductor substrate.

30. The radiation detector of claim 25, wherein the second doped semiconductor region is coextensive with the first doped semiconductor region.

31. The radiation detector of claim 25, wherein the semiconductor substrate comprises silicon, germanium, GaAs, or a combination thereof.

32. The radiation detector of claim 25, wherein the semiconductor nanocrystals are cadmium zinc telluride (CdZnTe) nanocrystals, cadmium telluride (CdTe) nanocrystals, cadmium selenide (CdSe) nanocrystals, cadmium sulfide (CdS) nanocrystals, or lead sulfide (PbS) nanocrystals.

33. The radiation detector of claim 25, wherein the recess is frustum, prismatic, pyramidal, cuboid, or cylindrical in shape.

34. The radiation detector of claim 25, further comprising

An electronic layer bonded to the semiconductor substrate, the electronic layer including an electronic system electrically connected to the second doped semiconductor region and configured to process an electrical signal generated in the semiconductor substrate.

35. A radiation detector, comprising:

an electrically insulating layer;

a semiconductor layer supported directly on the electrically insulating layer;

a via in the semiconductor layer, wherein a portion of the semiconductor layer extends into and is surrounded by the via;

a semiconductor nanocrystal in the via, the semiconductor nanocrystal having a different composition than the semiconductor layer; and

an electrode through the electrically insulating layer, the electrode in electrical contact with the portion of the semiconductor layer.

36. The radiation detector of claim 35, wherein the semiconductor layer comprises silicon, germanium, GaAs, or a combination thereof.

37. The radiation detector of claim 35, wherein the electrically insulating layer comprises an oxide, nitride, or oxynitride.

38. The radiation detector of claim 35, wherein the semiconductor nanocrystals are cadmium zinc telluride (CdZnTe) nanocrystals, cadmium telluride (CdTe) nanocrystals, cadmium selenide (CdSe) nanocrystals, cadmium sulfide (CdS) nanocrystals, or lead sulfide (PbS) nanocrystals.

39. The radiation detector of claim 35, wherein the via is frustum, prismatic, pyramidal, cuboid, or cylindrical in shape.

40. The radiation detector of claim 35, further comprising an electronics layer bonded to the electrically insulating layer, the electronics layer comprising an electronics system electrically connected to the electrodes and configured to process electrical signals generated in the semiconductor layer.

[ technical field ] A method for producing a semiconductor device

The disclosure herein relates to radiation detection devices and methods of making the same.

[ background of the invention ]

A radiation detector is a device that measures characteristics of radiation. Examples of the characteristics may include the spatial distribution of intensity, phase and polarization of the radiation. The radiation may be radiation that interacts with the object. For example, the radiation measured by the radiation detector may be radiation that has been transmitted through or reflected from the object. The radiation may be electromagnetic radiation such as infrared light, visible light, ultraviolet light, X-rays or gamma rays. The radiation may be of other types, such as alpha rays and beta rays.

One type of radiation detector is based on the interaction between radiation and a semiconductor. For example, a radiation detector of this type may have a semiconductor layer that absorbs radiation and generates carriers (e.g., electrons and holes) and a circuit for detecting the carriers.

Cadmium zinc telluride (CdZnTe or Cd)_1-xZn_xTe) is a direct gap semiconductor and an excellent candidate for room temperature radiation detection. CdZnTe is an alloy of zinc telluride and CdTe, and the value of x is the molar concentration of zinc in the CdZnTe. CdZnTe, with x values from 0.04 to 0.2, is considered as a prospect for detector development as it can handle and improve certain properties of CdTe. For example, CdTe and CdZnTe both have a large atomic number, and thus give the material excellent braking force, thereby having high absorption efficiency for incident X-rays, gamma-rays; and has a large bandgap (e.g., 1.5eV-1.6eV) and thus can be used for room temperature detectors; it also has a high resistivity to achieve a good signal-to-noise ratio of the radiation detector. At the same time, CdZnTe has a larger bandgap than CdTe due to the incorporation of zinc, thus increasing the maximum achievable resistivity.

The practical use of CdTe and CdZnTe detectors covers a wide range of applications, such as medical and industrial imaging, industrial measurement and non-destructive detection, security and surveillance, nuclear and non-diffusion, and astrophysics.

[ summary of the invention ]

Disclosed herein is a method comprising: forming a recess in a semiconductor substrate, wherein a portion of the semiconductor substrate extends into and is surrounded by the recess; depositing semiconductor nanocrystals into the recesses, the semiconductor nanocrystals having a different composition than the semiconductor substrate; forming a first doped semiconductor region in the semiconductor substrate; forming a second doped semiconductor region in the semiconductor substrate; wherein the first doped semiconductor region and the second doped semiconductor region form a p-n junction separating the portion of the semiconductor substrate from a remainder of the semiconductor substrate.

According to an embodiment, the first doped semiconductor region surrounds the second doped semiconductor region.

According to an embodiment, the second doped semiconductor region is in electrical contact with the portion of the semiconductor substrate.

According to an embodiment, the forming the second doped semiconductor region comprises doping a portion of the first doped semiconductor region.

According to an embodiment, the first doped semiconductor region extends from a surface of the semiconductor substrate to an interface between the recess and the semiconductor substrate.

According to an embodiment, the second doped semiconductor region is coextensive with the first doped semiconductor region.

According to an embodiment, the forming the recess comprises forming a mask on the semiconductor substrate and etching an area of the semiconductor substrate not covered by the mask.

According to an embodiment, the mask comprises metal, silicon nitride, silicon dioxide or carbon.

According to an embodiment, said etching said region is by wet etching, dry etching or a combination thereof.

According to an embodiment, the semiconductor substrate comprises silicon, germanium, GaAs or a combination thereof.

According to an embodiment, the semiconductor nanocrystal is a cadmium zinc telluride (CdZnTe) nanocrystal, a cadmium telluride (CdTe) nanocrystal, a cadmium selenide (CdSe) nanocrystal, a cadmium sulfide (CdS) nanocrystal, or a lead sulfide (PbS) nanocrystal.

According to an embodiment, the shape of the recess is frustum, prismatic, pyramidal, cuboid or cylindrical.

According to an embodiment, the semiconductor nanocrystal has a diameter of 10 nanometers or less.

According to an embodiment, the method described herein further comprises bonding the semiconductor substrate to another substrate comprising an electronic system therein or thereon, wherein the electronic system is electrically connected to the second doped semiconductor region and is configured to process an electrical signal generated in the semiconductor substrate.

Disclosed herein is a method comprising: forming a via in a semiconductor layer supported directly on an electrically insulating layer, wherein a portion of the semiconductor layer remains in and is surrounded by the via; depositing semiconductor nanocrystals into the vias, the semiconductor nanocrystals having a different composition than the semiconductor layer; forming an opening through the electrically insulating layer such that the portion of the semiconductor layer is exposed in the opening; forming an electrode in the opening, the electrode in electrical contact with the portion of the semiconductor layer.

According to an embodiment, the forming the via hole includes forming a mask on the semiconductor layer and etching a region of the semiconductor layer not covered by the mask.

According to an embodiment, the mask comprises metal, silicon nitride, silicon dioxide or carbon.

According to an embodiment, said etching said region is by wet etching, dry etching or a combination thereof.

According to an embodiment, the semiconductor layer comprises silicon, germanium, GaAs or a combination thereof.

According to an embodiment, the electrically insulating layer comprises an oxide, a nitride or an oxynitride.

According to an embodiment, the shape of the through-hole is frustum, prism, pyramid, cuboid or cylinder.

According to an embodiment, the method further comprises bonding the electrically insulating layer to an electronic layer, the electronic layer being electrically connected to the electrode and configured to process an electrical signal generated in the semiconductor layer.

Disclosed herein is a radiation detector comprising: a semiconductor substrate; a recess in the semiconductor substrate, wherein a portion of the semiconductor substrate extends into and is surrounded by the recess; a semiconductor nanocrystal in the recess, the semiconductor nanocrystal having a different composition than the semiconductor substrate; a first doped semiconductor region in the semiconductor substrate; and a second doped semiconductor region in the semiconductor substrate; wherein the first doped semiconductor region and the second doped semiconductor region form a p-n junction separating the portion of the semiconductor substrate from a remainder of the semiconductor substrate.

According to an embodiment, the radiation detector is configured to absorb radiation particles incident on the semiconductor nanocrystal and generate charge carriers.

Disclosed herein is a radiation detector comprising: an electrically insulating layer; a semiconductor layer supported directly on the electrically insulating layer; a via in the semiconductor layer, wherein a portion of the semiconductor layer extends into and is surrounded by the via; a semiconductor nanocrystal in the via, the semiconductor nanocrystal having a different composition than the semiconductor layer; and an electrode through the electrically insulating layer, the electrode in electrical contact with the portion of the semiconductor layer.

[ description of the drawings ]

Fig. 1 schematically shows a cross-sectional view of a radiation detector according to an embodiment.

Fig. 2A schematically shows a detailed cross-sectional view of the radiation detector according to an embodiment.

Fig. 2B schematically shows a detailed cross-sectional view of the radiation detector according to an embodiment.

Fig. 2C-2E schematically show top views of the radiation absorbing layer according to embodiments.

Fig. 3 schematically illustrates a process of forming the radiation absorbing layer in fig. 2A, according to an embodiment.

Fig. 4 schematically illustrates a process of forming the recesses of the radiation absorbing layer in fig. 2A according to an embodiment.

Fig. 5 schematically illustrates a process of forming the radiation absorbing layer in fig. 2B, according to an embodiment.

Fig. 6 schematically illustrates a process of forming a via of the radiation absorbing layer in fig. 2B according to an embodiment.

Fig. 7A and 7B schematically illustrate bonding between the radiation absorbing layer and the electron shells to form a radiation detector as shown in fig. 2A and 2B, respectively, according to an embodiment.

Fig. 8A and 8B respectively show component diagrams of the electronic system according to an embodiment.

Fig. 9 schematically shows a temporal variation of the voltage of the electrodes or the electrical contacts according to an embodiment.

[ detailed description ] embodiments

Fig. 1 schematically shows a cross-sectional view of a radiation detector 100 according to an embodiment. The radiation detector 100 may include: a radiation absorbing layer 110 configured to absorb incident radiation and generate electrical signals therefrom, and an electronics layer 120 (e.g., ASIC) for processing or analyzing the electrical signals generated in the radiation absorbing layer 110. The radiation detector 100 may or may not include a scintillator. The radiation absorbing layer 110 may comprise a semiconductor material such as silicon, germanium, GaAs, CdTe, CdZnTe, or combinations thereof. The semiconductor may have a high mass attenuation coefficient for the radiation of interest.

Fig. 2A schematically shows a detailed cross-sectional view of the radiation detector 100 according to an embodiment. The radiation detector 100 has a semiconductor substrate 102 and a recess 104 in the semiconductor substrate 102. A portion 107 of the semiconductor substrate 102 extends into the recess 104 and is surrounded by the recess 104. The radiation detector 100 has semiconductor nanocrystals 106 in the recess 104. The radiation detector 100 also has a first doped semiconductor region 108 and a second doped semiconductor region 109 in the semiconductor substrate 102. The first doped semiconductor region 108 and the second doped semiconductor region 109 form a p-n junction separating the portion 107 of the semiconductor substrate 102 from the remainder of the semiconductor substrate 102. In other words, each electrical path between the portion 107 of the semiconductor substrate 102 and the remainder of the semiconductor substrate 102 and throughout the interior of the semiconductor substrate 102 traverses the p-n junction. The portion 107 of the semiconductor substrate 102 may be in electrical contact with the second doped semiconductor region 109. The semiconductor substrate 102 (including the portion 107), the semiconductor nanocrystal 106, the first doped semiconductor region 108, and the second doped semiconductor region 109 can be in the radiation absorbing layer 110.

The semiconductor substrate 102 may be of a semiconductor material such as silicon, germanium, GaAs, combinations of the foregoing, or other suitable semiconductors. The semiconductor substrate 102 may be an extrinsic semiconductor (i.e., doped with an electron donor or electron acceptor).

The second doped semiconductor region 109 may be surrounded by the first doped semiconductor region 108. The second doped semiconductor region 109 need not be in the center of the first doped semiconductor region 108. The first doped semiconductor region 108 may extend from the surface 102b of the semiconductor substrate 102 to an interface 106b between the recess 104 and the semiconductor substrate 102. The second doped semiconductor region 109 may be coextensive with the first doped semiconductor region 108, e.g., in a direction perpendicular to the semiconductor substrate 102.

The portion 107 may be cylindrical or prismatic (e.g., rectangular prismatic or triangular prismatic). The portion 107 may have a height (i.e., a dimension in a direction perpendicular to the semiconductor substrate 102) equal to, greater than, or less than the height of the recess 104. The portion 107 may have a height of a few micrometers. The portion 107 may have the same doping type as the second doped semiconductor region 109 (e.g., both n-type or both p-type), but have an opposite doping type from the remainder of the semiconductor substrate 102 (e.g., the portion 107 is n-type and the remainder of the semiconductor substrate 102 is p-type, or vice versa).

In an embodiment, the semiconductor nanocrystals 106 can have a different composition than the semiconductor substrate 102. That is, the semiconductor nanocrystals 106 differ from the semiconductor substrate 102 not only in doping.

Here, the semiconductor nanocrystal 106 may refer to a crystal having a diameter between about 1nm and about 100 nm. In embodiments, the diameter of the semiconductor nanocrystal 106 can be 10 nanometers or less. The semiconductor nanocrystals 106 can be synthesized by various techniques known to those skilled in the art. The semiconductor nanocrystals 106 can have different shapes and orientations.

In an embodiment, the semiconductor nanocrystals 106 can be cadmium zinc telluride (CdZnTe) nanocrystals, cadmium telluride (CdTe) nanocrystals, cadmium selenide (CdSe) nanocrystals, cadmium sulfide (CdS) nanocrystals, or lead sulfide (PbS) nanocrystals, or another suitable nanocrystal that can absorb radiation particles incident thereon and generate charge carriers. The semiconductor nanocrystals 106 can have a sufficient thickness and thus a sufficient degree of absorption (e.g., > 80% or > 90%) for the incident radiation particles of interest (e.g., X-ray photons). The semiconductor nanocrystals 106 are in electrical contact with the portion 107 of the semiconductor substrate 102 and the rest of the semiconductor substrate 102.

When the radiation strikes the radiation absorbing layer 110, the semiconductor nanocrystals 106 can absorb radiation particles incident thereon and generate one or more carriers by several mechanisms. One radiation particle can generate 1 to 100000 carriers. The carriers may include electrons and holes. Under an electric field between the portion 107 and the rest of the semiconductor substrate 102, the carriers may drift to the sidewalls 104b of the recess 104 and the portion 107. For example, the holes may drift to the sidewall 104b, and the electrons may drift to the portion 107.

In an embodiment, the p-n junction formed by the first doped semiconductor region 108 and the second doped semiconductor region 109 may be under reverse bias during operation of the radiation detector 100. This reverse bias may be used to establish an electric field between the portion 107 and the rest of the semiconductor substrate 102. The p-n junction under the reverse bias substantially blocks current flow through the p-n junction, but allows current to flow between the portion 107 and the electron shell 120 through the second doped semiconductor region 109.

The electron shell 120 may include an electronic system 121, the electronic system 121 being configured to process an electrical signal generated by the collected carriers on the portion 107. The electronic system 121 may include analog circuits such as filter networks, amplifiers, integrators, and comparators, or digital circuits such as microprocessors and memories. The electronic system 121 may include one or more ADCs. The electronic system 121 may be electrically connected to the portion 107 by a via 131 and the second doped semiconductor region 109. The space between the vias may be filled with a filler material 130, which may increase the mechanical stability of the connection of the electron layer 120 to the radiation absorbing layer 110. Other bonding techniques may also be used to connect the electronic system 121 to the portion 107 or the portion 197 without using vias.

Fig. 2B schematically shows a detailed cross-sectional view of the radiation detector 190 according to an embodiment. The radiation detector 190 has an electrical insulator layer 198, a semiconductor layer 192 supported directly on the electrical insulator layer 198, and a via 194 in the semiconductor layer 192. A portion 197 of the semiconductor layer 192 extends into the via 194 and is surrounded by the via 194. The radiation detector 190 has a semiconductor nanocrystal 196 in the through-hole 194. The radiation detector 190 also has an electrode 199 in (e.g., through) the electrical insulator layer 198 and in electrical contact with the portion 197. The semiconductor layer 192 (including the portion 197), the semiconductor nanocrystals 196, the electrical insulator layer 198, and the electrode 199 can be in one radiation absorbing layer 191.

The semiconductor layer 192 may have a semiconductor material such as silicon, germanium, GaAs, or a combination thereof. The semiconductor layer 192 may be an extrinsic semiconductor (i.e., doped with an electron donor or an electron acceptor).

The electrical insulator layer 198 may be an oxide, nitride or oxynitride, or other suitable material.

The portion 197 may be cylindrical or prismatic (e.g., rectangular prismatic or triangular prismatic). The portion 197 may have a height (i.e., a dimension in a direction perpendicular to the semiconductor layer 192) equal to, greater than, or shorter than the height of the via 194. The portion 197 may have a height of several microns.

In an embodiment, the semiconductor nanocrystals 196 may have a different composition than the semiconductor layer 192. That is, the semiconductor nanocrystals 106 differ from the semiconductor layer 192 not only in doping. The semiconductor nanocrystals 196 are not formed by doping the semiconductor layer 192. For example, if the semiconductor layer 192 is doped silicon, the semiconductor nanocrystals 196 are not doped silicon or intrinsic silicon.

Here, the semiconductor nanocrystal 196 may refer to a crystal having a diameter between about 1nm and about 100 nm. In an embodiment, the semiconductor nanocrystal 196 can have a diameter of 10 nanometers or less. The semiconductor nanocrystal 196 may be synthesized by various techniques known to those skilled in the art. The semiconductor nanocrystals 196 may have different shapes and orientations.

In embodiments, the semiconductor nanocrystals 196 can be cadmium zinc telluride (CdZnTe) nanocrystals, cadmium telluride (CdTe) nanocrystals, cadmium selenide (CdSe) nanocrystals, cadmium sulfide (CdS) nanocrystals, or lead sulfide (PbS) nanocrystals, or another suitable nanocrystal that can absorb radiation particles incident thereon and generate charge carriers. The semiconductor nanocrystals 196 can have a sufficient thickness and thus sufficient absorbance (e.g., > 80% or > 90%) for the incident radiation particles of interest (e.g., X-ray photons). The semiconductor nanocrystals 106 are in electrical contact with the portion 197 of the semiconductor substrate 102 and the remainder of the semiconductor layer 192

The electrode 199 may comprise a conductive material, such as a metal (e.g., gold, copper, aluminum, platinum, etc.), or any other suitable conductive material (e.g., a doped semiconductor). The electrode 199 may be embedded in the electrical insulator layer 198 or may extend through the entire thickness of the electrical insulator layer 198.

When the radiation strikes the radiation absorbing layer 191, the semiconductor nanocrystals 196 may absorb radiation particles incident thereon and generate one or more carriers by several mechanisms. One radiation particle can generate 1 to 100000 carriers. The carriers may include electrons and holes. Under an electric field between the portion 197 and the rest of the semiconductor layer 192, the carriers may drift to the sidewall 194b of the via 194 and the portion 197. For example, the holes may drift to the sidewall 194b and the electrons may drift to the portion 197.

The electron shell 120 may include an electron system 121, the electron system 121 being configured to process an electrical signal generated by the collected carriers on the portion 197. The electronic system 121 may include analog circuits such as filter networks, amplifiers, integrators, and comparators, or digital circuits such as microprocessors and memories. The electronic system 121 may include one or more ADCs. The electronic system 121 may be electrically connected to the portion 197 by a via 131 and the electrode 199. The space between the through holes may be filled with a filler material 130, which may increase the mechanical stability of the connection of the electron layer 120 to the radiation absorbing layer 191. Other bonding techniques may also be used to connect the electronic system 121 to the portion 197 without using vias.

The recess 104 of fig. 2A and the through-hole 194 of fig. 2B may have a frustum, prism, pyramid, cuboid, cube, cylinder, or other suitable shape. The detector 100 of fig. 2A or the radiation detector 190 of fig. 2B may have multiple copies of the recess 104 or the through-hole 194, respectively, which may be arranged, for example, in a rectangular array, a honeycomb array, a hexagonal array, or any other suitable array.

Fig. 2C-2E schematically show top views of several examples of the radiation detector 100 or the radiation detector 190 with copies of the recess 104 or the through hole 194, having various shapes and arrangements. The spacing between the copies (e.g., the shortest distance between adjacent copies) may be less than 10 μm, less than 20 μm, or less than 30 μm. The surface area of each of said copies may be in the range 1-10000 μm²Within the range of (1) or any otherAnd suitable dimensions.

Fig. 3 schematically illustrates a process of forming the radiation absorbing layer 200 according to an embodiment.

According to an embodiment, in step 1010, a recess 204 is formed in the semiconductor substrate 210. A portion 207 of the semiconductor substrate 210 extends into the recess 204, and the portion 207 is surrounded by the recess 204. The recess 204 may be used as the recess 104 in fig. 2A. The portion 207 may be used as the portion 107 in fig. 2A.

According to an embodiment, in step 1020, semiconductor nanocrystals 206 are formed in the recesses 204. The semiconductor nanocrystals 206 can have a different composition than the semiconductor substrate 210. That is, the semiconductor nanocrystals 206 differ not only in doping from the semiconductor substrate 210. The semiconductor nanocrystals 206 may be used as the semiconductor nanocrystals 106 of the radiation absorbing layer 110 in fig. 2A. There are a variety of methods for forming the semiconductor nanocrystals 206 in the recesses 204. For example, colloidal synthesis is one method of preparing semiconductor nanocrystals.

According to an embodiment, in step 1030, a first doped semiconductor region 218 is formed in the semiconductor substrate 210.

According to an embodiment, in step 1040, a second doped semiconductor region 219 is formed in the semiconductor substrate 210. The first doped semiconductor region 218 and the second doped semiconductor region 219 form a p-n junction that separates the portion 207 from the remainder of the semiconductor substrate 210. The first doped semiconductor region 218 may surround the second doped semiconductor region 219. The second doped semiconductor region 219 may be in electrical contact with the portion 207.

In an embodiment, the second doped semiconductor region 219 may be formed by doping a portion of the first doped semiconductor region 218. The first doped semiconductor region 218 may be formed by doping a p-type or n-type dopant in the semiconductor substrate 210. The first doped semiconductor region 218 may extend from the surface 210a of the semiconductor substrate 210 to an interface 206a between the recess 204 and the semiconductor substrate 210. The second doped semiconductor region 219 may be coextensive with the first doped semiconductor region 218. The doped semiconductor region 219 may be formed by doping a p-type or n-type dopant in the semiconductor substrate 210, and the dopant used is opposite to the dopant used to form the first doped semiconductor region 218. For example, if the first doped semiconductor region 218 is formed by doping the semiconductor substrate 210 with a p-type dopant, the second doped semiconductor region 219 is formed by doping the semiconductor substrate 210 with an n-type dopant, and vice versa.

As shown in steps 1011-1014 of fig. 4, in an embodiment, forming the recess 204 may include forming a mask 203 on the semiconductor substrate 210, and etching regions of the semiconductor substrate 210 not covered by the mask 203. The mask 203 may be formed on a surface 210b of the semiconductor substrate 210, and the semiconductor substrate 210 may include a semiconductor material such as silicon, germanium, GaAs, or a combination thereof. As shown in step 1013a or 1013b, the mask 203 may be used as an etching mask for forming the recess 204. The mask 203 may comprise a material such as silicon dioxide, silicon nitride, or a metal (e.g., aluminum, chromium). The thickness of the mask 203 may be determined according to the depth of the recess 204 and the etching selectivity (i.e., the ratio of the etching rates of the mask 203 and the semiconductor substrate 210). In an embodiment, the mask 203 may have a thickness of several micrometers. The mask 203 may be formed on the surface 210a by various techniques, such as physical vapor deposition, chemical vapor deposition, spin coating, sputtering, or any other suitable process.

In step 1012, the mask 203 is patterned to have an opening therein exposing the semiconductor substrate 210, as shown in cross-section. The shape and location of the opening corresponds to the shape and location of the footprint of the recess 204 and other recesses formed in step 1013a or 1013 b. If the openings have a square shape (as shown in the top view in step 1012) and are arranged in a rectangular array, the footprint of the recess 204 and other recesses also has a square shape and is arranged in a rectangular array. The formation of the pattern on the mask 203 may involve a photolithography process or any other suitable process. For example, a resist layer may be first deposited (e.g., by spin coating) on the surface of the mask 203, followed by photolithography to form openings. The resolution of the lithography is limited by the wavelength of the radiation used. Photolithography tools using Deep Ultraviolet (DUV) light at wavelengths of approximately 248nm and 193nm can reduce the minimum feature size to approximately 50 nm. Electron beam lithography tools can reduce the minimum feature size to a few nanometers using electron energies from 1keV to 50 keV. In step 1013a or 1013b, the recess 204 and other recesses may be formed in the surface 210b of the semiconductor substrate 210 by etching the portion of the semiconductor substrate 210 not covered by the mask 203 to a desired depth. The height of the portion 207 may be lower than or equal to the depth of the recess 204. The recess 204 may have a frustum, prismatic, pyramidal, rectangular parallelepiped, cubic, or cylindrical shape. In the example of step 1013a, the recesses 204 and other recesses have a pyramidal shape; in the example of step 1013b, the recess 204 and the other recesses have a rectangular parallelepiped shape. The recess 204 may have a smooth surface.

In an embodiment, the etching of the portion of the semiconductor substrate 210 may be performed by wet etching, dry etching, or a combination thereof. Wet etching is an etching process using a liquid phase etchant. The semiconductor substrate 210 may be immersed in an etchant solution and regions not protected by the mask may be removed. The size and shape of the recess 204 and other recesses may be defined not only by the size and shape of the opening of the mask 203 but also by the material of the semiconductor substrate 210, the liquid chemicals or etchants used, the etching rate and duration, and the like. In an embodiment, the semiconductor substrate 210 may be a silicon substrate, and the recess 204 and the other recesses may be formed by anisotropic wet etching using an etchant such as potassium hydroxide (KOH), ethylenediamine pyrocatechol (EDP), tetramethylammonium hydroxide (TMAH), or the like. During anisotropic wet etching of a silicon substrate, a liquid etchant may etch the silicon substrate at different rates depending on the silicon crystal planes exposed to the etchant, so that the recess 204 and other recesses having different shapes and sizes may be formed. In the example of step 1013a, when the surface 210a is a silicon crystalline plane (100), a pyramid-shaped recess 204 with flat and angled etch walls may be formed using a wet etchant such as KOH. In the example of step 1013b, when the surface 210a is a silicon crystal plane (110), a rectangular parallelepiped-shaped recess 204 may be formed using a wet etchant such as KOH.

According to an embodiment, in step 1014, the mask 203 may be removed by wet etching, chemical mechanical polishing, or some other suitable technique after the formation of the recess 204 and other recesses.

Fig. 5 schematically illustrates a process of forming a radiation absorbing layer 400 according to an embodiment.

In step 2010, vias 404 are formed in semiconductor layer 410, the semiconductor layer 410 being supported directly on electrical insulator layer 402. A portion 407 of the semiconductor layer 410 remains in the via 404 and is surrounded by the via 404. Since the via 404 may extend through the entire thickness of the semiconductor layer 410, the portion 407 is electrically isolated from the rest of the semiconductor layer 410 at the end of step 2010. The electrical insulator layer 402 may be used as the electrical insulator layer 198 in fig. 2B. The via 404 may be used as the via 194 in fig. 2B. The portion 407 may be used as the portion 197 in fig. 2B.

In step 2020, semiconductor nanocrystals 406 are formed in the vias 404, according to an embodiment. The semiconductor nanocrystals 406 have a different composition than the semiconductor layer 410. The semiconductor nanocrystal 406 may be used as the semiconductor nanocrystal 196 in fig. 2B. There are a variety of ways to form the semiconductor nanocrystals 406 in the vias 404. For example, colloidal synthesis is one method of preparing semiconductor nanocrystals in industry.

According to an embodiment, in step 2030, an opening 409 is formed through the electrical insulator layer 402 such that the portion 407 is exposed in the opening 409.

According to an embodiment, in step 2040, an electrode 419 is formed in the opening 409. The electrode 419 is in electrical contact with the portion 407. The electrode 419 may be used as the electrode 199 in fig. 2B.

In an embodiment, as shown in steps 2011-2014 of fig. 6, forming the via 404 in the semiconductor layer 410 may include forming a mask 403 on the semiconductor substrate 210, and etching a region of the semiconductor layer 410 not covered by the mask 403. The mask 403 may be formed on a surface 410b of the semiconductor layer 410, and the semiconductor layer 410 may include a semiconductor material such as silicon, germanium, GaAs, or a combination thereof. The mask 403 may be used as an etch mask to form the via 404 and other vias, as shown in step 2013a or step 2013 b. The mask 403 may comprise a material such as silicon dioxide, silicon nitride, carbon, or a metal (e.g., aluminum, chromium). The thickness of the mask 403 may be determined according to the depth of the via 404 and other vias and the etching selectivity (i.e., the ratio of the etching rates of the mask 403 and the semiconductor layer 410). In an embodiment, the mask 403 may have a thickness of several microns. The mask 403 may be formed on the surface 410b by various techniques, such as physical vapor deposition, chemical vapor deposition, spin coating, sputtering, or any other suitable process.

In step 2012, the mask 403 is patterned to have openings therein that expose the semiconductor layer 410, as shown in cross-section. The shape and location of the opening corresponds to the shape and location of the footprint of the through-hole 404 and other recesses formed in step 2013a or step 2013 b. If the openings have a square shape (as shown in the top view in step 2012) and are arranged in a rectangular array, the footprint of the vias 404 and other vias also have a square shape and are arranged in a rectangular array. The formation of the pattern on the mask 403 may involve a photolithography process or any other suitable process. For example, a resist layer may be first deposited (e.g., by spin coating) on the surface of the mask 403, and then photolithography is performed to form an opening. The resolution of the lithography is limited by the wavelength of the radiation used. Photolithography tools using Deep Ultraviolet (DUV) light at wavelengths of approximately 248nm and 193nm can reduce the minimum feature size to approximately 50 nm. Electron beam lithography tools can reduce the minimum feature size to a few nanometers using electron energies from 1keV to 50 keV.

In step 2013a or step 2013b, the via 404 and other vias may be formed in the surface 410b of the semiconductor layer 410 by etching the portion of the semiconductor layer 410 not covered by the mask 403 to a desired depth. The height of the portion 407 may be less than or equal to the depth of the via 404. The via 404 may have a frustum, prism, pyramid, cuboid, cube, or cylindrical shape. In the example of step 2013a, the via 404 has a pyramidal shape; in the example of step 2013b, the via 404 has a rectangular parallelepiped shape. The through-hole 404 may have a smooth surface.

In an embodiment, the etching of the portion of the semiconductor layer 410 may be performed by wet etching, dry etching, or a combination thereof. Wet etching is an etching process using a liquid phase etchant. The semiconductor layer 410 may be immersed in an etchant solution and regions not protected by the mask may be removed. The size and shape of the via 404 may be defined not only by the size and shape of the opening of the mask 403 but also by the material of the semiconductor layer 410, the liquid chemical or etchant used, the etching rate and duration, and the like. The semiconductor layer 410 may be a silicon substrate, and the via hole 404 may be formed by anisotropic wet etching using an etchant such as potassium hydroxide (KOH), ethylenediamine pyrocatechol (EDP), tetramethylammonium hydroxide (TMAH), or the like. During anisotropic wet etching of a silicon substrate, a liquid etchant may etch the silicon substrate at different rates according to a crystal plane of silicon exposed to the etchant, so that the via 404 and other vias having different shapes and sizes may be formed. In the example of step 2013a, when the surface 410b is a silicon crystalline plane (100), a pyramidal via 404 with flat and angled etched walls may be formed using a wet etchant such as KOH. In the example of step 1013b, when the surface 410b is a silicon crystal plane (110), a rectangular parallelepiped-shaped via 404 may be formed using a wet etchant such as KOH.

According to an embodiment, in step 2014, the mask 403 may be removed by wet etching, chemical mechanical polishing, or some other suitable technique after the via 404 is formed.

Fig. 7A schematically illustrates the process of bonding the semiconductor substrate 102 to the electronics layer 120 as shown in fig. 2A. The electron shell 120 may comprise an electron system electrically connected to the second doped semiconductor region 109 and configured to process an electrical signal generated in the radiation absorbing layer 110. The second doped semiconductor region 109 as shown may be bonded to each of the vias 131 by a suitable technique such as direct bonding or flip-chip bonding.

FIG. 7B schematically illustrates the process of bonding the electrical insulator layer 198 to the electronics layer 120 as shown in FIG. 2B. The electronics layer 120 may include an electronics system 121, the electronics system 121 being electrically connected to the electrode 199 and configured to process an electrical signal generated in the radiation absorbing layer 191. The electrodes 199 as shown may be bonded to each of the vias 131 by a suitable technique such as direct bonding or flip-chip bonding.

Direct bonding is a wafer bonding process without any additional intermediate layers (e.g., solder bumps). The bonding process is based on a chemical bond between the two surfaces. Direct bonding can be performed at elevated temperatures, but need not be.

Flip-chip bonding uses solder bumps 132 deposited on contact pads (e.g., contact surfaces of the second doped semiconductor region 109 or the electrode 199 or the via 131). The radiation absorbing layer 110 or 191 or the electron shells 120 are turned over and the second doped semiconductor region 109 or the electrode 199 is aligned with the via 131. The solder bump 132 may be melted to solder the second doped semiconductor region 109 or the electrode 199 and the via 131 together. Any void spaces between the solder bumps 132 may be filled with an insulating material.

According to an embodiment, fig. 8A and 8B each show a component diagram of the electronic system 121. The electronic system 121 may include a first voltage comparator 301, a second voltage comparator 302, a counter 320, a switch 305, a voltmeter 306, and a controller 310.

The first voltage comparator 301 is configured to compare a voltage of an electrode (e.g., the second doped semiconductor region 109 on the semiconductor nanocrystal 106 or the electrode 199 on the semiconductor nanocrystal 106) to a first threshold. The first voltage comparator 301 may be configured to monitor the voltage directly or to calculate the voltage by integrating the current flowing through the electrode over a period of time. The first voltage comparator 301 may be controllably activated or deactivated by the controller 310. The first voltage comparator 301 may be a continuous comparator. That is, the first voltage comparator 301 may be configured to be continuously enabled and continuously monitor the voltage. The first voltage comparator 301 configured as a successive comparator reduces the chance that the system 121 misses the signal generated by the incident radiation particles. The first voltage comparator 301, which is configured as a continuous comparator, is particularly suitable when the intensity of the incident radiation is relatively high. The first voltage comparator 301 may be a clocked comparator, which has the benefit of lower power consumption. The first voltage comparator 301, which is configured as a clocked comparator, may cause the system 121 to miss signals generated by some incident radiation particles. When the intensity of the incident radiation is low, the chance of missing an incident radiation particle is low, because the time interval between two consecutive radiation particles is relatively long. Therefore, the first voltage comparator 301 configured as a clocked comparator is particularly suitable when the incident radiation intensity is relatively low. The first threshold may be 5-10%, 10-20%, 20-30%, 30-40%, or 40-50% of the maximum voltage of an incident radiation particle produced at the semiconductor nanocrystal 106 or 196. The maximum voltage may depend on the energy of the incident radiation particles (i.e., the wavelength of the incident radiation), the material of the radiation absorbing layer 110 or 191, and other factors. For example, the first threshold may be 50mV, 100mV, 150mV, or 200 mV.

The second voltage comparator 302 is configured to compare the voltage to a second threshold. The second voltage comparator 302 may be configured to monitor the voltage directly or to calculate the voltage by integrating the current flowing through the electrode over a period of time. The second voltage comparator 302 may be a continuous comparator. The second voltage comparator 302 may be controllably activated or deactivated by the controller 310. When the second voltage comparator 302 is disabled, the power consumption of the second voltage comparator 302 may be less than 1%, less than 5%, less than 10%, or less than 20% of the power consumption of the second voltage comparator 302 when enabled. The absolute value of the second threshold is greater than the absolute value of the first threshold. The term "absolute value" or "modulus" | x | of a real number x as used herein is a non-negative value of x regardless of its sign. That is to say that the first and second electrodes,the second threshold may be 200% -300% of the first threshold. The second threshold is at least 50% of a maximum voltage of an incident radiation particle generated at the semiconductor nanocrystal 106 or 196. For example, the second threshold may be 100mV, 150mV, 200mV, 250mV, or 300 mV. The second voltage comparator 302 and the first voltage comparator 301 may be the same component. That is, the system 121 may have one voltage comparator that may compare a voltage to two different thresholds at different times.

The first voltage comparator 301 or the second voltage comparator 302 may include one or more operational amplifiers or any other suitable circuit. The first voltage comparator 301 or the second voltage comparator 302 may have a high speed to allow the system 121 to operate at high flux of incident radiation. However, having high speed is usually at the cost of power consumption.

The counter 320 is configured to record a plurality of radiation particles that reach the semiconductor nanocrystal 106 or 196. The counters 320 may be software components (e.g., numbers stored in computer memory) or hardware components (e.g., 4017IC and 7490 IC).

The controller 310 may be a hardware component such as a microcontroller and a microprocessor, etc. The controller 310 is configured to initiate a time delay when the first voltage comparator 301 determines that the absolute value of the voltage equals or exceeds the absolute value of the first threshold (e.g., the absolute value of the voltage increases from below the absolute value of the first threshold to an absolute value that equals or exceeds the first threshold). Absolute values are used here because the voltage can be negative or positive depending on whether the voltage of the cathode or anode of the diode or which electrical contact is used. The controller 310 may be configured to keep disabling the second voltage comparator 302, the counter 320, and any other circuitry not required in the operation of the first voltage comparator 301 until the first voltage comparator 301 determines that the absolute value of the voltage equals or exceeds the absolute value of the first threshold. The time delay may expire before or after the voltage becomes stable (i.e., the rate of change of the voltage is substantially zero). The phrase "the rate of change is substantially zero" means that the time rate of change of the voltage is less than 0.1%/ns. The phrase "the rate of change is substantially non-zero" means that the time rate of change of the voltage is at least 0.1%/ns.

The controller 310 may be configured to start the second voltage comparator during the time delay (including start and expiration). In an embodiment, the controller 310 is configured to start the second voltage comparator at the beginning of the time delay. The term "activate" means to bring a component into an operational state (e.g., by sending a signal such as a voltage pulse or logic level, by providing power, etc.). The term "disable" means to bring a component into a non-operational state (e.g., by sending a signal such as a voltage pulse or logic level, by cutting power, etc.). The operating state may have a higher power consumption (e.g., 10 times higher, 100 times higher, 1000 times higher) than the non-operating state. The controller 310 itself may be disabled until the controller 310 is enabled when the output of the first voltage comparator 301 equals or exceeds the first threshold absolute value.

If, during the time delay, the second voltage comparator 302 determines that the absolute value of the voltage equals or exceeds the absolute value of the second threshold, the controller 310 may be configured to increment the number recorded by the counter 320 by one.

The controller 310 may be configured to cause the voltmeter 306 to measure the voltage upon expiration of the time delay. The controller 310 may be configured to connect the electrodes to electrical ground to reset the voltage and discharge any carriers accumulated on the electrodes. In an embodiment, the electrode is connected to electrical ground after the time delay expires. In an embodiment, the electrode is connected to electrical ground for a limited reset period. The controller 310 may connect the electrode to the electrical ground by controlling the switch 305. The switch may be a transistor such as a Field Effect Transistor (FET).

In an embodiment, the system 121 does not have an analog filter network (e.g., an RC network). In an embodiment, the system 121 has no analog circuitry.

The voltmeter 306 can feed the voltage it measures to the controller 310 as an analog or digital signal.

The system 121 can include a capacitor module 309 electrically connected to the electrode, wherein the capacitor module is configured to collect carriers from the electrode. The capacitor module may include a capacitor in a feedback path of the amplifier. An amplifier so configured is referred to as a capacitive transimpedance amplifier (CTIA). CTIA has a high dynamic range by preventing the amplifier from saturating and improves the signal-to-noise ratio by limiting the bandwidth in the signal path. The carriers from the electrodes are present over a period of time ("integration period") (e.g., at time t, as shown in fig. 7)₀And time t₁In between, or at time t₁And time t₂In between) is accumulated on the capacitor. After the integration period expires, the capacitor voltage is sampled and then reset by a reset switch. The capacitor module may include a capacitor directly connected to the electrode.

FIG. 9 showsThe time variation of the current (upper curve) and the corresponding time variation of the voltage of the electrode (lower curve) caused by carriers generated by the radiation particles incident on the semiconductor nanocrystal 106 or 196 flowing through the electrode is illustrated. The voltage may be an integral of the current with respect to time. At time t₀The radiation particle strikes the semiconductor nanocrystal 106 or 196, a carrier begins to be generated on the semiconductor nanocrystal 106 or 196, a current begins to flow through an electrode of the semiconductor nanocrystal 106 or 196, and an absolute value of a voltage of the electrode or the electrode begins to increase. At time t₁The first voltage comparator 301 determines that the absolute value of the voltage equals or exceeds the absolute value of the first threshold V1, the controller 310 activates a time delay TD1 and the controller 310 may deactivate the first voltage comparator 301 when the TD1 starts. If the controller 310 is at time t₁Previously deactivated, at time t₁The controller 310 is activated. During the TD1, the controller 310 activates the second voltage comparator 302. The term "during" a time delay as used herein means any time between the beginning and expiration (i.e., ending) and in the middle. For example, the controller 310 may activate the second voltage comparator 302 upon expiration of the TD 1. If during the TD1, the second voltage comparator 302 determines at time t₂The absolute value of the voltage equals or exceeds the absolute value of the second threshold, the controller 310 increases the number recorded by the counter 320 by one. At time t_eAll carriers generated by the radiation particles drift out of the radiation absorbing layer 110. At time t_sThe time delay TD1 expires. In the example of FIG. 11, time t_sAt time t_eThen; that is, TD1 expires after all carriers generated by the radiation particles drift out of the radiation absorbing layer 110. At time t_sThe rate of change of voltage is therefore substantially zero. The controller 310 may be configured to expire at TD1 or at time t₂Or any time in between, disables the second voltage comparator 302.

The controller 310 may be configured to cause the voltmeter 306 to measure the voltage upon expiration of the time delay TD 1. In an embodiment, the controller 310 causes the voltmeter 306 to measure the voltage after the time delay TD1 expires and the rate of change of the voltage becomes substantially zero. The voltage at this time is proportional to the number of carriers generated by the radiation particles, which is related to the energy of the radiation particles. The controller 310 may be configured to determine the energy of the radiation particles based on the voltage measured by the voltmeter 306. One way to determine the energy is by binning the voltage. The counter 320 may have a sub-counter for each bin. When the controller 310 determines that the energy of the radiation particle falls into one bin, the controller 310 may increase the number recorded in the sub-counter of the bin by one. Thus, the system 121 is able to detect radiation images and to resolve the radiation energy of each radiation particle.

After the expiration of TD1, the controller 310 connects the electrode to electrical ground for a reset period RST to allow the carriers accumulated on the electrode to flow to ground and reset the voltage. After RST, the system 121 is ready to detect another incident radiation particle. Implicitly, in the example of fig. 11, the rate of incident radiation particles that the system 121 can handle is limited to 1/(TD1+ RST). If the first voltage comparator 301 has been disabled, the controller 310 may enable it at any time prior to the expiration of RST. If the controller 310 has been deactivated, it may be activated before the RST expires.

While various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for purposes of illustration and not limitation, and their true scope and spirit should be determined by the claims herein.