阅读说明：本技术 用于发光二极管中的表面复合速度降低的外延层的再生长 (Regrowth of epitaxial layers with reduced surface recombination velocity for use in light emitting diodes ) 是由 马库斯·布罗尔 迈克尔·格伦德曼 大卫·黄 史蒂芬·卢特根 布莱恩·马修·麦克斯金明 阿努 于 2020-03-30 设计创作，主要内容包括：本文公开了用于发光二极管(LED)阵列设备的方法、系统和设备。在一些实施方案中,LED阵列设备可以包括从层状外延结构蚀刻的多于一个台面。层状外延结构可以包括P型掺杂半导体层、有源层和N型掺杂半导体层。LED阵列设备还可以包括一个或更多个再生长半导体层,包括第一再生长半导体层,所述一个或更多个再生长半导体层可以在多于一个台面的经蚀刻的端面上外延生长。在一些情况下,对于每个台面,第一再生长半导体层可以围绕台面的整个周边覆盖P型掺杂半导体层、有源层和N型掺杂半导体层的经蚀刻的端面。(Methods, systems, and devices for Light Emitting Diode (LED) array devices are disclosed herein. In some embodiments, the LED array device may include more than one mesa etched from the layered epitaxial structure. The layered epitaxial structure may include a P-type doped semiconductor layer, an active layer, and an N-type doped semiconductor layer. The LED array device may further include one or more regrown semiconductor layers, including the first regrown semiconductor layer, which may be epitaxially grown on the etched end face of more than one mesa. In some cases, for each mesa, the first regrown semiconductor layer may cover the etched end faces of the P-type doped semiconductor layer, the active layer, and the N-type doped semiconductor layer around the entire perimeter of the mesa.)

1. A Light Emitting Diode (LED) array apparatus, comprising:

more than one mesa etched from a layered epitaxial structure, wherein the layered epitaxial structure comprises a P-type doped semiconductor layer, an active layer, and an N-type doped semiconductor layer; and

one or more regrown semiconductor layers, including a first regrown semiconductor layer, the one or more regrown semiconductor layers epitaxially grown on the etched end faces of the more than one mesa,

wherein for each mesa, the first regrown semiconductor layer covers the etched end faces of the P-type doped semiconductor layer, the active layer, and the N-type doped semiconductor layer around the entire perimeter of the mesa.

2. The apparatus of claim 1, wherein the one or more regrown semiconductor layers at least partially fill voids between adjacent mesas of the more than one mesa.

3. The apparatus of claim 1, wherein the first regrown semiconductor layer:

comprising a Wide Bandgap (WBG) semiconductor material; and is

Doped to obtain a fermi level associated with the first regrown semiconductor layer acting as an insulator that prevents charge flow between the P-type doped semiconductor layer and the N-type doped semiconductor layer through the first regrown semiconductor layer.

4. The apparatus of claim 1, wherein the first regrown semiconductor layer comprises a material selected from the group consisting of: aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum gallium arsenide (AlGaAs), aluminum indium phosphide (AlInP), aluminum gallium indium phosphide (AlGaInP), or zinc oxide (ZnO) having a higher aluminum content than the active layer.

5. The apparatus of claim 1, wherein a second regrown semiconductor layer is grown as an additional epitaxial layer on the first regrown semiconductor layer.

6. The apparatus of claim 5, wherein:

the first regrown semiconductor layer comprises a Wide Band Gap (WBG) semiconductor material; and is

The second regrown semiconductor layer comprises a Narrow Bandgap (NBG) semiconductor material.

7. The apparatus of claim 6, wherein:

the wide band gap semiconductor material is undoped; and is

The narrow bandgap semiconductor material is doped.

8. The apparatus of claim 7, wherein the one or more regrown semiconductor layers further comprise a transition layer between the first regrown semiconductor layer and etched end faces of the P-type doped semiconductor layer, the active layer, and the N-type doped semiconductor layer.

9. The apparatus of claim 8, wherein the first regrown semiconductor layer comprises a WBG material, the second regrown semiconductor layer comprises a NBG material, and the transition layer comprises a material having a bandgap that is narrower than a bandgap of the WBG material and wider than a bandgap of the NBG material.

10. A method for forming a Light Emitting Diode (LED) array, comprising:

obtaining a layered epitaxial structure, wherein the layered epitaxial structure comprises a P-type doped semiconductor layer, an active layer and an N-type doped semiconductor layer;

etching more than one mesa from the layered epitaxial structure; and

epitaxially growing one or more regrown semiconductor layers on the etched end faces of the more than one mesa, the one or more regrown semiconductor layers including a first regrown semiconductor layer,

wherein for each mesa, the first regrown semiconductor layer covers the etched end faces of the P-type doped semiconductor layer, the active layer, and the N-type doped semiconductor layer around the entire perimeter of the mesa.

11. The method of claim 10 wherein the one or more regrown semiconductor layers completely fill voids between adjacent mesas of the more than one mesa.

12. The method of claim 10, wherein the one or more regrown semiconductor layers partially fill voids between adjacent mesas of the more than one mesa.

13. The method of claim 10, wherein the first regrown semiconductor layer comprises a wide bandgap semiconductor (WBG) material.

14. The method of claim 13, wherein the first regrown semiconductor layer is doped to obtain a fermi level associated with the first regrown semiconductor layer acting as an insulator that prevents charge flow between the P-type doped semiconductor layer and the N-type doped semiconductor layer through the first regrown semiconductor layer.

15. The method of claim 10, wherein a second regrown semiconductor layer is grown as an additional epitaxial layer on the first regrown semiconductor layer.

16. The method of claim 15, wherein:

the first regrown semiconductor layer comprises a Wide Band Gap (WBG) semiconductor material; and is

The second regrown semiconductor layer comprises a Narrow Bandgap (NBG) semiconductor material.

17. The method of claim 16, wherein the one or more regrown semiconductor layers further comprises a transition layer between the first regrown semiconductor layer and etched end faces of the P-type doped semiconductor layer, the active layer, and the N-type doped semiconductor layer.

18. The method of claim 17, wherein the first regrown semiconductor layer comprises a WBG material, the second regrown semiconductor layer comprises a NBG material, and the transition layer comprises a material having a bandgap that is narrower than a bandgap of the WBG material and wider than a bandgap of the NBG material.

19. The method of claim 10, wherein the etched facets of the P-type doped semiconductor layer, the active layer, and the N-type doped semiconductor layer are treated with at least one of a cleaning process, an annealing process, or a flash process prior to growing the first regrown semiconductor layer on the etched facets.

20. A system for forming a Light Emitting Diode (LED) array, comprising:

means for obtaining a layered epitaxial structure, wherein the layered epitaxial structure comprises a P-type doped semiconductor layer, an active layer, and an N-type doped semiconductor layer;

means for etching more than one mesa from the layered epitaxial structure; and

means for epitaxially growing one or more regrown semiconductor layers on the etched end faces of the more than one mesa, the one or more regrown semiconductor layers including a first regrown semiconductor layer,

wherein for each mesa, the first regrown semiconductor layer covers and is in contact with the etched end faces of the P-type doped semiconductor layer, the active layer, and the N-type doped semiconductor layer around the entire perimeter of the mesa.

Background

Aspects of the present disclosure relate to the design of Light Emitting Diodes (LEDs). As the physical size of LEDs is reduced, efficiency losses due to surface recombination become increasingly important as a factor affecting overall performance. Etching a mesa (mesa) from a layered epitaxial structure typically results in an etched mesa facet (etched mesa facet) that includes surface defects. Such undesirable features tend to increase surface recombination velocity and cause dark current, which reduces the light conversion efficiency of the LED. There is a need for techniques to address the problem of surface recombination exhibited in etched mesas to improve the efficiency of LEDs.

Brief Description of Drawings

Aspects of the present disclosure are illustrated by way of example.

FIG. 1 illustrates a simplified diagram showing the basic components of an etched parabolic mesa configured as an LED;

FIG. 2A illustrates more than one vertical mesa;

FIG. 2B illustrates more than one mesa having a trapezoidal profile;

fig. 3 illustrates a regrown semiconductor layer grown as an additional epitaxial layer on the etched end face of more than one mesa in accordance with an embodiment of the present disclosure;

FIG. 4 depicts a close-up area (close up area) at the junction of an N-type doped semiconductor material, a multiple quantum well layer (multiple quantum well layer), a P-type doped semiconductor material, and a regrowth layer;

fig. 5 illustrates a regrown semiconductor layer partially filling the void between adjacent mesas, in accordance with an embodiment of the present disclosure;

fig. 6 illustrates a second regrown semiconductor layer grown as an additional epitaxial layer on the first regrown semiconductor layer in accordance with an embodiment of the present disclosure;

fig. 7 depicts a close-up region at the junction of the N-type doped semiconductor material, the multiple quantum well layer, and the P-type doped semiconductor material of the LED and the first regrowth layer and the second regrowth layer grown on the end face of the LED;

FIG. 8 is an energy band diagram along the lateral axis of the semiconductor structure shown in FIG. 7;

FIG. 9 illustrates a transition layer grown on the mesa facets to provide a smooth film (smooth film) prior to the growth of the first regrown semiconductor layer, in accordance with an embodiment of the present disclosure;

fig. 10 is a flow chart presenting illustrative steps for regrowing an epitaxial layer on an etched facet configured as a mesa of an LED, in accordance with various embodiments of the present disclosure;

11A and 11B illustrate the mesa array during an exemplary cleaning process that may be performed prior to growth of one or more regrown semiconductor layers;

fig. 12 provides an image depicting an array of mesas that have undergone an annealing process;

FIGS. 13A and 13B depict an array of mesas having a regrown layer epitaxially grown on the mesa facets;

FIGS. 14A and 14B depict a mesa structure that has not undergone a BOE clean process prior to the growth of a regrowth layer on the epitaxial structure;

fig. 15A provides a close-up view of the interface between the regrown layer of mesa sidewalls and the epitaxial layer;

FIGS. 15B-15D provide images of the elemental layout (elemental mapping) of the interface between the regrowth layer of the mesa sidewalls and the epitaxial layer;

fig. 16 provides a graph showing the distribution of elements throughout the depth of the interface between the regrown layer of the mesa sidewalls and the epitaxial layer;

FIG. 17 provides an image of a mesa structure that has undergone a BOE cleaning process prior to application of a regrowth layer;

fig. 18A provides a close-up view of the interface between the regrown layer of mesa sidewalls and the epitaxial layer;

18B-18D provide images of the elemental layout of the interface between the regrown layer of the mesa sidewalls and the epitaxial layer; and

fig. 19 provides a graph showing the distribution of elements throughout the depth of the interface between the regrown layer of mesa sidewalls and the epitaxial layer.

Detailed Description

The present disclosure presents various embodiments in which regrowth of the epitaxial layer is used to passivate the etched facets of the LED mesa in a manner that provides an improved crystal interface at the etched facets to reduce dangling bonds (dangling bonds) and other surface defects. Doing so reduces the current lost due to non-radiative recombination associated with surface states, i.e., at or near the etched end face of the LED mesa. In other words, the surface recombination velocity can be significantly reduced and the efficiency loss of the LED due to surface recombination can be greatly mitigated.

Fig. 1 illustrates an example of an LED 100 including a parabolic mesa structure. According to an embodiment of the present disclosure, the LED 100 emits incoherent light. The LED 100 may be a micro LED having a lateral dimension (lateral dimension) or diameter of less than 10 microns. The LED 100 may be made of an inorganic material such as a multi-layer semiconductor material. For example, the layered semiconductor light emitting device may include multiple layers of III-V semiconductor materials. The III-V semiconductor material may include one or more group III elements such As aluminum (Al), gallium (Ga), or indium (In) In combination with a group V element such As nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb).

Layered semiconductor devices can be fabricated by growing multiple epitaxial layers on a substrate in one or more chambers using techniques such as Molecular Beam Epitaxy (MBE), Metal Organic Vapor Phase Epitaxy (MOVPE), also known as organometallic vapor phase epitaxy (OMVPE) or Metal Organic Chemical Vapor Deposition (MOCVD), or Physical Vapor Deposition (PVD), e.g., Pulsed Laser Deposition (PLD). For example, the semiconductor layers may be grown layer-by-layer on a substrate having a particular lattice orientation, such as sapphire, quartz, gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP). The silicon substrate may be cut in a specific direction to expose a specific plane as a growth surface.

LED 100 may include a substrate layer 110, and substrate layer 110 may include, for example, aluminum oxide (Al)₂O₃) A substrate ("sapphire" substrate) or a GaN substrate. Semiconductor layer 120 may be grown on substrate layer 110. The semiconductor layer 120 may comprise a III-V material, such as GaN, and may Be p-doped (e.g., doped with Mg, Ca, Zn, or Be) or n-doped (e.g., doped with Si or Ge). In the example shown in fig. 1, layer 120 is an N-type doped semiconductor material. One or more active layers 130 may be grown on the semiconductor layer 120. The active layer 130 may include one or more indium gallium nitride (InGaN) layers, one or more aluminum indium gallium phosphide (AlInGaP) layers, or one or more GaN layers, which may form a single layerOne or more heterostructures, such as one or more quantum wells. Here, the active layer 130 includes a Multiple Quantum Well (MQW) layer. The semiconductor layer 140 may be grown on the active layer 130. The semiconductor layer 140 may comprise a III-V material such as GaN, and may Be p-doped (e.g., doped with Mg, Ca, Zn, or Be) or n-doped (e.g., doped with Si or Ge). In the example shown in fig. 1, layer 140 is a P-type doped semiconductor material. The semiconductor layer 120 and the semiconductor layer 140 sandwich the active layer 130 to form a light emitting diode. For example, the LED 100 may include an InGaN layer between a p-type GaN layer doped with magnesium and an n-type GaN layer doped with silicon or oxygen. In some embodiments, the LED 100 may include a layer of AlInGaP between a p-type AlInGaP layer doped with zinc or magnesium and an n-type AlInGaP layer doped with selenium, silicon, or tellurium.

To make contact with the semiconductor layer 120 (e.g., n-GaN layer) of the diode and to more efficiently extract light emitted by the active layer 130 from the LED 100, the semiconductor layer may be etched to expose the semiconductor layer 120 and form a mesa structure including the layer 120 and 140. The mesa structure may confine carriers within the implanted region of the device. Etching the mesa structures may result in the formation of mesa sidewalls, also referred to herein as end surfaces, which may not be parallel to the growth plane, or in some cases orthogonal to the growth plane. The reflective layer 170 may be formed on sidewalls of the mesa structure. The reflective layer 170 may include an oxide layer, such as silicon oxide (SiO)₂) Layers, and may act as a reflector to reflect emitted light out of LED 100. Contacts 180 may be formed on the semiconductor layer 120 and may serve as electrodes of the LED 100, which contacts 180 may include a metal, such as Al, Au, Ni, Ti, or any combination thereof, or a non-metallic conductive material, shown in this figure as N-contacts. In addition, another contact 190, such as a metal layer of Al/Ni/Au, shown in this figure as a P contact, can be formed to make ohmic contact with the semiconductor layer 140 to serve as another electrode of the LED 100.

When a voltage signal is applied to the contact layers 180 and 190, electrons and holes may recombine in the active layer 430, where the recombination of the electrons and holes may result in photon emission. The wavelength and energy of the emitted photons may depend on the energy band gap between the valence band and the conduction band in the active layer 130. For example, an InGaN active layer may emit green or blue light, while an AlInGaP active layer may emit red, orange, yellow, or green light. The emitted photons may be reflected by the reflective layer 170 and may exit the LED 100, for example, from the bottom side (e.g., substrate 110) as shown in fig. 1.

In some embodiments, the LED 100 may include a mesa of another shape, such as a planar shape, a vertical shape, a conical shape, a semi-parabolic shape, or a parabolic shape, wherein a base area (base area) of the mesa may be circular, rectangular, hexagonal, or triangular. For example, the LED may include mesas of curved shapes (e.g., parabolic shapes) and non-curved shapes (e.g., conical shapes). The mesas may be truncated or non-truncated.

Fig. 2A illustrates more than one vertical mesa 200A. In contrast to the parabolic mesa shown in fig. 1, mesa 200A shown in fig. 2A has vertically oriented sidewalls or end surfaces. In contrast to fig. 1, the orientation of the mesa 200A has also been flipped in fig. 2A. Here, light from each LED exits the mesa from the "top" side of the figure. More than one mesa 200A shown in fig. 2A may be formed as an array of LEDs that contribute light to the display. For example, the light for each mesa may contribute light for one pixel of the display or one color of a pixel.

Each of the mesas 200A may be a light emitter in a light source. In some embodiments, the mesa 200A may be a micro LED made of an inorganic material, such as multiple layers of semiconductor material. The layered semiconductor light emitting device may include multiple layers of III-V semiconductor materials. The III-V semiconductor material may include one or more group III elements such As aluminum (Al), gallium (Ga), or indium (In) In combination with a group V element such As nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb). When the group V element in the III-V semiconductor material includes nitrogen, the III-V semiconductor material is referred to as a ill-nitride material. The layered semiconductor light emitting device may be fabricated by using a technique such as Vapor Phase Epitaxy (VPE), Liquid Phase Epitaxy (LPE), Molecular Beam Epitaxy (MBE), or Metal Organic Chemical Vapor Deposition (MOCVD)A plurality of epitaxial layers are grown on a substrate. For example, a layer of semiconductor material may be grown layer-by-layer on a substrate having a particular lattice orientation (e.g., polar, non-polar, or semi-polar), such as a GaN substrate, GaAs substrate, or GaP substrate, or substrates including, but not limited to, the following: sapphire, silicon carbide, silicon, zinc oxide, boron nitride, lithium aluminate, lithium niobate, germanium, aluminum nitride, lithium gallate, partially substituted spinel or shared beta-LiAlO₂A substrate of a structured quaternary tetragonal oxide (quaternary tetragonal oxide), wherein the substrate can be cut in a specific direction to expose a specific plane as a growth surface.

In the example shown in fig. 2A, each of the mesas 200A may include an N-type doped semiconductor layer 220 and a P-type doped semiconductor layer 240. The N-type doped semiconductor layer 220 may include a III-V material, such as GaN, and may Be p-doped (e.g., doped with Mg, Ca, Zn, or Be) or N-doped (e.g., doped with Si or Ge). The P-type doped semiconductor layer 240 may include a III-V material, such as GaN, and may Be P-doped (e.g., doped with Mg, Ca, Zn, or Be) or n-doped (e.g., doped with Si or Ge). One or more Multiple Quantum Well (MQW) layers 230 may be grown between the N-type doped semiconductor layer 220 and the P-type doped semiconductor layer 240 to form an active region. The MQW layer 230 may also be referred to herein as an active layer or active layers. In some embodiments, MQW layer 230 may be or may include one or more layers of Quantum Dots (QDs) or quantum wires (qwires). The active region formed by MQW layer 230 may form the light emitting region of mesa 200A. The MQW layer 330 may include group III-V materials, such as one or more InGaN layers, one or more AlInGaP layers, and/or one or more GaN layers, which may form one or more heterostructures. In an exemplary embodiment, each of the mesas 200A may include an InGaN layer between a P-type GaN layer doped with magnesium and an N-type GaN layer doped with silicon or oxygen. In other embodiments, each of the mesas 200A may include a layer of AlInGaP between a P-type AlInGaP layer doped with zinc or magnesium and an N-type AlInGaP layer doped with selenium, silicon, or tellurium.

In some embodiments not shown, mesa 200A may include a substrate, which may include, for example, a sapphire substrate or a GaN substrate. Additional components, such as P-contacts, N-contacts, reflector layers, conductive layers, etc., may be present, however, for ease of illustration, are not explicitly shown.

Although fig. 2A presents a cross-sectional view, the array of mesas 200A may include a two-dimensional array of mesas, each mesa corresponding to an LED device. As previously mentioned, each LED may have a lateral dimension or diameter of less than 10 microns. According to various embodiments, the voids or trenches (trenches) between two adjacent mesas may be in the range of 0.05 microns to 7 microns from a plan view or a top-down view. This supports a wide range of pitch distances, i.e. the center-to-center distance between two adjacent mesas. The number of mesas included in the array may vary. In various embodiments, the number of mesas along the first dimension may be thousands, and the number of mesas along the second dimension may also be thousands. By way of example only, the array may include 1,500 mesas by 1000 mesas. In another example, the array may include 2,000 mesas by 1500 mesas.

Although fig. 2A illustrates an example of a vertical mesa associated with a cylindrical three-dimensional shape, other shapes are possible. By way of example only, fig. 2B illustrates more than one mesa 200B having a trapezoidal profile. Mesa 200B may be identical to mesa 200A except for the shape of each mesa. Other types of mesas are also possible, including mesas having more complex profiles, such as combinations of shapes, such as a combination of rectangular profiles and trapezoidal profiles. As shown, both mesas 200A and 200B form an end surface 250 along a surface of each mesa. According to various embodiments of the present disclosure, for mesas of different shapes and profiles, the use of a regrown semiconductor layer on the end faces of the mesa may be employed to reduce non-radiative recombination.

Surface defects on the end face 250 of each mesa may contribute to undesirable surface recombination, which reduces the efficiency of each LED. At the end face 250, the atomic lattice structure of the N-type doped semiconductor layer 220 and the P-type doped semiconductor layer 240 ends abruptly as a result. At these surfaces, atoms of the semiconductor material lack neighbors to which bonds can be attached. This results in a "dangling bond" characterized by unpaired valence electrons. These dangling bonds create energy levels within the bandgap of the semiconductor material that would otherwise be absent, which causes non-radiative electron-hole recombination at or near the surface of the semiconductor material. A measure of the ease with which such recombination occurs is the Surface Recombination Velocity (SRV). Thus, the increased SRV is associated with non-radiative recombination, i.e., the recombination of electrons and holes without generating photons, which reduces the efficiency of the LED.

The effect of non-radiative recombination is particularly pronounced when the physical size of each mesa is reduced to a diameter of 10 microns and below, and more particularly, to a diameter of 5 microns and below. In larger LED devices, e.g. larger than 50 microns in diameter, the LED area affected by surface recombination is proportionally small. For example, assuming a diffusion length of 1 micron, the effects of surface recombination may be limited to those regions within the mesa facets of about 1 micron. For a device with a diameter of 50 microns, only a small portion of the interior of the device is within 1 micron of the device surface, i.e., the mesa facet. The regions of the device affected by surface recombination collectively do not constitute a significant portion of the span of the MQW layer 230. In other words, the desired radiative recombination (which releases photons) at the MQW layer 230 dominates the percentage of the total recombination events for the LED device. In contrast, for devices having very small physical dimensions, such as 2 microns in diameter, the area affected by surface recombination can be quite significant given a diffusion length of 1 micron. In such a case, a large percentage of the total recombination events may be affected by the recombination effects of the non-radiative surface near the mesa facet. Therefore, the possibility of efficiency degradation is particularly severe for micro LEDs.

To exacerbate the problem, LEDs typically cannot operate at high current densities sufficient to avoid the problems associated with high surface recombination velocities. The diffusion length of a given material may vary depending on the current density at which the device operates. Higher current density (example)E.g. in amperes/cm²In units) is associated with a lower surface recombination velocity. Theoretically, the surface recombination velocity can be reduced by increasing the current density. For example, the laser device may be operated at high current densities, for example at kiloamps/cm²In order to reduce the surface recombination velocity. In contrast, LED devices generally cannot operate at such high current densities. Instead, LED devices are typically at 1 ampere/cm²-100 amperes/cm²Operate within the range of (1). Therefore, operation at very high current densities may not be feasible, and the need for alternative strategies to reduce surface recombination velocity in LED devices is even greater. According to various embodiments of the present disclosure, one or more regrown semiconductor layers on the end facets of a micro LED may be used to reduce the surface recombination velocity and significantly improve the LED efficiency.

Fig. 3 provides more than one mesa 300 with a regrown semiconductor layer 360 grown as additional epitaxial layers on the etched end faces of the more than one mesa 300 in accordance with embodiments of the present disclosure. More than one mesa 300 may be or may include a material similar to the material of mesas 200A and 200B. For example, mesas 300 may each include an N-type doped semiconductor layer 320, a P-type doped semiconductor layer 340, and a MQW layer 330 grown between N-type doped semiconductor layer 320 and P-type doped semiconductor layer 340.

In the present embodiment, regrown semiconductor layer 360 covers the etched end faces of P-type doped semiconductor layer 340, MQW layer 330, and N-type doped semiconductor layer 320 around the entire perimeter of the mesa and is in contact with the etched end faces of P-type doped semiconductor layer 340, MQW layer 330, and N-type doped semiconductor layer 320. For example, each vertical mesa shown in fig. 3 may have a generally cylindrical shape. Thus, the regrown semiconductor layer 360 may completely surround each vertical mesa such that the peripheral sidewall of the cylindrical shape of each mesa is covered by the regrown semiconductor layer 360. The cross-sectional view presented in fig. 3 illustrates such an arrangement. In the particular embodiment shown in this figure, the regrown semiconductor layer 360 completely fills the void between adjacent mesas.

The growth of the regrown semiconductor layer 360 may be performed using a variety of techniques including, for example, Molecular Beam Epitaxy (MBE), Metal Organic Vapor Phase Epitaxy (MOVPE), or Physical Vapor Deposition (PVD), such as Pulsed Laser Deposition (PLD). However, the general strategy of growing a regrown semiconductor layer 360 as an additional epitaxial layer on the etched surface of the mesa to reduce the surface recombination velocity is not necessarily limited to a particular growth technique such as MBE or MOVPE.

Various surface preparation techniques may be used to remove defects or otherwise improve the condition of the mesa facet surfaces for epitaxial regrowth. These surface preparations may include plasma cleaning, thermal desorption in high or ultra high vacuum, H₂、NH₃Phosphine, arsine overpressure at high temperature, in situ Cl₂Etching, and the like. In the case of MOCVD, the surface preparation technique may include, for example, annealing at high temperatures (e.g., in the range of about 900 degrees celsius). In the case of MBE, the surface preparation technique may include, for example, (1) the use of hydrogen H₂Cleaning in situ and/or annealing in Ultra High Vacuum (UHV), e.g. below 10^-7A pressure of pascal; and (2) gallium (Ga) flash evaporation or Ga polishing.

In addition to cleaning and removing material, the surface may also be rebuilt. For example, pressure treatment with group V materials using an extended high temperature step near the growth temperature of the regrown material may be used in order to build up an ordered surface. The progress of the surface reconstruction can be monitored using in situ techniques such as Reflection High Energy Electron Diffraction (RHEED) or ellipsometry (SE). A rapid quenching step may also be used and/or the temperature may be increased for the subsequent deposition step.

A regrowth mask 370 may be used to ensure area-selective growth. As shown in fig. 3, a regrowth mask 370 may be deposited on top of each mesa (shown on the bottom side of fig. 3 because the orientation of the mesa is "flipped" in the figure) prior to the regrowth step. Although not shown in fig. 3 and subsequent figures, a P-contact layer may be present on the P-type doped semiconductor layer 340. A regrowth mask 370 may be deposited on such a P-contact layer (e.g., a metal layer).According to various embodiments, the regrowth mask 370 may comprise, for example, SiO₂Or SiN_xThe material of (1). The regrowth mask 370 ensures that the regrown semiconductor layer 360 grows only at selected locations. After the one or more regrown semiconductor layers 360 are established, the regrowth mask 370 may be etched away. Additionally or alternatively, other techniques may be used to remove unwanted or excess regrown material from locations where regrowth is not desired. Such removal techniques may include planarization, such as Chemical Mechanical Planarization (CMP).

The epitaxial growth of the one or more regrown semiconductor layers 360 may be designed to take into account a number of factors. In some cases, the material may induce local strain at the regrowth interface. In other cases, the initially grown layer may become diffused. The one or more regrown semiconductor layers 360 may be configured to:

energy landscapes (e.g., large band gap materials next to the original crystal);

defect density to reduce non-radiative recombination;

electrostatic control by doping (inducing band bending in the original material to make minority carriers less likely to be transported into interface traps);

lattice matching to the starting material (e.g., wurtzite on wurtzite or 001 wurtzite on 111 sphalerite material); and/or

Environmental sensitivity (e.g., an Al-free surface that prevents oxidation, or a finished surface (finish) that has an Al surface and is purposefully oxidized in a subsequent step).

According to some embodiments, the one or more regrown semiconductor layers 360 may include a Wide Bandgap (WBG) semiconductor material and/or a narrow bandgap (NGB) semiconductor material. Here, WBG refers to a semiconductor material having a relatively large band gap, for example, in the range of 2 electron volts (eV) to 4 electron volts. NGB refers to a semiconductor material having a relatively small bandgap, for example less than 1.11 eV. Conventional semiconductors such as silicon have a bandgap in the range of 1eV to 1.5 eV. In some embodiments, regrown semiconductor layer 360 may include undoped semiconductor material. In other embodiments, regrown semiconductor layer 360 may include a doped semiconductor material. Regrown semiconductor layer 360 may also include "lightly doped" semiconductor material. For example, the regrown semiconductor layer 360 may have a dopant concentration that is significantly lower than the dopant concentration of the N-doped semiconductor layer 320 (or the P-doped semiconductor layer 340). In various embodiments, regrown semiconductor layer 360 may include a material selected from the group consisting of: aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum gallium arsenide (AlGaAs), aluminum indium phosphide (AlInP), aluminum gallium indium phosphide (AlGaInP), or zinc oxide (ZnO) having a higher aluminum content than the active layer.

According to various embodiments of the present disclosure, the material of the regrown semiconductor layer 360 may be selected to match or be similar to the material of the N-type doped semiconductor layer 320 and/or the P-type doped semiconductor layer 340 of the LED, such that a "perfect" or near perfect crystal interface is achieved. Similar materials allow for a consistent lattice structure to be continued at the interface between the regrown semiconductor layer 360 of the etched mesa structure and the N-doped semiconductor layer 320 (or at the interface between the regrown semiconductor layer 360 and the P-doped semiconductor layer 340). Such an interface minimizes the occurrence of dangling bonds to effectively reduce Surface Recombination Velocity (SRV). For example, if the N-type doped semiconductor layer 320 and the P-type doped semiconductor layer 340 include a III-V semiconductor material, the regrown semiconductor layer 360 may also include a III-V semiconductor material.

The growth conditions for the one or more regrown semiconductor layers 360 may be different from the growth conditions for the N-type doped semiconductor layer 320 and the P-type doped semiconductor layer 340 of the etched mesa structure for the LED. The N-type doped semiconductor layer 320 and the P-type doped semiconductor layer 340 of the LED are grown in an upward direction from a substrate layer (e.g., substrate layer 110 in fig. 1). In contrast, the regrown semiconductor layer 360 grows primarily in the lateral direction from the end face of the mesa structure outward. Thus, the growth conditions for regrowing the semiconductor layer 360 may be optimized to increase the lateral growth rate, as opposed to the upward growth rate relative to the substrate layer. Optimization of the lateral growth rate may be achieved by controlling factors such as the molecular composition of the regrown semiconductor layer 360, e.g., the ratio of group III elements to group V elements in the material ("III/V ratio"), the temperature at which regrowth occurs, and by aligning the offcuts (offcuts) to the growth plane.

For example, the material selected for the one or more regrown semiconductor layers 360 may include a group III-AsP or group III-N material, including AlInGaP, AlInGaP (As), AlInGaPN, AlInGaN, (B) AlInGaN. These materials may also be doped with additives such as Si, Mg, C, Te, etc. In other examples, the materials selected for the one or more regrown semiconductor layers 360 may include group II-group VI materials, such as ZnS and ZnO. The material may be deposited using growth conditions that may differ from typical growth plane growth conditions such that:

1. altering the relative growth rate on the exposed end face as compared to the original end face of the material;

2. the quality of the material is improved; and/or

3. Heterostructures with controlled thickness are built.

As an example, GaN can be generally treated in MOCVD at high NH levels₃Growth under partial pressure so as to promote lateral growth and suppress growth in the 001 direction to obtain a smooth film. However, according to embodiments of the present disclosure, regrown layer/film 360 may alternatively be at a significantly lower NH₃Growth under partial pressure to obtain a smooth film on the sidewalls of the device (e.g., LED device) or to inhibit bridging when grown in trenches with high aspect ratios. An example of such a trench may be a void between each mesa 200A and 200B shown in fig. 2A and 2B.

Fig. 4 depicts an enlarged version of the close-up area 380 depicted in fig. 3. As shown, close-up region 380 illustrates the junction of N-type doped semiconductor layer 320, MQW layer 330, P-type doped semiconductor layer 340, and regrowth layer 360. According to an embodiment, regrowth layer 360 may include a doped semiconductor material. Here, the regrown semiconductor layer 360 may be doped to obtain a fermi level associated with the regrown semiconductor layer 360 acting as an insulator that prevents shorting of the LED-i.e., shorting caused by charge flow between the P-type doped semiconductor layer 340 and the N-type doped semiconductor layer 320 through the regrown semiconductor layer 360.

For example, referring again to fig. 4, if an N-type doped semiconductor layer 320 is used to regrow the semiconductor layer 360, the structure shown in fig. 4 may have a first p-N junction and potentially a second p-N junction. The first p-n junction is the LED itself; i.e., across the junction of P-doped semiconductor layer 340 and MQW layer 330. A second P-N junction will potentially be formed across the P-type doped semiconductor layer 340 and the regrown semiconductor layer 360 (which in this example comprises an N-type doped semiconductor material). However, the materials and doping levels may be selected for the various layers to control the respective fermi levels such that the turn-on voltage of the first p-n junction is significantly lower than the turn-on voltage of the second p-n junction. In the presence of a charge potential, the first p-n junction will conduct and the second p-n junction will not. That is, charge will flow with respect to the first p-n junction but not with respect to the second p-n junction. Therefore, regrown semiconductor layer 360 will act as an insulator to prevent shorting of the LED.

Fig. 5 illustrates a mesa array 500 having more than one mesa with a regrown semiconductor layer 560 partially filling the gap between adjacent mesas in accordance with an embodiment of the present disclosure. Here, although the space between adjacent mesas is only partially filled, the regrown semiconductor layer 560 still effectively passivates the exposed end faces of the mesa structures. Again, similar materials may be used to allow for a consistent lattice structure to continue at the interface between the regrown semiconductor layer 560 and the N-doped semiconductor layer 520 of the etched mesa structure (or at the interface between the regrown semiconductor layer 560 and the P-doped semiconductor layer 520). This significantly reduces the appearance of dangling bonds at the mesa end face, especially near the MQW, thereby mitigating the deleterious effects of surface recombination.

The choice between completely filling and partially filling the gaps between adjacent mesas may involve balancing the feasibility versus performance gain (performance gain) associated with each approach. Factors that affect the feasibility and performance gain of the respective methods include the pitch (i.e., center-to-center distance between adjacent mesas) and the shape of the mesas.

Fig. 6 provides an array of mesas 600 having a second regrown semiconductor layer 656, the second regrown semiconductor layer 656 grown as an additional epitaxial layer on the first regrown semiconductor layer 660 in accordance with an embodiment of the present disclosure. Thus, by employing two or more different regrown semiconductor layers, a heteroregrown structure can be achieved. This may be referred to as a "heterostructure" variation of the regrown semiconductor structure. The plurality of regrown semiconductor layers may include different materials. By way of example only, referring to fig. 6, the first regrown semiconductor layer 660 may include a Wide Bandgap (WBG) material and the second regrown semiconductor layer 665 may include a Narrow Bandgap (NBG) material. In this example, the WBG material may provide an insulating function to prevent the regrown semiconductor layer from acting as a conduit for charge movement between the P-type doped semiconductor layer 640 and the N-type doped semiconductor layer 620 of the LED. The WBG material may also provide a passivation function to avoid dangling bonds at the mesa faces, significantly reducing the surface recombination velocity.

According to some embodiments, the WBG material of the first regrown semiconductor layer 660 may be undoped, P-type doped, or N-type doped. The NBG material of the second regrown semiconductor layer 665 may be undoped, P-doped, N-doped, or doped such that the material is in a mid-gap state (mid-gap state). That is, by careful control of the fermi level, the NBG material can even be designed to act as an insulator. Various combinations of such materials are possible. Some examples of such combinations are listed below.

In a first particular embodiment, the first regrown semiconductor layer 660 comprises undoped WBG material and the second regrown semiconductor layer 665 comprises NBG material in an interstitial state. In a second particular embodiment, the first regrown semiconductor layer 660 comprises an undoped WBG material and the second regrown semiconductor layer 665 comprises an NBG material that is P-type doped. In a third particular embodiment, the first regrown semiconductor layer 660 comprises an undoped WBG material and the second regrown semiconductor layer 665 comprises an NBG material that is N-type doped.

An example of a heterostructure can be formed by first depositing an environmentally sensitive undoped WBG material followed by a less environmentally sensitive doped material NBG as the electrostatic control layer. In a particular embodiment, aluminum arsenide (AlAs) may be deposited first at 10nm to 100nm, followed by gallium arsenide (GaAs) doped with silicon (Si) at 10nm to 100 nm.

Additionally, multiple regrown semiconductor layers may be implemented using a variety of techniques. One such technique is delta doping. Delta doping involves the use of thin layers of high dopant concentration during growth to obtain a doping profile (doping profile) that resembles the delta function. For example, delta doping can be achieved by impurity deposition with growth interruption during, for example, Molecular Beam Epitaxy (MBE).

Fig. 7 depicts a close-up region 680 as zoomed in from fig. 6. Close-up region 680 illustrates the junction of N-type doped semiconductor layer 620, MQW layer 630, and P-type doped semiconductor layer 640, and first regrowth layer 660 and second regrowth layer 665 grown on the end faces of the mesa structures. A lateral axis or "cut line" may be envisioned as a cut across the N-type doped semiconductor layer 620 (or P-type doped semiconductor layer 640), first regrowth layer 660, and second regrowth layer 665 of the LED.

Fig. 8 provides a band diagram 800 of the semiconductor structure of the close-up region 680 shown in fig. 7. Here, the x-axis is the same horizontal axis shown in fig. 7, cut across different materials, such as the N-doped semiconductor layer 620 (or the P-doped semiconductor layer 640), the first regrown semiconductor layer 660, and the second regrown semiconductor layer 665 of the LED. The y-axis is the magnitude of the energy of the electron. As shown, the N-type doped semiconductor layer 620 of the LED may comprise a Narrow Bandgap (NBG) material characterized by a narrow gap between a lower boundary of a conduction band and an upper boundary of a valence band of the material. In contrast, and in accordance with embodiments of the present disclosure, the first regrown semiconductor layer 660 may include a Wide Bandgap (WBG) material characterized by a wide gap between a lower boundary of a conduction band and an upper boundary of a valence band of the material. Further, in accordance with embodiments of the present disclosure, second regrown semiconductor layer 665 may comprise an NBG material, again characterized by a narrow gap between a lower boundary of the conduction band and an upper boundary of the valence band of the material.

According to various embodiments of the present disclosure, the selection of materials for the different layers allows for electrostatic control of the overall structure. In particular, the curvature of the lower boundary of the conduction band and the upper boundary of the valence band near the interface between adjacent materials can be controlled by selecting a plurality of various materials.

Fig. 9 illustrates a structure 900 according to an embodiment of the present disclosure, the structure 900 providing a transition layer 980 grown on the mesa facets prior to the growth of the first regrown semiconductor layer 960 to provide a smooth film. The transition layer 980 may also be considered one of the regrowth layers. Thus, in fig. 9, the one or more regrown semiconductor layers include a transition layer 980, a first regrown semiconductor layer 960, and a second regrown semiconductor layer 965. The first regrown semiconductor layer 960 may have a similar construction or material as the first regrown semiconductor layer 660, and the second regrown semiconductor layer 965 may have a similar construction or material as the second regrown semiconductor layer 665. In some cases, the material selected for the first regrown semiconductor layer 960 may be characterized by low mobility. For example, the first regrown semiconductor layer 960 may include a material characterized by low mobility that includes aluminum (Al). That is, once deposited, the molecules of the material cannot travel far and therefore cannot move to locations such as pits (coaters) to fill depressions and level matte surfaces. As a result, non-uniformities, i.e., undesirable surface features, tend to be repeated when depositing a layer of immobile regrown material. To address this problem, a transition layer 980 having a relatively high mobility may be deposited on the mesa facets to provide a smooth surface on which the first regrown semiconductor layer 960 may be grown. According to one embodiment, the transition layer 980 may comprise a moderately narrow bandgap material.

In one embodiment, first regrown semiconductor layer 960 may include a Wide Bandgap (WBG) material, second regrown semiconductor layer 965 may include a Narrow Bandgap (NBG) material, and transition layer 980 may include a material with a moderately narrow bandgap that is narrower than the WBG material of first regrown layer 960, but wider than the NBG material of second regrown layer 965. For example, the first regrown semiconductor layer 960 may include aluminum gallium nitride (Al)_xGa_1-xN), the second regrown semiconductor layer 965 may include gallium nitride (GaN), and the transition layer 980 may include aluminum indium gallium nitride (AlInGaN). In this example, when the aluminum (Al) content of the first regrown layer 960 is greater than a certain threshold, such as when [ AlN [ ]]>0.2 (i.e., when x>0.2), the transition layer 980 may be particularly useful.

Fig. 10 provides a flow chart of a rendering method 1000. Method 1000 provides illustrative steps for regrowing semiconductor layers, such as regrowth layers 360, 560, 660, 665, 960, and 965 on an etched facet configured as a mesa of an LED in accordance with various embodiments of the present disclosure. The following discussion of method 1000 will be discussed with reference to fig. 11A, 11B, 12, 13A, and 13B for illustrative purposes only.

Method 1000 may include step 1010. In step 1010, layers of an epitaxial structure used to form a mesa structure of the LED may be grown on the substrate. For example, the layers may include N-type doped semiconductor layers, such as N-type doped semiconductor layers 120, 220, 320, 520, 620, and 920, one or more MQW layers, such as MQW layers 130, 230, 330, 530, 630, and 930, and P-type doped semiconductor layers, such as P-type doped semiconductor layers 140, 240, 340, 540, 640, and 940. Additional layers may also be formed. For example, a conductive layer such as a P metal layer may be formed on top of the P-type doped semiconductor layer.

At step 1020, an array of mesa shapes may be etched from the epitaxial structure, which exposes mesa facets, such as facet 250. In some embodiments, an etching process, such as dry etching in an Inductively Coupled Plasma (ICP) etch or Reactive Ion Etch (RIE) system, may be used to etch the epitaxial structure. The etching may continue through the conductive layer (if present) and through one or more of the underlying epitaxial layers. For example, the etching may continue through the P-type doped semiconductor layer, through the one or more MQW layers, and to the N-type doped semiconductor layer. The etch may stop somewhere within the N-doped semiconductor layer, although in some applications the etch may continue through the entire N-doped semiconductor layer and stop at the substrate. Optionally, in some embodiments, the method 1000 may include a step for depositing a conductive layer onto the epitaxial structure or the mesa structure after etching.

At step 1030, a layer of a regrowth mask, such as layer of regrowth mask 370, may be formed on top of the mesa. For example, these regrowth masks may be formed over the conductive layer (if present). In some embodiments, there may be more than one layer of regrowth mask. Exemplary masking layers may include photosensitive materials (e.g., photoresist) and hard mask materials (e.g., SiO)₂Or Si₃N₄)。

Method 1000 may also include step 1040. Step 1040 may include one or more processing steps such as, for example, cleaning, annealing, and flashing. Step 1040 may be performed prior to growing one or more regrown semiconductor layers on the etched epitaxial structure to remove sub-surface damage (subsurface Damage) and clean the regrown surface. One or more processing steps may be performed on the exposed mesa end face.

Fig. 11A and 11B illustrate an exemplary cleaning process that may be performed prior to growth of one or more regrown semiconductor layers. Fig. 11A and 11B illustrate exemplary mesa shapes that undergo a sub-surface damage removal and cleaning process. FIG. 11A provides an image 1100A of the array of mesas 1110 during the cleaning process. FIG. 11B provides an image 1100B, and the image 1100B provides a close-up view of the two mesas 1110 from the image 1100A. As illustrated by images 1100A and 1100B, each mesa 1110 includes an etched epitaxial layer 1120 having an end face 1150 formed thereon.

The cleaning process illustrated by images 1110A and 1110B is a modified wet etch cycle that removes sub-surface damage on the mesa surface. The cleaning process provides a smooth mesa surface for subsequent growth of one or more regrown semiconductor layers. A wet etch cycle, Buffered Oxide Etch (BOE), or similar cycle is used to clean the mesa surfaces, remove the oxide or oxygen containing layer on the surfaces prior to regrowth, and reduce surface traps at the heterointerface. In some embodiments, the wet etch process may include a digital etch in which about 0.5nm to about 20nm of semiconductor material is controllably removed from exposed mesa sidewalls. The cleaning process illustrated by images 1110A and 1110B shows the mesa facets after soft etch back (soft back) and cleaning of the mesa surfaces by the BOE process. BOE uses a wet etchant, such as a buffered etching solution, to controllably remove material from the mesa surface. For example, the cleaning process may include 20 wet etch cycles. During the wet etch cycle, the surface of the mesa may be exposed to surface oxidation to form an oxide layer covering the surface of the etched mesa 1110. The oxide layer may be less than 2nm and is not visible in images 1110A and 1110B. After oxidation of the mesa surfaces, the oxide along with any sub-surface damage may be removed by wet or gas etching.

As shown in image 1100B, a growth mask 1170 may be used to protect the mesa structures from undesired etching during the cleaning process. In some embodiments, growth mask 1170 may be the same as the regrowth mask applied at step 1030. In other embodiments, growth mask 1170 may be a different mask than the regrowth mask applied at step 1030. As shown, the cleaning process used in images 1100A and 1100B can result in mostly smooth vertical sidewalls of each mesa 1110. In some cases, the wet etch process may result in some undercuts 1175 under the hard mask 1170, e.g., SiO₂Or Si₃N₄。

In some casesIn an embodiment, one or more of the treatments at step 1040 may also include an annealing process. Fig. 12 provides an image 1200 depicting an array of mesas 1210 that have undergone an annealing process. The annealing process may be performed prior to the growth of the regrown layer on the epitaxial structure. Mesa 1210 depicted in image 1200 has been subjected to an in situ recrystallization process in a MOVPE reactor. This is done at high temperatures, such as for example between 300 ℃ and 600 ℃. In applying II-VI or III-V regrowth layers or other layers such as SiN, SiO by PECVD, ICPECVD, ALD or sputtering₂、HfO、AlN、Al₂O₃、TiO₂Previously, this process recrystallized the mesa surface and reduced surface traps.

Next, the method 1000 may include step 1050. At step 1050, one or more regrown semiconductor layers, such as regrown layers 360, 560, 660, 665, 960, or 965 may be epitaxially grown on the mesa facets. Fig. 13A and 13B provide an array of mesas with a regrown layer epitaxially grown on the mesa facets. Fig. 13A provides an image 1300A depicting a cylindrical mesa 1310A having a regrown layer 1360A grown around the surface of the mesa structure. Similarly, fig. 13B provides an image 1300B depicting rectangular mesas 1310B having a regrowth layer 1360B grown around the surface of the mesa structure. Regrowth layers 1360A and 1360B include AlInP and are formed by MOVPE.

After growing one or more regrown semiconductor layers on the mesa structures, method 1000 may include step 1060. At step 1060, the regrowth mask may be removed.

Fig. 14A-19 provide exemplary comparisons of a mesa structure that has been subjected to a BOE clean process prior to growing a regrowth layer on the epitaxial structure relative to a mesa structure that has not been subjected to a BOE clean process. Beginning with fig. 14A and 14B, images 1400A and 1400B depict mesa 1410. As illustrated by image 1400A, mesa structure 1410 includes an epitaxial structure. The epitaxial structure includes an N-type doped semiconductor layer 1420, MQW layer 1430, and a P-type doped semiconductor layer 1440. The N-type doped semiconductor layer 1420 and the P-type doped semiconductor layer 1440 may be or may include Al-rich cladding layers, such as AlInP, AlGaInP, or AlGaAs with an aluminum content greater than or equal to 40%. Image 1400B provides a close-up view of the sidewalls of mesa 1410. As illustrated by image 1400B, regrowth layer 1460 has been grown on the sidewalls of mesa 1410. Regrowth layer 1460 may comprise ZnSe. Mesa structure 1410 undergoes a UHV H clean prior to the growth of regrown layer 1460. However, mesa structure 1410 is not cleaned using a BOE cleaning process, as described above.

Fig. 15A and 15B illustrate the effect of not adequately removing sub-surface damage and cleaning the mesa surface prior to the growth of the regrowth layer. Fig. 15A provides a close-up view of the interface 1490 from fig. 14B between the regrown layer 1460 of the mesa sidewalls and the epitaxial layer 1520. The epitaxial layer 1520 may include an N-type doped semiconductor layer 1420, an MQW layer 1430, and a P-type doped semiconductor layer 1440. As shown by the interface 1490, a thin oxide layer 1585 may exist between the epitaxial layer 1520 and the regrown layer 1460. The thin oxide layer 1585 may be left behind, for example, after mesa etching and wafer processing, for example, in air. The different vertically stacked epitaxial layers 1520 may have different material compositions at the mesa facets, resulting in different oxides. For example, for a mesa structure including an AlGaAs layer, AlGaInP layer, GaInP layer, GaAs layer, GaO and InO may be formed at the mesa surface with a binding energy less than AlO at the surface. Using H in MBE chamber by, for example, wet etch process₂The UHV vacuum cleaning, soft back sputtering process (soft back sputter process), and the like, the GaO and InO can be more easily eroded and removed. The main problem may be to remove the AlO-based compound for the Al-rich epitaxial layer without damaging the mesa facets.

The thin oxide layer 1585 may be left after the mesa etch process from a previous process step. If the epitaxial layer 1520 includes a relatively high concentration of aluminum, as they do here, a thin oxide layer 1585 may be formed on the epitaxial layer 1520. Due to compositional differences between different material layers in epitaxial layer 1520, different types of oxides may form at the sidewalls. Thus, in some embodiments, different cleaning processes may completely remove certain layers (e.g., rich)Ga-containing layers, such as MQW layers), such as thin oxide layer 1585, but without removing other oxides (e.g., AlO) at other layers, such as, for example, Al-rich P-type or N-type cladding layers. A larger oxide layer 1580 is also present. Oxide layer 1580 may be additional Al after formation of regrowth layer 1460₂O₃Depositing the dielectric layer. Oxide layer 1580 is in contact with regrowth layer 1460.

Fig. 15B, 15C, and 15D provide images of the elemental layout of the interface 1490 between the regrowth layer 1460 and the epitaxial layer 1520. The element layout shows the presence of elements across the depth of the material. Here, the images of fig. 15B, 15C, and 15D show the elemental distribution of oxygen, zinc, and selenium across the depth of the interface 1490. Regrowth layer 1460 comprises ZnSe, so the presence of zinc and selenium shown in fig. 15C and 15D indicates the presence of regrowth layer 1460. The element distribution provided in fig. 15B indicates the presence of the thin oxide layer 1585 and the oxide layer 1580 at the interface 1490 depicted in the image 1500B. By aligning fig. 15B, 15C, and 15D, the presence of a thin oxide layer 1585 between epitaxial layer 1520 and regrowth layer 1460 is evident.

Fig. 16 provides a diagram 1600 of the distribution of elements throughout the depth of the interface 1490 depicted in the image 1500. The x-axis of diagram 1600 is the distance extending from epitaxial layer 1520 to regrowth layer 1460. The y-axis provides the atomic percent of each element through the depth. As shown by diagram 1600, the epitaxial layer 1520 extends between about 0nm and 30nm into the interface 1490. This is indicated by the presence of aluminum, indium, and phosphate at these depths, which correspond to the AlInP cladding layer as part of the epitaxial layer 1520. Regrowth layer 1460 extends between about 35nm and 55nm in interface 1490. This is indicated by the presence of zinc and selenium at these depths corresponding to the ZnSe regrowth layer 1460. A thin oxide layer 1585 is present between the epitaxial layer 1520 and the regrowth layer 1460, as indicated by the increase in oxygen between 27nm and 30 nm. The presence of the oxide layer 1580 is indicated by an increase in oxygen starting at 50 nm. The presence of thin oxide layer 1585 may be undesirable because it may result in overgrowth of amorphous or polycrystalline with traps for more carriers than the good crystalline material quality of regrowth layer 1460.

Fig. 17 provides an image 1700 of mesa structure 1710 that has undergone a BOE cleaning process prior to applying a regrowth layer. Mesa structure 1710 also undergoes UHV H cleaning prior to growth of regrown layer 1760. As shown, mesa structure 1710 includes an epitaxial structure. The epitaxial structure includes an N-doped semiconductor layer 1720, an MQW layer 1730, and a P-doped semiconductor layer 1740. Fig. 18A provides a close-up view of interface 1790. Interface 1790 shows the interface between epitaxial layer 1820 and regrowth layer 1760. Regrowth layer 1760 comprises ZnSe. As shown by interface 1790, there is no thin oxide layer between epitaxial layer 1820 and regrowth layer 1760. Only the oxide layer 1880 is in contact with the regrowth layer 1760 at the interface 1790.

Fig. 18B, 18C, and 18D provide elemental distributions of oxygen, zinc, and selenium at the interface 1790. Fig. 18B depicts the presence of oxygen, indicating the presence of an oxide layer 1880 at the interface 1790. Fig. 18C and 18D depict the presence of zinc and selenium, respectively, indicating the presence of the regrown layer 1760 at the interface 1790. Unlike fig. 15B, there is no thin oxide layer between epitaxial layer 1820 and regrowth layer 1760.

The diagram 1900 provided in fig. 19 also illustrates the absence of a thin oxide layer between epitaxial layer 1820 and regrowth layer 1760. Diagram 1900 is similar to Diagram 1600 in that it shows the distribution of elements across the depth of interface 1790. Similar to fig. 1600, epitaxial layer 1820 is indicated between about 0nm and 30nm by the presence of aluminum, indium, and phosphate. Next, regrowth layer 1760 is indicated between 30nm and 50nm by the presence of zinc and selenium. As shown by plot 1900, there is no increase in oxygen between 30nm and 35nm, indicating the absence of a thin oxide layer between epitaxial layer 1820 and regrowth layer 1760. The presence of the oxide layer 1880 is indicated by an increase in oxygen starting at 55 nm.

The methods, systems, and apparatus discussed above are examples. Various embodiments may omit, substitute, or add various procedures or components as appropriate. For example, in alternative configurations, the described methods may be performed in an order different than that described, and/or stages may be added, omitted, and/or combined. Furthermore, features described with respect to certain embodiments may be combined in various other embodiments. Different aspects and elements of the embodiments may be combined in a similar manner. In addition, technology is constantly evolving and, thus, many elements are examples that do not limit the scope of the disclosure to those specific examples.

In the description, specific details are given to provide a thorough understanding of the embodiments. However, embodiments may be practiced without these specific details. For example, well-known circuits, processes, systems, structures, and techniques have been shown without unnecessary detail in order to avoid obscuring the embodiments. This description provides exemplary embodiments only, and is not intended to limit the scope, applicability, or configuration of the invention. Rather, the foregoing description of the embodiments will provide those skilled in the art with an enabling description (enabling description) for implementing the various embodiments. Various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the disclosure.

Further, some embodiments are described as processes, which are depicted as flowcharts or block diagrams. Although each may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. The process may have additional steps not included in the figure. Furthermore, embodiments of the methods may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware or microcode, the program code or code segments to perform the associated tasks may be stored in a computer-readable medium such as a storage medium. The processor may perform the associated tasks.

It will be apparent to those skilled in the art that substantial variations may be made in accordance with specific requirements. For example, customized hardware or dedicated hardware might also be used, and/or particular elements might be implemented in hardware, software (including portable software, such as applets, etc.), or both. In addition, connections to other computing devices, such as network input/output devices, may be employed.

Referring to the figures, components that may include memory may include a non-transitory machine-readable medium. The terms "machine-readable medium" and "computer-readable medium" may refer to any storage medium that participates in providing data that causes a machine to operation in a specific fashion. In the embodiments provided above, various machine-readable media may be involved in providing instructions/code to a processing unit and/or other apparatus for execution. Additionally or alternatively, a machine-readable medium may be used to store and/or carry such instructions/code. In many implementations, the computer-readable medium is a physical and/or tangible storage medium. Such a medium may take many forms, including but not limited to, non-volatile media, and transmission media. Common forms of computer-readable media include, for example, magnetic and/or optical media such as Compact Disks (CDs) or Digital Versatile Disks (DVDs), punch cards, paper tape, any other physical medium with patterns of holes, RAMs, programmable read-only memories (PROMs), erasable programmable read-only memories (EPROMs), flash-EPROMs, any other memory chip or cartridge, a carrier wave as described hereinafter, or any other medium from which a computer can read instructions and/or code. A computer program product may include code and/or machine executable instructions, which may represent procedures, functions, subroutines, programs, routines, applications (App), subroutines, modules, software packages, classes, or any combination of instructions, data structures, or program statements.

Those of skill in the art would understand that the information and signals used to convey the messages described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The terms "and" or "as used herein may include a variety of meanings that are also contemplated to depend at least in part on the context in which such terms are used. In general, "or" if used in association lists, such as A, B or C, is intended to mean A, B and C (used herein in an inclusive sense) and A, B or C (used herein in an exclusive sense). Furthermore, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe some combination of features, structures, or characteristics. It should be noted, however, that this is merely an illustrative example and that claimed subject matter is not limited to this example. Furthermore, at least one of the terms (at least one of) if used for an association list, such as A, B or C, may be interpreted to mean any combination of A, B and/or C, such as a, AB, AC, BC, AA, ABC, AAB, AABBCCC, etc.

Furthermore, while certain embodiments have been described using a particular combination of hardware and software, it should be recognized that other combinations of hardware and software are possible. Certain embodiments may be implemented in hardware only, or in software only, or using a combination thereof. In one example, the software may be implemented in a computer program product comprising computer program code or instructions executable by one or more processors for performing any or all of the steps, operations, or processes described in this disclosure, wherein the computer program may be stored on a non-transitory computer readable medium. The various processes described herein may be implemented on the same processor or on different processors in any combination.

Where a device, system, component, or module is described as being configured to perform certain operations or functions, such configuration may be accomplished, for example, by designing an electronic circuit that performs the operations, by programming a programmable electronic circuit (such as a microprocessor) to perform the operations (such as by executing computer instructions or code), or by a processor or core programmed to execute code or instructions stored on a non-transitory memory medium, or any combination thereof. The processes may communicate using a variety of techniques, including but not limited to conventional techniques for inter-process communication, and different pairs of processes may use different techniques, or the same pair of processes may use different techniques at different times.

The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that additions, deletions, and other modifications and changes may be made thereto without departing from the broader spirit and scope as set forth in the claims. Thus, while specific embodiments have been described, these embodiments are not intended to be limiting. Various modifications and equivalents are within the scope of the appended claims.