阅读说明：本技术 包含用于刷新的补充感测放大器电路的集成组合件 (Integrated assembly including supplemental sense amplifier circuitry for refresh ) 是由 S·J·德尔纳 C·L·英戈尔斯 于 2019-05-29 设计创作，主要内容包括：本申请案涉及包括用于刷新的补充感测放大器电路的集成组合件。一些实施例包含具有第一存储器阵列的集成组合件，所述第一存储器阵列包含第一列第一存储器单元。第一数字线沿着所述第一列延伸并用于寻址所述第一列的所述第一存储单元。第二存储器阵列靠近所述第一存储器阵列并包含第二列第二存储器单元。第二数字线沿着所述第二列延伸并用于寻址所述第二列的所述第二存储单元。初级感测放大器将所述第一数字线与所述第二数字线相对地耦合。第一次级感测放大器沿着所述第一数字线，且第二次级感测放大器沿着所述第二数字线。(The application relates to an integrated assembly including a supplemental sense amplifier circuit for refresh. Some embodiments include an integrated assembly having a first memory array including a first column of first memory cells. A first digit line extends along the first column and is used to address the first memory cell of the first column. A second memory array is proximate the first memory array and includes a second column of second memory cells. A second digit line extends along the second column and is used to address the second memory cell of the second column. A primary sense amplifier couples the first digit line opposite the second digit line. A first secondary sense amplifier is along the first digit line and a second secondary sense amplifier is along the second digit line.)

1. An integrated assembly, comprising:

a first memory array comprising a first column of first memory cells;

a first digit line extending along the first memory cell of the first column and for addressing the first memory cell of the first column;

a second memory array proximate to the first memory array and comprising a second column of second memory cells;

a second digit line extending along the second column of the second memory cells and for addressing the second memory cells of the second column;

a primary sense amplifier oppositely coupling the first bit line and the second bit line; the primary sense amplifier is configured to be utilized during reading from and writing to the first and second memory cells along the first and second columns; and

a first secondary sense amplifier along the first digit line and a second secondary sense amplifier along the second digit line; the first and second secondary sense amplifiers are configured only for refreshing the first and second memory cells along the first and second digit lines.

2. The integrated assembly of claim 1, comprising:

a base; the primary and secondary sense amplifiers are along the base;

a first platform located above the base; a first portion of the first column of the first storage units is along the first platform and a first portion of a second column of the second storage units is along the first platform; and

a second platform located above the first platform; a second portion of the first column of the first memory cells is along the second ledge, and a second portion of the second column of the second memory cells is along the second ledge.

3. The integrated assembly of claim 2, wherein the first secondary sense amplifier is located between the first portion of the first column of the first memory cells and the second portion of the first column of the first memory cells; and wherein the second secondary sense amplifier is located between the first portion of the second column of the second memory cells and the second portion of the second column of the second memory cells.

4. The integrated assembly of claim 1, wherein the first and second storage units comprise charge storage devices in combination with transistors.

5. The integrated assembly of claim 1, wherein the first and second storage cells comprise capacitors in combination with transistors.

6. An integrated assembly, comprising:

a first memory array comprising a first column of first memory cells;

a first digit line extending along the first memory cell of the first column and for addressing the first memory cell of the first column;

a second memory array proximate to the first memory array and comprising a second column of second memory cells;

a second digit line extending along the second column of the second memory cells and for addressing the second memory cells of the second column;

a primary sense amplifier configured to oppositely couple the first digit line and the second digit line;

a first secondary sense amplifier along the first digit line and a first switch between the first secondary sense amplifier and the first digit line; the first switch is configured to close during a first operation along the first column to shunt electrical signals through the first secondary sense amplifier; the first switch is configured to open during a second operation along the first column to enable the first secondary sense amplifier to oppositely couple a portion of the first digit line on one side of the first secondary sense amplifier with another portion of the first digit line on an opposite side of the first secondary sense amplifier; and

a second secondary sense amplifier along the second digit line; and a second switch between the second secondary sense amplifier and the second digit line; the second switch is configured to close during a first operation along the second column to shunt electrical signals through the second secondary sense amplifier; the second switch is configured to open during a second operation along the second column to enable the second secondary sense amplifier to oppositely couple a portion of the second digit line on one side of the second secondary sense amplifier with another portion of the second digit line on an opposite side of the second secondary sense amplifier.

7. The integrated assembly of claim 6, wherein each of the first and second switches comprises a transistor.

8. The integrated assembly of claim 6, wherein each of the first and second secondary sense amplifiers comprises fewer components than the primary sense amplifier.

9. The integrated assembly of claim 6, wherein the primary sense amplifier comprises a balancing circuit absent in the first and second secondary sense amplifiers.

10. The integrated assembly of claim 6, wherein the primary sense amplifier comprises input/output circuitry absent in the first and second secondary sense amplifiers.

11. The integrated assembly of claim 6, wherein the primary sense amplifier is located below the first and second memory arrays.

12. The integration assembly of claim 11, wherein the first and second secondary sense amplifiers are located below the first and second memory arrays.

13. The integrated assembly of claim 6, wherein the first and second storage units comprise charge storage devices in combination with transistors.

14. The integrated assembly of claim 6, wherein the first and second storage cells comprise capacitors in combination with transistors.

15. The integration assembly of claim 6, wherein the second operation along the first and second columns is a refresh operation.

16. An integrated assembly, comprising:

a base;

a first platform located above the base;

a second platform located above the first platform;

a first memory array comprising a first column of first memory cells;

a first digit line extending along the first memory cell of the first column and for addressing the first memory cell of the first column; a first portion of the first column of the first storage units is along the first ledge and a second portion of the first column of the first storage units is along the second ledge;

a second memory array proximate to the first memory array and comprising a second column of second memory cells;

a second digit line extending along the second column of the second memory cells and for addressing the second memory cells of the second column; a first portion of the second column of the second storage units is along the first ledge and a second portion of the second column of the second storage units is along the second ledge;

a primary sense amplifier configured to oppositely couple the first digit line and the second digit line; the primary sense amplifier is along the pedestal;

a first secondary sense amplifier along the first digit line and coupled to the first digit line through a first transistor; the first transistor has a first source/drain region coupled to a first portion of the first digit line, a second source/drain region coupled to a second portion of the first digit line, and a first gate coupled with an isolation driver; and

a second secondary sense amplifier along the second digit line and coupled to the second digit line through a second transistor; the second transistor has a third source/drain region coupled to a first portion of the second digit line, a second source/drain region coupled to a second portion of the second digit line, and a second gate coupled with the isolation driver.

17. The integrated assembly of claim 16, wherein the first and second storage units are 1T-1C memory cells.

18. The integrated assembly of claim 16, wherein the primary sense amplifiers are configured to be utilized during reading from and writing to the first and second memory cells along the first and second columns; and wherein the first and second secondary sense amplifiers are configured to be utilized only during refreshing of the first and second memory cells along the first and second rows.

19. The integrated assembly of claim 16, wherein the first and second secondary sense amplifiers are along the pedestal.

20. The integrated assembly of claim 19, wherein a primary sense amplifier is located between the first secondary sense amplifier and the second secondary sense amplifier.

Technical Field

The integrated assembly includes a supplemental sense amplifier circuit for refresh.

Background

Memory is used in modern computing architectures to store data. One type of memory is Dynamic Random Access Memory (DRAM). The DRAM may provide advantages of a simple structure, low cost, and high speed, compared to alternative types of memory.

DRAM may utilize memory cells having a capacitor in combination with a transistor (so-called 1T-1C memory cells), where the capacitor is coupled to the source/drain region of the transistor. Example 1T-1C memory cell 2 is shown in fig. 1, with the transistor labeled T and the capacitor labeled C. The capacitor has one node coupled to the source/drain regions of the transistor and another node coupled to the common plate CP. The common plate can be coupled to any suitable voltage, such as a voltage ranging from greater than or equal to ground to less than or equal to VCC (i.e., ground ≦ CP ≦ VCC). In some applications, the common plate is at a voltage of about half of VCC (i.e., about VCC/2). The transistor has a gate coupled to a word line WL (i.e., an access line) and has a source/drain region coupled to a bit line BL (i.e., a digit line or a sense line). In operation, an electric field generated by a voltage along a word line may gate couple a bit line to a capacitor during read/write operations.

Another prior art 1T-1C memory cell configuration is shown in FIG. 2. The configuration of FIG. 2 shows two memory cells 2a and 2 b; wherein memory cell 2a includes transistor T1 and capacitor C1, and wherein memory cell 2b includes transistor T2 and capacitor C2. Word lines WL0 and WL1 are electrically coupled to the gates of transistors T1 and T2, respectively. Memory cells 2a and 2b share a connection to a bit line BL.

The memory cells described above can be incorporated into a memory array, and in some applications, the memory array can have an open bit line arrangement. An example integrated assembly 9 having an open bit line architecture is shown in fig. 3. The assembly 9 includes two laterally adjacent memory arrays ("array 1" and "array 2"), with each of the arrays including memory cells of the type described in figure 2 (not labeled in figure 3 in order to simplify the drawing). Word lines WL 0-WL 7 extend across the array and are coupled with word line drivers. The digit lines D0 to D8 are associated with the first array (array 1) and the digit lines D0 to D8 are associated with the second array (array 2). Sense amplifiers SA 0-SA 8 are disposed between the first and second arrays. The digitlines at the same height are paired with each other and compared by the sense amplifier (e.g., digitlines D0 and D0 are paired with each other and compared to sense amplifier SA 0). In a read operation, one of the paired digit lines can be used as a reference to determine an electrical characteristic (e.g., voltage) of the other of the paired digit lines.

A continuing goal of integrated circuit fabrication is to increase packing density and, thus, integration. It is desirable to develop three-dimensional arrangements with closely packed memory. Another objective is to enable refresh of DRAM cells quickly. It is desirable to develop integrated memory configurations that are capable of fast refresh of DRAM cells.

Disclosure of Invention

An embodiment of the present invention provides an integrated assembly comprising: a first memory array comprising a first column of first memory cells; a first digit line extending along the first column of the first memory cells and for addressing the first memory cells of the first column; a second memory array proximate to the first memory array and comprising a second column of second memory cells; a second digit line extending along the second column of the second memory cells and for addressing the second memory cells of the second column; a primary sense amplifier oppositely coupling the first digit line and the second digit line; the primary sense amplifier is configured to be utilized during reading from and writing to the first and second memory cells along the first and second columns; and a first secondary sense amplifier along the first digit line and a second secondary sense amplifier along the second digit line; the first and second secondary sense amplifiers are configured only for refreshing the first and second memory cells along the first and second digit lines.

Another embodiment of the present invention provides an integrated assembly comprising: a first memory array comprising a first column of first memory cells; a first digit line extending along the first column of the first memory cells and for addressing the first memory cells of the first column; a second memory array proximate to the first memory array and comprising a second column of second memory cells; a second digit line extending along the second column of the second memory cells and for addressing the second memory cells of the second column; a primary sense amplifier configured to oppositely couple the first digit line and the second digit line; a first secondary sense amplifier along the first digit line, and a first switch between the first secondary sense amplifier and the first digit line; the first switch is configured to close during a first operation along the first column to shunt electrical signals through the first secondary sense amplifier; the first switch is configured to open during a second operation along the first column to enable the first secondary sense amplifier to oppositely couple a portion of the first digit line on one side of the first secondary sense amplifier with another portion of the first digit line on an opposite side of the first secondary sense amplifier; and a second secondary sense amplifier along the second digit line, and a second switch between the second secondary sense amplifier and the second digit line; the second switch is configured to close during a first operation along the second column to shunt electrical signals through the second secondary sense amplifier; the second switch is configured to open during a second operation along the second column to enable the second secondary sense amplifier to oppositely couple a portion of the second digit line on one side of the second secondary sense amplifier with another portion of the second digit line on an opposite side of the second secondary sense amplifier.

Another embodiment of the present invention provides an integrated assembly comprising: a base; a first platform located above the base; a second platform located above the first platform; a first memory array comprising a first column of first memory cells; a first digit line extending along the first column of the first memory cells and for addressing the first memory cells of the first column; a first portion of the first column of the first memory cells is along the first ledge and a second portion of the first column of the first memory cells is along the second ledge; a second memory array proximate to the first memory array and comprising a second column of second memory cells; a second digit line extending along the second column of the second memory cells and for addressing the second memory cells of the second column; a first portion of the second column of second memory cells is along a first terrace and a second portion of the second column of second memory cells is along the second terrace; a primary sense amplifier configured to oppositely couple the first digit line and the second digit line; the primary sense amplifier is along the pedestal; a first secondary sense amplifier along the first digit line and coupled to the first digit line through a first transistor; the first transistor has a first source/drain region coupled to a first portion of the first digit line, a second source/drain region coupled to a second portion of the first digit line, and a first gate coupled with an isolation driver; and a second secondary sense amplifier along the second digit line and coupled to the second digit line through a second transistor; the second transistor has a third source/drain region coupled to a first portion of the second digit line, a second source/drain region coupled to a second portion of the second digit line, and a second gate coupled to the isolation driver.

Drawings

FIG. 1 is a schematic diagram of a prior art memory cell having 1 transistor and 1 capacitor.

FIG. 2 is a schematic diagram of a pair of prior art memory cells each having 1 transistor and 1 capacitor, and which share a bitline connection.

FIG. 3 is a schematic diagram of a prior art integration assembly having an open bitline architecture.

FIG. 4 is a schematic three-dimensional view of an exemplary integrated assembly having multiple stages that are vertically displaced relative to each other.

FIG. 4A is a schematic three-dimensional view of an exemplary integrated assembly having multiple platforms that are vertically displaced relative to one another.

Fig. 5A and 5B are schematic side views showing example arrangements of circuit components.

Fig. 6A and 6B are schematic side views showing an example arrangement of circuit components.

Fig. 7A and 7B are schematic side views showing example arrangements of circuit components.

Fig. 8 is a schematic side view showing an example arrangement of circuit components.

Fig. 9-11 are schematic diagrams of example sense amplifier circuits.

Detailed Description

Operation of a DRAM (e.g., the conventional DRAM of figure 3) utilizes sense amplifiers to read to and write from memory cells, as well as for refreshing memory cells. The data state of a DRAM cell may correspond to the charge state of a capacitor within the memory cell. If the capacitor is charged, then the memory cell is in one memory state; if the capacitor is not charged, the memory cell is in a different memory state. Refreshing is required because the capacitor discharges over time and thus the memory cell will lose data unless the state of charge of the capacitor is restored aperiodically.

The digit lines of a memory array can be considered to extend along columns of the memory array, and the word lines can be considered to extend along rows of the memory array. Refreshing of the memory cells may include activating the word line to trigger all memory cells along a row. Data from the triggered memory cell is placed on the digit line associated with the memory cell. The digit lines extend to sense amplifiers (as shown in the conventional DRAM of figure 3). The sense amplifier pulls the data signal to full level (ground or VCC) and then returns this full level charge to the memory cell.

Sense amplifiers are also used to read from and write to memory cells. Such operations include triggering individual memory cells to provide contents to the memory cells (during a write operation), or determining the contents of the memory cells (during a read operation). Read and write operations may require more complex operation of the sense amplifier than do refresh operations. Some embodiments include adding auxiliary sense amplifiers along columns of a DRAM array, where such supplemental sense amplifiers are used only during refresh operations. The supplemental sense amplifier may be referred to as a secondary sense amplifier. The main sense amplifier is still the primary sense amplifier utilized during read/write operations. The secondary sense amplifier may have a simpler circuit design than the primary sense amplifier and may therefore consume less semiconductor real estate. The secondary sense amplifier divides the digit line into short segments during refresh operations, which can increase the available signals and thereby reduce refresh cycles and save power. The timing performance of the refresh cycle may also be enhanced. In some embodiments, the primary and secondary sense amplifiers may be provided under the memory array, which may enable the fabrication of highly integrated architectures. Example embodiments are described with reference to fig. 4, 4A, 5B, 6A, 6B, 7A, 7B, and 8-11.

Referring to fig. 4, the integrated assembly 10 includes a base 12, a first platform 14 above the base, and a second platform 16 above the first platform. The second platform 14 includes a first section 14a and a second section 14 b.

The base 12 may comprise a semiconductor material; and may, for example, comprise, consist essentially of, or consist of monocrystalline silicon. The susceptor 12 may be referred to as a semiconductor substrate. The term "semiconductor substrate" refers to any construction comprising semiconductor material, including, but not limited to, bulk semiconductor materials such as semiconductor wafers (alone or in assemblies comprising other materials) and layers of semiconductor material (alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including but not limited to the semiconductor substrate described above. In some applications, the base 12 may correspond to a semiconductor substrate that includes one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, and the like. Each of the mesas 14 and 16 may also include semiconductor material.

A first memory Array (Array-1) is along one side of the first and second platforms 14, 16, and a second memory Array (Array-2) is along the other side of the first and second platforms. Digit lines D0 and D1 extend along columns of the first memory array, and digit lines D0 and D1 extend along columns of the second memory array. Word lines WL0 and WL4 extend along a row of the first memory array, and word lines WL8 and WL12 extend along a row of the second memory array. The illustrated word lines and digit lines represent a large number of substantially identical word lines and digit lines that can extend across a memory array (where the term "substantially identical" means identical within reasonable tolerances in fabrication and measurement). A memory array may include hundreds, thousands, millions, etc. of substantially identical memory cells; and such memory cells can each be uniquely addressed with one of the digit lines and one of the word lines. Thus, there may be hundreds, thousands, millions, etc. of word lines and digit lines associated with a memory array. Individual memory cells are not shown in fig. 4, but example memory cells are described below with reference to fig. 5A, 5B, 6A, 6B, 7A, 7B, and 8.

Still referring to FIG. 4, word lines WL0, WL4, WL8 and WL12 are coupled with word line drivers; with one of the drivers labeled as the Left Row Driver (Row-Driver Left) and the other as the right Row Driver (Row-Driver right). The left row driver drives the word lines along the first memory Array (Array-1) and the right row driver drives the word lines along the second memory Array (Array-2).

Digit line D0 is coupled opposite digit line D0 by primary sense amplifier SA-0 and digit line D1 is coupled opposite digit line D1 by primary sense amplifier SA-1. The primary sense amplifiers SA-0 and SA-1 are identified by the tag 20 and may be referred to herein as sense amplifiers 20, or as sense amplifier circuits 20. For understanding the present invention and the claims that follow, a first digit line is "oppositely coupled" with a second digit line by a sense amplifier circuit if the sense amplifier circuit is configured to compare electrical properties (e.g., voltages) of the first and second digit lines to one another. Fig. 11 (below) shows an example primary sense amplifier SA-0, and shows an example application where digit lines D0 and D0 are oppositely coupled through the example primary sense amplifier.

Each of the digit lines of fig. 4 includes a first portion along the first mesa 14 and a second portion along the second mesa 16. Specifically, digit line D0 includes a first portion D0-a along first platform 14 and a second portion D0-b along second platform 16. Similarly, the digit lines D0, D1, and D1 include first portions D0 a, D1 a, and D1 a along the first land 14, and include second portions D0 b, D1 b, and D1 b along the second land 16. In some embodiments, the second portion of the digit line can be considered to be vertically offset relative to the first portion of the digit line. The digit lines extend along columns of the memory Array (Array-1 and Array-2), and thus such columns of the memory Array can be understood to have a first portion along the first mesa 14 and have a second portion along the second mesa 16.

In the embodiment shown, a first portion of the digit line (e.g., portion D0-a of digit line D0) is relatively coupled to a second portion of the digit line (e.g., portion D0-b of digit line D0) through a secondary sense amplifier. The secondary sense amplifiers are labeled SA-REF-1, SA-REF-2, SA-REF-3, and SA-REF-4; where the term "REF" is used to emphasize that the secondary sense amplifier may be dedicated to refresh operations. The secondary sense amplifiers SA-REF-1, SA-REF-2, SA-REF-3 and SA-REF-4 are all identified by labels 22; and may be referred to as a sense amplifier 22 or as a sense amplifier circuit 22.

Sense amplifier circuits 20 and 22 may comprise any suitable configuration. The example sense amplifier circuit 20 is illustrated exploded in fig. 11, and the example sense amplifier circuit 22 is illustrated exploded in fig. 9 and 10. The dashed lines provided in FIG. 4 show the approximate boundaries of the sense amplifier circuitry. In the embodiment shown, the primary sense amplifier 20 is along the pedestal 12, and the secondary sense amplifier 22 is also along this pedestal; with the primary sense amplifiers 20 located laterally between the secondary sense amplifiers 22. In some embodiments, at least part of the amplifier circuitry may be provided directly below the memory array to enable tight packing density.

Figure 4 shows one embodiment in which the top platform 16 has a different configuration than the underlying platform 14. In particular, the platform 14 is divided between two portions 14a and 14b, while the platform 16 is a continuous expanse. In other embodiments, the upper platform 16 may be separated similarly to the underlying platform 14, as shown in fig. 4A.

The memory arrays of FIGS. 4 and 4A (Array-1 and Array-2) can comprise any suitable memory cells. Example configurations of such memory arrays are described with reference to fig. 5A, 5B, 6A, 6B, 7A, and 7B and 8.

Referring to FIG. 5A, the memory cells of the memory arrays Array-1 and Array-2 are labeled MC.

Fig. 5A specifically shows a portion of the integrated assembly 10 including regions of the first memory Array (Array-1) and the second memory Array (Array-2) along digit lines D0 and D0. The digit lines D0 and D0 may be referred to as first and second digit lines, respectively. Memory cells MC along a first digit line D0 are labeled as first memory cells 30 and are arranged in a first column 40; with digit line D0 extending along this first column. Memory cells MC along a second digit line D0 are labeled as second memory cells 32 and are arranged in a second column 42; where digit line D0 extends along this second column. Each of the memory cells 30 of the first memory Array (Array-1) is uniquely addressed by a digit line D0 and one of the illustrated word lines (WL 0-WL 7). Each of the memory cells 32 of the second memory Array (Array-2) is uniquely addressed by a digit line D0 and one of the illustrated word lines (WL 8-WL 15). Digit lines D0 and D0 are oppositely coupled through primary sense amplifier SA-0.

The first digit line D0 is subdivided into portions D0-a and D0-b; and the first column 40 can be considered to be similarly subdivided into a first portion 40a and a second portion 40 b. The first portion 40a of the first column 40 is associated with a first portion D0-a of the digit line D0 and the second portion 40b of the first column 40 is associated with a second portion D0-b of the digit line D0.

The second digit line D0 is subdivided into portions D0 a and D0 b; and the second column 42 can be considered to be similarly subdivided into a first portion 42a and a second portion 42 b. The first portion 42a of the second column 42 is associated with a first portion D0 a of the digit line D0, and the second portion 42b of the first column 42 is associated with a second portion D0 b of the digit line D0.

The first portion D0-a and the second portion D0-b of the first digit line D0 are coupled to each other. Depending on the mode of operation of switch 34, the coupling may be through first switch 34 or through secondary sense amplifier 22 (SA-REF-2). Similarly, the first portion D0 a and the second portion D0 b of the second digit line D0 are coupled to each other through the second switch 36 or the secondary sense amplifier 22(SA-REF-3) depending on the mode of operation of the switch 36. FIG. 5A shows the mode of operation with switches 34 and 36 in a closed configuration, and thus the electrical signals along columns 40 and 42 are shunted through secondary sense amplifier 22. The mode of operation of fig. 5A effectively removes the secondary sense amplifier 22 from affecting current flow along columns 40 and 42. Thus, the primary sense amplifier 20 can be used to access all of the memory cells associated with the first and second columns 40, 42 of Array-1 and Array-2; and may be used for read/write operations associated with first column 40 and second column 42.

Switches 34 and 36 are shown as being controlled by isolation circuit 38, isolation circuit 38 being labeled DL-ISO; and may be referred to as a digitline isolation circuit or as a digitline isolation driver.

Switches 34 and 36 may have any suitable configuration, and may correspond to transistors in some embodiments; as described in more detail below with reference to fig. 9 and 10. Switches 34 and 36 represent switches that may be associated with each of the secondary sense amplifier circuits 22. Such switches may be located in any suitable location, and in some embodiments may be along base 12 of fig. 4. In some embodiments, at least a portion of the switches (e.g., 34 and 36) may be directly below the memory array to enable tight packaging. In some embodiments, all of the switches (e.g., 34 and 36) may be directly below the memory array to achieve tight packing.

Fig. 5B shows a mode of operation in which switches 34 and 36 are in an open configuration. Thus, the first portion D0-a of the first digit line D0 is relatively coupled to the second portion D0-b through the secondary sense amplifier SA-REF-2, and the first portion D0-a of the second digit line D0 is relatively coupled to the second portion D0-b through the secondary sense amplifier SA-REF-3. In some embodiments, secondary sense amplifiers SA-REF-2 and SA-REF-3 may be referred to as first and second secondary sense amplifiers, respectively. The mode of operation of FIG. 5B may be used to refresh memory cells along columns 40 and 42.

Refreshing memory cells MC using secondary sense amplifier 22 may utilize any suitable programming operation. For example, in some embodiments, the primary sense amplifier 20 may be utilized to initially precharge the first digit line D0 and the second digit line D0 when the switches 34 and 36 are in the closed configuration of fig. 5A; driver 38 may be used to then change switches 34 and 36 to the open configuration of fig. 5B; and the secondary sense amplifiers 22 and row drivers may then be utilized during refresh operations. In some embodiments (not shown), columns 40 and 42 may be configured such that the primary sense amplifier 20 may also be utilized during refresh operations.

In some embodiments, the configurations of fig. 5A and 5B may be considered to correspond to first and second operations performed along columns 40 and 42, respectively.

FIGS. 5A and 5B stand for operation along a single column from Array-1 and along Array-2. The same operation may be performed along all other columns of the memory array.

Referring to fig. 6A and 6B, example memory cells 30 and 32 are shown in more detail than in fig. 5A and 5B. Each of the example memory cells 30 and 32 includes a transistor T coupled with a capacitor C. Each capacitor has a node coupled to a reference voltage 46. The reference voltage 46 may correspond to the Common Plate (CP) voltage described above with reference to fig. 1. The illustrated memory cells of FIGS. 6A and 6B are 1T-1C memory cells. In other embodiments, other memory cells may be utilized. The capacitors of the illustrated memory cells 30 and 32 are example charge storage devices, and in other embodiments, other suitable charge storage devices (e.g., phase change devices, conductive bridge devices, etc.) may be utilized.

Referring to fig. 7A and 7B, example memory cells 30 and 32 are shown in more detail than in fig. 6A and 6B. The transistor T is shown as comprising a vertically-extending pillar 50 of semiconductor material 52. Semiconductor material 52 may comprise any suitable composition; and in some embodiments may comprise, consist essentially of, or consist of one or more of silicon, germanium, a group III/V semiconductor material (e.g., gallium phosphide), a semiconductor oxide, and the like; wherein the term group III/V semiconductor material refers to a semiconductor material comprising an element selected from groups III and V of the periodic table of elements (wherein groups III and V are old nomenclature and are now referred to as groups 13 and 15). Source/drain and channel regions (not shown) may be disposed within the pillars 50. Gate dielectric material 54 is along the sidewalls of the pillars and conductive gate material 56 is along the gate dielectric material. The gate dielectric material may comprise any suitable composition; and in some embodiments may comprise, consist essentially of, or consist of silica. Gate material 56 may comprise any suitable conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.).

Capacitor C includes a first conductive node 58, a second conductive node 60, and an insulating material 62 between the first and second conductive nodes. The first conductive node 60 and the second conductive node 62 may comprise any suitable conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). The first and second conductive nodes may comprise the same composition as one another, or may comprise different compositions from one another. The insulating material 62 may comprise any suitable composition; and in some embodiments may comprise, consist essentially of, or consist of silica.

In the embodiment shown, the lower conductive node 58 is configured as an upwardly open container. In other embodiments, the lower conductive node may have other suitable shapes. The lower conductive node 58 may be referred to as a storage node and the upper node 60 may be referred to as a plate electrode. In some embodiments, the plate electrodes within Array-1 may all be coupled to each other, and the plate electrodes within Array-2 may also all be coupled to each other.

Digit lines D0 and D0 are shown as including conductive materials 64 and 66, respectively. Such conductive materials may include any suitable conductive composition; for example, various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc. in some embodiments, the conductive materials 64 and 66 may be the same composition as one another, or may be different compositions.

The embodiments of figures 4, 4A, 5B, 6A, 6B, 7A, and 7B show each of the digit lines having a second portion at a different elevation level than the first portion (e.g., digit line D0 has a second portion D0-B at a different elevation level than first portion D0-a). In other embodiments, the first and second portions of the digit line can be at the same height level as each other. For example, fig. 8 shows a region of integrated assembly 10 that is similar to the integrated assemblies of fig. 5A and 5B, but with digit lines D0 and D0 extending horizontally along a single elevational level. Thus, first portion D0-a and second portion D0-b of digit line D0 are at the same height level along each other, and first portion D0 a and second portion D0-b of digit line D0 are at the same height level along each other. Word lines and word line drivers are not shown in fig. 8 in order to simplify the drawing, but may be similar to those in fig. 5A and 5B. Switches 34 and 36 are generally illustrated in fig. 8, the switches not shown being in either the open configuration or the closed configuration. Switches 34 and 36 may operate similar to those described above with reference to fig. 5A and 5B.

The secondary sense amplifiers 22 of fig. 4, 4A, 5B, 6A, 6B, 7A, 7B, and 8 may have any suitable configuration. Example embodiments of secondary sense amplifiers 22, specifically secondary sense amplifiers SA-REF-2 and SA-REF-3, are described with reference to FIGS. 9 and 10.

The secondary sense amplifier 22 includes a p-sense amplifier 80 comprising a pair of cross-coupled pull-up transistors 82 and 84, and includes an n-sense amplifier 86 comprising a pair of cross-coupled pull-down transistors 88 and 90. The p sense amplifier 80 is coupled with an active pull-up circuit (labeled ACT) and the n sense amplifier 86 is coupled with a common node (labeled RNL).

The secondary sense amplifier SA-REF-2 of FIG. 9 is coupled with a first digital line portion D0-a and a second digital line portion D0-b; or in other words, digit line portions D0-a and D0-b are coupled relative to each other through the illustrated secondary sense amplifier SA-REF-2. In operation, amplifiers 80 and 86 may be used together to detect the relative signal voltages of D0-a and D0-b, and drive the higher signal voltage to VCC while driving the lower signal voltage to ground.

The secondary sense amplifier SA-REF-3 of fig. 10 is coupled to the first digit line portion D0 a and the second digit line portion D0 b in a manner similar to the manner in which the secondary sense amplifier SA-REF-2 of fig. 9 is coupled to the first digit line portion D0-a and the second digit line portion D0-b.

Switches 34 and 36 of fig. 9 and 10 are illustrated as first and second transistors 100 and 102, respectively. The first transistor 100 has a first source/drain region 101 coupled to a first portion D0-a of the first digit line D0 and has a second source/drain region 103 coupled to a second portion D0-b of the first digit line. Transistor 100 also includes a gate 105, gate 105 being electrically coupled to isolation driver 38. The second transistor 102 has a first source/drain region 107 coupled to a first portion D0 a of the second digit line D0 and has a second source/drain region 109 coupled to a second portion D0 b of the second digit line. In addition, the second transistor 102 includes a gate 111 coupled to the isolation driver 38. In some embodiments, the gate 105 of the first transistor 100 may be referred to as a first gate, and the gate 111 of the second transistor 102 may be referred to as a second gate.

In the illustrated embodiment, the secondary sense amplifier 22 includes an additional isolation circuit 120, which includes a pair of transistors 122 and 124, and an isolation driver 126 (labeled ISO). The isolation circuit 120 enables the ACT and RNL circuits to be shared between the secondary sense amplifiers, as each of the amplifiers may be isolated when not in use. In some embodiments, the isolation circuit 120 may be omitted, and in such embodiments, individual ACT and RNL devices may be associated with each of the secondary sense amplifiers.

The primary sense amplifiers 20 of fig. 4, 4A, 5B, 6A, 6B, 7A, 7B, and 8 may have any suitable configuration. An example embodiment of primary sense amplifier 20, specifically primary sense amplifier SA-0, is described with reference to FIG. 11.

The primary sense amplifier 20 includes a p-sense amplifier 80 and an n-sense amplifier 86 as described above with reference to fig. 9 and 10 (and typically shown in fig. 11 more than in fig. 9 and 10). In operation, amplifiers 80 and 86 may be used together to detect the relative signal voltages of D0 and D0, and drive the higher signal voltage to VCC while driving the lower signal voltage to ground.

The primary sense amplifier 20 includes inputs and outputs (labeled I/O) that may be used to output data regarding the relative signal voltages of D0 and D0, and/or for programming memory cells along one or both of D0 and D0; a balancing circuit (labeled EQ) provided therein to balance electrical properties within the sense amplifier; including column select circuitry (labeled CSEL); and may include other components. Thus, the primary sense amplifier 20 of fig. 11 is substantially more complex than the secondary sense amplifier 22 of fig. 9 and 10. This is because the primary sense amplifier 20 is configured for read/write operations, while the secondary sense amplifier 22 is only configured for refresh operations. Because the secondary sense amplifier includes fewer components than the primary sense amplifier, the secondary sense amplifier may be easier to manufacture than the primary sense amplifier and may be packaged into a tighter space than the primary sense amplifier.

The examples of figures 4, 4A, 5B, 6A, 6B, 7A, 7B and 8 utilize the illustrated secondary sense amplifiers to subdivide each digit line into two portions, and thus effectively half divide the digit line during refresh operations. In other embodiments, additional secondary sense amplifiers may be provided such that the digit lines are subdivided into three, four, five, etc. during refresh operations.

The illustrated digit lines of figures 5A, 5B, 6A, 6B, 7A, 7B, and 8 include eight memory cells. In other embodiments, the digit line can have more than eight memory cells, or less than eight memory cells. For example, in some embodiments, a digit line may include 16 memory cells, 32 memory cells, 64 memory cells, and so on.

The assemblies and structures discussed above may be used within an integrated circuit (where the term "integrated circuit" denotes an electronic circuit supported by a semiconductor substrate); and possibly incorporated into an electronic system. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. Electronic systems may be any of a wide range of systems, such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, airplanes, and the like.

Unless otherwise specified, the various materials, substances, compositions, etc. described herein can be formed using any suitable method, now known or yet to be developed, including, for example, Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), etc.

The terms "dielectric" and "insulating" may be used to describe a material having insulating electrical properties. Terms are considered synonyms in the present invention. The use of the term "dielectric" in some cases and the term "insulating" (or "electrically insulating") in other cases may vary the language provided within this disclosure to simplify the antecedent basis in the claims that follow and is not intended to indicate any significant chemical or electrical difference.

The particular orientation of the various embodiments in the drawings is for illustrative purposes only, and in some applications, embodiments may be rotated relative to the orientation shown. The description provided herein and the claims that follow refer to any structure having the described relationships between various features, whether the structure is in a particular direction in the figures, or rotated relative to that direction.

To simplify the drawings, the cross-sectional views of the accompanying description show only features within the plane of the cross-section, and do not show material behind the plane of the cross-section, unless otherwise indicated.

When a structure is referred to above as being "on," "adjacent to," or "against" another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being "directly on," "directly adjacent to," or "directly against" another structure, there are no intervening structures present. The terms "directly under", "directly over", and the like do not indicate direct physical contact (unless explicitly stated otherwise), but rather indicate upright alignment.

Structures (e.g., layers, materials, etc.) may be referred to as "vertically extending" to indicate that the structures generally extend upward from an underlying base (e.g., substrate). The vertically extending structure may extend substantially vertically relative to the upper surface of the base, or not.

Some embodiments include an integrated assembly having a first memory array including a first column of first memory cells. A first digit line extends along a first column of first memory cells and is used to address the first memory cells of the first column. A second memory array is proximate the first memory array and includes a second column of second memory cells. A second digit line extends along the second column of the second memory cells and is used to address the second column of second memory cells. A primary sense amplifier couples the first digit line opposite the second digit line. The primary sense amplifier is configured to be utilized during reading from and writing to the first and second memory cells along the first and second columns. A first secondary sense amplifier is along the first digit line and a second secondary sense amplifier is along the second digit line. The first and second secondary sense amplifiers are configured for refreshing the first and second memory cells only along the first and second digit lines.

Some embodiments include an integrated assembly having a first memory array including a first column of first memory cells. A first digit line extends along a first column of first memory cells and is used to address the first memory cells of the first column. The second memory array is adjacent to the first memory array and includes a second column of second memory cells. A second digit line extends along a second column of second memory cells and is used to address the second column of second memory cells. The primary sense amplifier is configured to oppositely couple the first digit line and the second digit line. The first secondary sense amplifier is along the first digit line and the first switch is between the first secondary sense amplifier and the first digit line. The first switch is configured to close during a first operation along the first column to shunt electrical signals through the first secondary sense amplifier. The first switch is configured to open during a second operation along the first column to enable the first secondary sense amplifier to oppositely couple a portion of the first digit line on one side of the first secondary sense amplifier with another portion of the first digit line on an opposite side of the first secondary sense amplifier. The second secondary sense amplifier is along the second digit line, and the second switch is between the second secondary sense amplifier and the second digit line. The second switch is configured to close during a first operation along the second column to shunt the electrical signal through the second secondary sense amplifier. The second switch is configured to open during a second operation along the second column to enable the second secondary sense amplifier to oppositely couple a portion of the second digit line on one side of the second secondary sense amplifier with another portion of the second digit line on an opposite side of the second secondary sense amplifier.

Some embodiments include an integrated assembly having a base, a first platform above the base, and a second platform above the first platform. The first memory array includes a first column of first memory cells. A first digit line extends along a first column of first memory cells and is used to address the first memory cells of the first column. A first portion of the first column of first memory cells is along the first terrace and a second portion of the first column of first memory cells is along the second terrace. The second memory array is adjacent to the first memory array and includes a second column of second memory cells. A second digit line extends along a second column of second memory cells and is used to address the second column of second memory cells. A first portion of a second column of second memory cells is along the first mesa and a second portion of the second column of second memory cells is along the second mesa. The primary sense amplifier is configured to oppositely couple the first digit line and the second digit line. The primary sense amplifier is along the pedestal. The first secondary sense amplifier is along the first digit line and is coupled to the first digit line through a first transistor. The first transistor has a first source/drain region coupled to a first portion of the first digit line, a second source/drain region coupled to a second portion of the first digit line, and a first gate coupled to the isolation driver. A second secondary sense amplifier along the second digit line and coupled to the second digit line through a second transistor; the second transistor has a third source/drain region coupled to a first portion of the second digit line, a second source/drain region coupled to a second portion of the second digit line, and a second gate coupled to the isolation driver.