阅读说明：本技术 半导体存储器 (Semiconductor memory device with a memory cell having a plurality of memory cells ) 是由 柳平康辅 酒向万里生 于 2018-12-19 设计创作，主要内容包括：实施方式提供一种能够使读出动作高速化的半导体存储器。实施方式的半导体存储器包含第1及第2存储单元、连接于第1及第2存储单元的字线、分别连接于第1及第2存储单元的第1及第2位线、分别连接于第1及第2位线的第1及第2感测放大器、以及控制器。第1及第2感测放大器分别包含第1至第3晶体管。第3晶体管的一端电连接于第1及第2晶体管，另一端连接于位线。在读出动作中控制器对字线施加读出电压ER。在第1时刻t5，控制器对第1及第2晶体管分别施加第1电压Vblk及第2电压Vblc，第1感测放大器经由第1及第3晶体管对第1位线施加电压，第2感测放大器经由第2及第3晶体管对第2位线施加电压。(Embodiments provide a semiconductor memory capable of speeding up a read operation. The semiconductor memory of the embodiment includes 1 st and 2 nd memory cells, word lines connected to the 1 st and 2 nd memory cells, 1 st and 2 nd bit lines connected to the 1 st and 2 nd memory cells, respectively, 1 st and 2 nd sense amplifiers connected to the 1 st and 2 nd bit lines, respectively, and a controller. The 1 st and 2 nd sense amplifiers include the 1 st to 3 rd transistors, respectively. One end of the 3 rd transistor is electrically connected to the 1 st and 2 nd transistors, and the other end is connected to the bit line. In a read operation, the controller applies a read voltage ER to the word line. At time t5, the controller applies a1 st voltage Vblk and a2 nd voltage Vblc to the 1 st and 2 nd transistors, respectively, the 1 st sense amplifier applies a voltage to the 1 st bit line through the 1 st and 3 rd transistors, and the 2 nd sense amplifier applies a voltage to the 2 nd bit line through the 2 nd and 3 rd transistors.)

1. A semiconductor memory includes:

1 st and 2 nd memory cells that store data of a plurality of bits based on threshold voltages, respectively;

word lines connected to the gates of the 1 st and 2 nd memory cells, respectively;

1 st and 2 nd bit lines connected to the 1 st and 2 nd memory cells, respectively;

1 st and 2 nd sense amplifiers connected to the 1 st and 2 nd bit lines, respectively; and

a controller; and is

The 1 st and 2 nd sense amplifiers respectively comprise a1 st transistor, a2 nd transistor and a 3 rd transistor, one end of the 3 rd transistor is respectively electrically connected with the 1 st transistor and the 2 nd transistor, and the other end is connected with a corresponding bit line,

in the read operation of the 1 st and 2 nd memory cells,

the controller applies a1 st sense voltage to the word line,

at a1 st time included in a1 st period during which the controller applies the 1 st readout voltage,

the controller applies a1 st voltage higher than a ground voltage to the 1 st transistor, applies a2 nd voltage different from the 1 st voltage to the 2 nd transistor,

at the time of the 1 st time instant,

the 1 st sense amplifier applies a voltage to the 1 st bit line via the 1 st transistor and the 3 rd transistor,

the 2 nd sense amplifier applies a voltage to the 2 nd bit line via the 2 nd transistor and the 3 rd transistor.

2. The semiconductor memory according to claim 1, wherein

The 1 st and 2 nd memory cells store 1 st data based on a1 st threshold voltage and 2 nd data based on a2 nd threshold voltage higher than the 1 st threshold voltage, respectively,

in the above-mentioned read-out operation,

the 1 st memory cell has the 2 nd threshold voltage,

the 2 nd memory cell has the 1 st threshold voltage.

3. The semiconductor memory according to claim 1, wherein

The 1 st and 2 nd sense amplifiers further include: a 4 th transistor having one end connected to a1 st node and the other end connected to the 1 st transistor; a 5 th transistor having one end connected to the 1 st node, the other end connected to the 2 nd transistor, a gate connected to the gate of the 4 th transistor, and a conductivity type different from that of the 4 th transistor; and a 6 th transistor connected between a power supply line and the 1 st node;

in each of the 1 st and 2 nd sense amplifiers, the other end of the 1 st transistor, the other end of the 2 nd transistor, and one end of the 3 rd transistor are connected to a2 nd node,

the 2 nd voltage is a voltage between the ground voltage and the 1 st voltage.

4. The semiconductor memory according to claim 3, wherein

At the 2 nd time point later than the 1 st time point included in the 1 st period,

the controller applies the 1 st voltage to the 1 st transistor and the 2 nd transistor, respectively.

5. The semiconductor memory according to claim 3, wherein

In the read operation, the controller applies a2 nd read voltage that is a read voltage applied first and lower than the 1 st read voltage before applying the 1 st read voltage to the word line,

at a 3 rd time included in a2 nd period in which the controller applies the 2 nd readout voltage, the controller applies a 3 rd voltage higher than the 2 nd voltage to the 1 st transistor and applies the 2 nd voltage to the 2 nd transistor,

at the time instant 3, it is possible to,

the 1 st sense amplifier applies a voltage to the 1 st bit line via the 2 nd transistor and the 3 rd transistor,

the 2 nd sense amplifier applies a voltage to the 2 nd bit line via the 2 nd transistor and the 3 rd transistor.

6. The semiconductor memory according to claim 5, wherein

The 1 st voltage is higher than the 3 rd voltage.

7. The semiconductor memory according to claim 3, wherein

In the read operation, the controller applies a2 nd read voltage higher than the 1 st read voltage as an initially applied read voltage before applying the 1 st read voltage to the word line,

at a 3 rd time included in a2 nd period in which the controller applies the 2 nd readout voltage, the controller applies a 3 rd voltage higher than the 2 nd voltage to the 1 st transistor and applies the 2 nd voltage to the 2 nd transistor,

at the time instant 3, it is possible to,

the 1 st sense amplifier applies a voltage to the 1 st bit line via the 1 st transistor and the 3 rd transistor,

the 2 nd sense amplifier applies a voltage to the 2 nd bit line via the 1 st transistor and the 3 rd transistor.

8. The semiconductor memory according to claim 7, wherein

The 1 st voltage is lower than the 3 rd voltage.

9. The semiconductor memory according to any one of claims 5 to 8, wherein

The 1 st and 2 nd sense amplifiers respectively have a plurality of latch circuits including a1 st latch circuit connected to a gate of the 4 th transistor and a gate of the 5 th transistor,

in the read operation, the controller updates the information held in the 1 st latch circuit based on a read result of the 2 nd read voltage.

10. The semiconductor memory according to claim 1, wherein

The 1 st and 2 nd sense amplifiers further include: a 4 th transistor to which a power supply voltage is supplied at one end; a 5 th transistor having one end connected to the other end of the 4 th transistor and the other end connected to one end of the 1 st transistor; a 6 th transistor to which a power supply voltage is supplied at one end; and a 7 th transistor having one end connected to the other end of the 6 th transistor and the other end connected to one end of the 2 nd transistor;

in each of the 1 st and 2 nd sense amplifiers, the other end of the 1 st transistor is connected to one end of the 3 rd transistor, the other end of the 2 nd transistor is connected to the one end of the 1 st transistor,

at the 1 st time, the controller applies a 3 rd voltage to the 5 th transistor, applies a 4 th voltage higher than the 3 rd voltage to the 7 th transistor, applies a voltage of a1 st logic level to the 6 th transistor of the 1 st sense amplifier, and applies a voltage of a2 nd logic level different from the 1 st logic level to the 6 th transistor of the 2 nd sense amplifier,

the 2 nd voltage is higher than the 1 st voltage.

11. The semiconductor memory according to claim 10, wherein

At the 2 nd time point later than the 1 st time point included in the 1 st period,

the controller applies the 3 rd voltage to the 1 st transistor, applies a 5 th voltage lower than the 3 rd voltage to the 2 nd transistor, applies the 4 th voltage to the 5 th transistor, and applies a 6 th voltage lower than the 3 rd voltage to the 7 th transistor.

12. The semiconductor memory according to claim 10, wherein

In the read operation, the controller applies a2 nd read voltage that is a read voltage applied first and lower than the 1 st read voltage before applying the 1 st read voltage to the word line,

at a 3 rd time included in a2 nd period in which the controller applies the 2 nd readout voltage, the controller applies a 7 th voltage higher than the 2 nd voltage to the 1 st transistor and applies the 2 nd voltage to the 2 nd transistor,

at the 3 rd time, the controller applies the 3 rd voltage to the 5 th transistor, the 4 th voltage to the 7 th transistor, the 2 nd logic level voltage to the 6 th transistor of the 1 st sense amplifier, and the 2 nd logic level voltage to the 6 th transistor of the 2 nd sense amplifier.

13. The semiconductor memory according to claim 12, wherein

The 1 st voltage is higher than the 7 th voltage.

14. The semiconductor memory according to claim 10, wherein

In the read operation, the controller applies a2 nd read voltage higher than the 1 st read voltage as an initially applied read voltage before applying the 1 st read voltage to the word line,

at a 3 rd time included in a period in which the controller applies the 2 nd read voltage, the controller applies a 7 th voltage higher than the 2 nd voltage to the 1 st transistor and applies the 2 nd voltage to the 2 nd transistor,

at the 3 rd time, the controller applies the 3 rd voltage to the 5 th transistor, the 4 th voltage to the 7 th transistor, the 1 st logic level voltage to the 6 th transistor of the 1 st sense amplifier, and the 1 st logic level voltage to the 6 th transistor of the 2 nd sense amplifier.

15. The semiconductor memory according to claim 14, wherein

The 1 st voltage is lower than the 7 th voltage.

16. The semiconductor memory according to any one of claims 12 to 15, wherein

The controller changes a voltage applied to the 6 th transistor at the 1 st time based on a result of reading the 2 nd read voltage.

17. A semiconductor memory includes:

a storage unit storing a plurality of bits of data based on a threshold voltage;

word lines connected to the gates of the memory cells;

a bit line connected to the memory cell;

a sense amplifier including a1 st transistor having one end supplied with a power supply voltage, a2 nd transistor having one end connected to the other end of the 1 st transistor, a 3 rd transistor having one end connected to the other end of the 2 nd transistor, and a 4 th transistor having one end connected to the other end of the 3 rd transistor and the other end connected to the bit line; and

a controller for applying a1 st read voltage and a2 nd read voltage different from the 1 st read voltage to the word line in a read operation;

the controller applies a1 st voltage higher than a ground voltage to the 2 nd transistor, applies a2 nd voltage higher than the ground voltage to the 3 rd transistor, and applies a 3 rd voltage higher than the ground voltage and lower than the 2 nd voltage to the 3 rd transistor after applying the 2 nd voltage to the 3 rd transistor in a1 st period in which the controller applies the 1 st read voltage,

in a2 nd period in which the controller applies the 2 nd readout voltage, the controller applies the 1 st voltage to the 2 nd transistor, applies the 3 rd voltage to the 3 rd transistor, and does not apply a voltage higher than the 3 rd voltage to the 3 rd transistor.

18. The semiconductor memory according to claim 17, wherein

The controller sets whether or not a voltage higher than the 3 rd voltage is applied to the 3 rd transistor for each read voltage during a period in which the read voltage is applied to the word line.

19. The semiconductor memory according to claim 17 or 18, wherein

The 1 st readout voltage is higher than the 2 nd readout voltage.

20. The semiconductor memory according to claim 17 or 18, wherein

The controller is capable of applying a 3 rd read voltage to the word line that is different from both the 1 st read voltage and the 2 nd read voltage,

in a 3 rd period in which the controller applies the 3 rd readout voltage, the controller applies the 1 st voltage to the 2 nd transistor and applies a 4 th voltage, which is higher than the 3 rd voltage and is different from the 3 rd voltage, to the 3 rd transistor.

Technical Field

Background

A NAND (Not And) type flash memory capable of nonvolatile storage of data is known.

Disclosure of Invention

Drawings

Fig. 1 is a block diagram showing an example of the configuration of the semiconductor memory according to embodiment 1.

Fig. 2 is a circuit diagram showing an example of a circuit configuration of a memory cell array included in the semiconductor memory according to embodiment 1.

Fig. 3 is a plan view showing an example of a planar layout of a memory cell array included in the semiconductor memory according to embodiment 1.

Fig. 4 is a plan view showing an example of a planar layout in a cell region of a memory cell array provided in the semiconductor memory according to embodiment 1.

Fig. 5 is a cross-sectional view showing an example of a cross-sectional structure in a cell region of a memory cell array included in the semiconductor memory according to embodiment 1.

Fig. 6 is a cross-sectional view showing an example of a cross-sectional structure of a memory pillar in the semiconductor memory according to embodiment 1.

Fig. 7 is a plan view showing an example of a planar layout in a lead-out region of a memory cell array included in the semiconductor memory according to embodiment 1.

Fig. 8 is a cross-sectional view showing an example of a cross-sectional structure in a lead-out region of a memory cell array included in the semiconductor memory according to embodiment 1.

Fig. 9 is a circuit diagram showing an example of a circuit configuration of a row decoder module included in the semiconductor memory according to embodiment 1.

Fig. 10 is a circuit diagram showing an example of a circuit configuration of a sense amplifier module included in the semiconductor memory according to embodiment 1.

Fig. 11 is a circuit diagram showing an example of a more detailed circuit configuration of a sense amplifier module included in the semiconductor memory according to embodiment 1.

Fig. 12 is a diagram showing an example of threshold distribution, data distribution, and read voltage of memory cell transistors in the semiconductor memory according to embodiment 1.

Fig. 13 is a timing chart showing an example of a read operation of the semiconductor memory according to embodiment 1.

Fig. 14 is a timing chart showing an example of a read operation in the variation of embodiment 1.

Fig. 15 is a circuit diagram showing an example of a circuit configuration of a sense amplifier module included in the semiconductor memory according to embodiment 2.

Fig. 16 is a timing chart showing an example of a read operation of the semiconductor memory according to embodiment 2.

Fig. 17 is a timing chart showing an example of a read operation in the modification of embodiment 2.

Fig. 18 is a circuit diagram showing an example of a circuit configuration of a sense amplifier module included in the semiconductor memory according to embodiment 3.

Fig. 19 is a timing chart showing an example of a read operation in the comparative example of embodiment 3.

Fig. 20 is a table showing an example of setting of a kick operation in a read operation of the semiconductor memory according to embodiment 3.

Fig. 21 is a timing chart showing an example of a read operation of the semiconductor memory according to embodiment 3.

Fig. 22 is a timing chart showing an example of a read operation in the modification of embodiment 3.

Fig. 23 is a table showing an example of setting of a kick operation in a read operation of the semiconductor memory according to embodiment 4.

Fig. 24 is a timing chart showing an example of a read operation of the semiconductor memory according to embodiment 4.

Fig. 25 is a timing chart showing an example of the reading operation in the variation of embodiment 4.

Fig. 26 is a timing chart showing an example of the read operation in variation 1.

Fig. 27 is a timing chart showing an example of the reading operation in variation 2.

Embodiments relate to a semiconductor memory.