阅读说明：本技术 半导体设备及其测试设备和方法 (Semiconductor device, and test apparatus and method thereof ) 是由 黄淙泰 于 2019-03-05 设计创作，主要内容包括：一种测试设备包括测试安装电路，该测试安装电路上安装有多个半导体设备作为相应的被测设备。每个被测设备中包括对应的延迟控制电路和目标电路。提供电耦接到测试安装电路的测试逻辑器件。测试逻辑器件被配置为生成测试输入，测试输入被并行地提供给多个被测设备内的延迟控制电路。延迟控制电路至少包括第一延迟控制电路和第二延迟控制电路，第一延迟控制电路和第二延迟控制电路被配置为在相对于彼此异相的相应的第一测试时间间隔和第二测试时间间隔期间向对应的第一目标电路和第二目标电路传递测试输入，以便在测试期间实现测试安装电路的更均匀的功耗需求。(A test apparatus includes a test mounting circuit on which a plurality of semiconductor devices are mounted as respective devices under test. Each device under test includes a corresponding delay control circuit and a target circuit. A test logic device electrically coupled to the test mounting circuit is provided. The test logic device is configured to generate test inputs that are provided in parallel to delay control circuits within the plurality of devices under test. The delay control circuit includes at least first and second delay control circuits configured to pass test inputs to corresponding first and second target circuits during respective first and second test time intervals that are out of phase with respect to each other in order to achieve more uniform power consumption requirements of the test mounted circuit during testing.)

1. A test apparatus, comprising:

a test mounting circuit on which a plurality of semiconductor devices are mounted as respective devices under test including corresponding delay control circuits and target circuits therein; and

a test logic device electrically coupled to the test mounting circuit, the test logic device configured to generate test inputs that are provided in parallel to delay control circuits within the plurality of devices under test, the delay control circuits including at least a first delay control circuit and a second delay control circuit configured to pass the test inputs to corresponding first and second target circuits during respective first and second test time intervals that are out of phase with respect to each other.

2. The test apparatus of claim 1, wherein the first and second delay control circuits receive the same test input from the test logic device at the same time, but provide the test input to the first and second target circuits at different times, such that a first test mode is initiated within the first target circuit using the test input before or after a second test mode is initiated within the second target circuit using the test input.

3. The test apparatus of claim 2, wherein the first delay control circuit comprises a timing control circuit that causes the test input to be passed through the first delay control circuit to the first target circuit by a programmable first delay amount.

4. The test apparatus of claim 3, wherein the first delay control circuit is configured to bypass the timing control circuit when output test data generated by the first target circuit is passed through the first delay control circuit.

5. The test apparatus of claim 2, wherein the first delay control circuit comprises a first timing control circuit that causes a plurality of portions of the test input to be passed through the first delay control circuit to the first target circuit to be delayed by a corresponding plurality of different delay amounts.

6. A test apparatus, comprising:

a Device Under Test (DUT) mounting circuit on which a plurality of semiconductor devices are mounted as DUTs; and

test logic configured to generate test inputs provided to target circuitry in the plurality of semiconductor devices and to determine whether the DUT is defective based on test outputs from the plurality of semiconductor devices,

wherein the test logic device is configured to provide the test input to the plurality of semiconductor devices in parallel, an

Wherein a timing of transmitting the test input to the target circuit in some of the plurality of semiconductor devices is different from a timing of transmitting the test input to the target circuit in some of the other of the plurality of semiconductor devices.

7. The test apparatus of claim 6, wherein each of the plurality of semiconductor devices includes a delay control circuit that receives the test input, delays the test input, and outputs a delayed test input, and

wherein the test logic device is configured to provide delay control signals to the plurality of semiconductor devices to set different amounts of delay for the test input.

8. The test apparatus of claim 6, wherein the plurality of semiconductor devices are classified into first to Nth groups, where N is an integer equal to or greater than 2, each of the first to Nth groups including one or more semiconductor devices,

wherein the target circuits in the semiconductor devices belonging to the same group receive the test input simultaneously, and the target circuits in the semiconductor devices belonging to different groups receive the test input at different times.

9. The test apparatus of claim 6, wherein the plurality of semiconductor devices includes M semiconductor devices, where M is an integer equal to or greater than 2,

wherein the target circuit of the M semiconductor devices receives the test input at different times.

10. The test device of claim 6, wherein the plurality of semiconductor devices includes a first semiconductor device comprising a plurality of channels, each of the plurality of channels receiving the test input via a separate interface,

wherein target circuits in the plurality of channels receive the test input at different times.

11. The test apparatus of claim 10, wherein the first semiconductor device comprises a High Bandwidth Memory (HBM).

12. The test apparatus of claim 6, wherein the plurality of semiconductor devices comprise semiconductor packages,

wherein the test logic device is on a test board including the DUT mounted circuitry.

13. The test apparatus of claim 6, wherein the plurality of semiconductor devices comprise dies formed in a semiconductor wafer,

wherein the test logic device is included in a probe card for testing the dies of the semiconductor wafer.

14. A semiconductor device, comprising:

a delay control circuit configured to receive a test input provided from an external test logic device in a test mode, delay the test input, and output the delayed test input; and

a target circuit configured to receive a delayed test input from the delay control circuit,

wherein the delay control circuit is configured to delay the test input according to a delay amount set in response to a delay control signal in the test mode.

15. The semiconductor device of claim 14, wherein the delay control circuit comprises:

a buffer circuit configured to receive the test input from the external test logic device; and

a timing control circuit configured to adjust a timing of transmitting the test input to the target circuit by a delay operation according to the set delay amount.

16. The semiconductor device of claim 15, wherein the buffer circuit comprises: a receive buffer configured to receive the test input; and a transmit buffer configured to transmit test outputs generated using the test inputs to the external test logic device,

wherein the timing control circuit is at an output terminal of the receive buffer to delay the test input, and

wherein the test output is provided to the transmit buffer without passing through the timing control circuit.

17. The semiconductor device of claim 14, wherein the delay control signal is provided from the external test logic device.

18. The semiconductor device of claim 14, wherein the semiconductor device comprises a die formed in a semiconductor wafer, and

wherein the delay control signal is provided to the delay control circuit from an external probe card.

19. The semiconductor device of claim 14, wherein the semiconductor device comprises a semiconductor package comprising one or more semiconductor chips,

wherein the delay control signal is supplied from the external test logic device to the delay control circuit through a wiring formed in a test board.

20. The semiconductor device of claim 14, wherein the semiconductor device comprises a plurality of channels configured to receive the test input via respective independent interfaces, and the delay control circuit is configured to provide the test input to the plurality of channels,

wherein the test input is provided to the target circuit in the plurality of channels at different times according to a delay amount set in response to the delay control signal.

21. The semiconductor device of claim 14, wherein the delay control circuit comprises: a buffer circuit configured to receive the test input from the external test logic device; and a timing control circuit configured to perform a delay operation according to the set delay amount,

wherein the buffer circuit is configured to receive a normal input from outside also in a normal mode of the semiconductor device,

wherein the normal input is provided to the target circuit without delay when the timing control circuit is disabled in the normal mode.

22. A method of testing a semiconductor device, the semiconductor device including a delay control circuit having a programmable delay amount, the method comprising:

setting a delay amount of the delay control circuit in response to a delay control signal in a test mode;

receiving a test input from an external test logic device;

performing a delay process on the received test input according to the set delay amount; and

sending the delayed test input to a target circuit in the semiconductor device,

wherein a timing of transmitting the test input to the target circuit is adjusted according to the set delay amount.

23. The method of claim 22, wherein the semiconductor device comprises a semiconductor package comprising a first semiconductor chip and a second semiconductor chip,

wherein performing the delay process comprises: generating a first delayed test input provided to a target circuit of the first semiconductor chip and a second delayed test input provided to a target circuit of the second semiconductor chip,

wherein a timing of providing the first delayed test input to the target circuit of the first semiconductor chip and a timing of providing the second delayed test input to the target circuit of the second semiconductor chip are different from each other.

24. The method of claim 22, wherein the semiconductor device comprises a semiconductor chip comprising a first channel and a second channel in communication with each other via independent interfaces,

wherein performing the delay process comprises: generating a first delayed test input provided to a first target circuit of the first channel and a second delayed test input provided to a second target circuit of the second channel,

wherein a timing of providing the first delayed test input to the first target circuit and a timing of providing the second delayed test input to the second target circuit are different from each other.

25. The method of claim 22, wherein the semiconductor device comprises a semiconductor wafer having a plurality of dies formed therein, the plurality of dies comprising a first die and a second die, wherein each of the first die and the second die comprises a delay control circuit,

wherein, in response to the delay control signal, a delay amount having a first value is set in the first die and a delay amount having a second value different from the first value is set in the second die.

Technical Field

The present inventive concept relates to a method of testing a semiconductor device, and more particularly, to a test apparatus and a test method of reducing occurrence of peak noise and/or peak power consumption during a test, and a semiconductor device on which a test is performed using the test apparatus and the test method.

Background

With the rapid growth of the electronics industry and consumer demand, electronic devices have become more compact, more complex, and support greater capacity. Therefore, testing of semiconductor devices included in electronic devices becomes more complicated. For example, in a production test environment, a semiconductor device including tens or hundreds of wafer dies or semiconductor packages may be tested simultaneously as a Device Under Test (DUT). Furthermore, when a Device Under Test (DUT) corresponds to a multi-channel and/or high capacity memory device, peak noise and/or peak power consumption may be excessive as the operating current increases to tens of amperes (a).

Disclosure of Invention

The present inventive concept provides a test apparatus and a test method capable of reducing test performance degradation due to peak noise and/or peak power consumption in a test environment, and a semiconductor apparatus on which a test is performed using the test apparatus and the test method.

According to some embodiments of the present invention, there is provided a test apparatus including a test mounting circuit and a test logic device. The test-mounting circuit has mounted thereon a plurality of semiconductor devices as respective devices under test. Each of these devices under test includes a corresponding delay control circuit and a target circuit to be tested. Test logic devices electrically coupled to the test mounting circuitry are configured to generate test inputs, which are typically provided in parallel to delay control circuits within multiple devices under test. The delay control circuits may include at least first and second delay control circuits configured to pass test inputs to corresponding first and second target circuits during respective first and second test time intervals that are out of phase with respect to each other. In particular, the first delay control circuit and the second delay control circuit may receive the same test input from the test logic device at the same time, but provide the test input to the first target circuit and the second target circuit at different times, such that the first test mode is initiated within the first target circuit using the test input before or after the second test mode is initiated within the second target circuit using the test input.

In some embodiments of the invention, the first delay control circuit may include a timing control circuit that causes a programmable first delay amount of the test input delay to be communicated to the first target circuit through the first delay control circuit. Additionally, the first delay control circuit may be configured to bypass the timing control circuit when the output test data generated by the first target circuit is passed through the first delay control circuit. In still other embodiments of the present invention, the first delay control circuit may include a first timing control circuit that delays passing the plurality of portions of the test input through the first delay control circuit to the first target circuit by a corresponding plurality of different delay amounts.

According to still further embodiments of the present invention, a method of testing a semiconductor device includes: a test input is provided to a test mounting circuit on which a plurality of identical semiconductor devices are mounted as devices under test, each of which includes a corresponding delay control circuit and a target circuit. Test inputs are then passed from the test mount circuit to a plurality of delay control circuits within the plurality of devices under test. Next, test inputs are passed from the plurality of delay control circuits to the corresponding plurality of target circuits to be tested in a phased, asynchronous manner such that a first test mode is initiated within a first one of the target circuits using the test inputs before or after a second test mode is initiated within a second one of the target circuits using the test inputs. According to some of these embodiments of the invention, the transferring comprises: the test inputs are passed from all of the plurality of delay control circuits to all of the corresponding plurality of target circuits to be tested in a phased, asynchronous manner such that each of the plurality of target circuits is tested in an asynchronous manner with the same test input relative to all other target circuits. Additionally, delay control circuitry within the device under test may provide programmable delays to the test inputs. Additionally, passing the test input from the test mounting circuit may include: test inputs are passed in parallel from the test mounting circuit to a plurality of delay control circuits within a plurality of devices under test.

According to another embodiment of the present invention, there is provided a test apparatus including: a Device Under Test (DUT) mounting circuit on which a plurality of semiconductor devices are mounted as DUTs; and test logic configured to generate test inputs provided to target circuits in the plurality of semiconductor devices and to determine whether the DUT is defective based on the test outputs from the plurality of semiconductor devices. The test logic device may be configured to provide test inputs to the plurality of semiconductor devices in parallel, and a timing of transferring the test inputs to the target circuits in some of the plurality of semiconductor devices may be different from a timing of transferring the test inputs to the target circuits in other some of the plurality of semiconductor devices.

According to another embodiment of the inventive concept, there is provided a semiconductor apparatus including: a delay control circuit configured to receive a test input provided from an external test logic device in a test mode, delay the test input, and output the delayed test input; and a target circuit configured to receive the delayed test input from the delay control circuit. The delay control circuit is configured to delay the test input according to a delay amount set in response to the delay control signal in the test mode. According to another embodiment of the present invention, a method of testing a semiconductor device including a delay control circuit having a programmable delay amount is provided. The method can comprise the following steps: setting a delay amount of the delay control circuit in response to the delay control signal in the test mode; receiving a test input from an external test logic device; performing a delay process on the received test input according to the set delay amount; and sending the delayed test input to a target circuit in the semiconductor device. The timing of the test input to the target circuit may be adjusted according to the set delay amount.

Drawings

Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

fig. 1 is a block diagram of a test apparatus according to an example embodiment of the inventive concept;

fig. 2 and 3 are block diagrams showing examples of a delay control circuit provided in a semiconductor device;

fig. 4A and 4B are schematic diagrams illustrating an example of a design for testability (DFT) circuit according to an embodiment of the inventive concept;

fig. 5 and 6 are flowcharts of a method of testing a semiconductor device according to an example embodiment of the inventive concepts;

fig. 7A and 7B are views illustrating an example of a test operation of a semiconductor wafer according to an example embodiment of the inventive concepts;

fig. 8 and 9 are schematic diagrams respectively showing an example of group setting of a plurality of Devices Under Test (DUTs) arranged on a test board and an example of delaying a test input;

FIGS. 10 and 11 are block diagrams illustrating examples of setting a delay amount of a DUT according to various methods;

fig. 12 is a block diagram illustrating an example of implementing a semiconductor device according to an example embodiment of the inventive concepts as a High Bandwidth Memory (HBM);

fig. 13 and 14 are circuit diagrams illustrating examples of a delay control circuit according to example embodiments of the inventive concepts; and

fig. 15 is a block diagram illustrating an example of implementing a semiconductor device according to an example embodiment of the inventive concepts as a memory device.

Detailed Description

The present invention will now be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like reference numerals refer to like elements throughout the drawings.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," "including," "has," "having," and variations thereof, when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. Rather, the term "consisting of … …" when used in this specification indicates that the stated features, steps, operations, elements, and/or components, and excludes additional features, steps, operations, elements, and/or components.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 is a block diagram of a test apparatus 100 according to an example embodiment of the inventive concepts. Referring to fig. 1, a test apparatus 100 for testing a semiconductor device may include a tester (or test logic device) 110 and at least one Device Under Test (DUT) to be tested. In an embodiment, test apparatus 100 may include a test board, and the test board may include DUT mounting circuitry 120 on which a plurality of DUTs are mounted. Although fig. 1 illustrates an example in which the test logic device 110 is mounted on a test board, embodiments of the inventive concept are not limited thereto. For example, testing the logic device 110 may be defined as being external to the test board.

The DUT mounting circuit 120 may include a plurality of sockets (not shown) on which a plurality of semiconductor devices 121_1 to 121_ N are mounted as DUTs, respectively. Although not shown in fig. 1, the test apparatus 100 may further include: a communication device (not shown) for communicating with an external host requesting a test; a memory (not shown) for temporarily storing various types of information related to various tests; and a power supply circuit (not shown) for supplying power to various devices provided in the test apparatus 100. In addition, the test apparatus 100 according to an example embodiment of the inventive concept may be defined differently. For example, in fig. 1, components other than the plurality of semiconductor devices 121_1 to 121_ N may be defined to constitute the test apparatus 100.

According to an embodiment, the test logic device 110 may be implemented as a semiconductor chip, such as a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), or an Application Processor (AP), and may transmit and receive various information to and from the semiconductor devices 121_1 to 121_ N according to a parallel communication method. For example, the test logic device 110 may provide test inputs to the DUT mounting circuit 120 through a plurality of channels, and the plurality of semiconductor devices 121_1 to 121_ N in the DUT mounting circuit 120 may receive the test inputs from the test logic device 110 in parallel.

The test process for determining whether the semiconductor device is defective may be performed at various stages of a semiconductor process, and may include, for example, a wafer level test and a test after the wafer level test. Wafer level testing may correspond to testing of individual semiconductor dies at the wafer level. The test after the wafer level test may be a test for a semiconductor die before performing packaging, or may be a test for a semiconductor package in which one semiconductor die (or semiconductor chip) is packaged. The test for the semiconductor package may be a test for a semiconductor package including a plurality of semiconductor chips. According to an embodiment, when the test apparatus 100 shown in fig. 1 is an apparatus for performing a wafer level test, the plurality of semiconductor devices 121_1 to 121_ N may respectively correspond to a plurality of semiconductor dies formed on a semiconductor wafer, and the DUT mounting circuit 120 may be an apparatus on which the semiconductor wafer is placed. Alternatively, when the test apparatus 100 shown in fig. 1 is an apparatus for testing a semiconductor package, each of the semiconductor devices 121_1 to 121_ N mounted on the DUT mounting circuit 120 may be a semiconductor package.

The semiconductor devices 121_1 to 121_ N may be devices that perform various functions. For example, each of the semiconductor devices 121_1 to 121_ N may be a memory device including a memory cell array. For example, the memory device may be a Dynamic Random Access Memory (DRAM), such as a double data rate synchronous dynamic random access memory (DDR SDRAM), a Low Power Double Data Rate (LPDDR) SDRAM, a Graphics Double Data Rate (GDDR) SDRAM, or a Rambus Dynamic Random Access Memory (RDRAM). Alternatively, the memory device may correspond to a non-volatile memory, such as a flash memory, a magnetic ram (mram), a ferroelectric ram (feram), a phase change ram (pram), or a resistive ram (reram).

According to the embodiment, the test inputs Input _1 to Input _ M from the test logic device 110 may be supplied in parallel to the semiconductor devices 121_1 to 121_ N in the DUT mounting circuit 120. Each of the semiconductor devices 121_1 to 121_ N may include a delay control circuit 122. The delay control circuit 122 may delay the received test input and provide the delayed test input to a target circuit (not shown) in the semiconductor device. For example, referring to the semiconductor device 121_1 as a first semiconductor, the delay control circuit 122 may receive and delay a first test Input (i.e., the test Input _1), and transmit the delayed first test Input to a target circuit in the first semiconductor device (i.e., the semiconductor device 121_ 1).

According to an embodiment, the plurality of semiconductor devices 121_1 to 121_ N may delay the respective test inputs according to different delay amounts. Accordingly, the test inputs Input _1 to Input _ M are supplied to the DUT mounting circuit 120 in parallel (or simultaneously), and the plurality of semiconductor devices 121_1 to 121_ N can supply the respective test inputs to the respective internal target circuits at different points in time. Accordingly, it is possible to perform testing on a plurality of semiconductor devices 121_1 to 121_ N at different timings, thereby dispersing large peak noise that may be caused by simultaneous testing, and thus it is possible to prevent the characteristics of the DUT from deteriorating in a parallel test environment.

According to an embodiment, the number of test inputs Input _1 to Input _ M may be equal to the number of semiconductor devices 121_1 to 121_ N. The number of test inputs Input _1 to Input _ M may be greater than or less than the number of semiconductor devices 121_1 to 121_ N. For example, when one test Input is provided to each of the semiconductor devices 121_1 to 121_ N, the number of test inputs Input _1 to Input _ M may be equal to the number of semiconductor devices 121_1 to 121_ N. When the semiconductor devices 121_1 to 121_ N are classified into a plurality of groups and the same test Input is provided for each group, the number of test inputs Input _1 to Input _ M may be smaller than the number of semiconductor devices 121_1 to 121_ N. When each of the semiconductor devices 121_1 to 121_ N includes a plurality of channels communicating through independent interfaces and a separate test Input is provided to each channel, the number of the test inputs Input _1 to Input _ M may be greater than the number of the semiconductor devices 121_1 to 121_ N.

According to an embodiment, the delay control circuit 122 within each of the semiconductor devices 121_1 to 121_ N may delay the test input according to a programmable delay amount. For example, each of the semiconductor devices 121_1 to 121_ N may include an element for generating a delay control signal (where the delay control signal is used to set a delay amount of the delay control circuit 122), and may delay the test input according to the set delay amount during the test operation mode. In the test operation mode, the test logic device 110 may provide the delay control signal Ctrl _ delay to the semiconductor devices 121_1 to 121_ N, and each of the semiconductor devices 121_1 to 121_ N may set a delay amount in response to the delay control signal Ctrl _ delay.

According to the embodiment, when the delay amounts of the delay control circuits 122 of the semiconductor devices 121_1 to 121_ N are differently set, timings of supplying the test inputs Input _1 to Input _ M to the target circuits of the semiconductor devices 121_1 to 121_ N may be different from each other, and thus timings of performing the tests on the semiconductor devices 121_1 to 121_ N may be different from each other.

The plurality of semiconductor devices 121_1 to 121_ N may be classified into one or more groups, and each group may include one or more semiconductor devices. Further, when the delay amount of the delay control circuit 122 is differently set on a group basis, the test input may be simultaneously supplied to the target circuits of the semiconductor devices belonging to the same group. For example, the delay control circuits 122 of the semiconductor devices belonging to the same group may delay the test input according to the same delay amount. On the other hand, the delay control circuits 122 of the semiconductor devices belonging to different groups may delay the test input according to different delay amounts.

When any one of the semiconductor devices includes a plurality of channels for receiving test inputs through independent interfaces as described above, tests may be performed on the plurality of channels of each of the semiconductor devices 121_1 to 121_ N at different times. In an embodiment, each of the semiconductor devices 121_1 to 121_ N may include a plurality of delay control circuits 122 respectively corresponding to a plurality of channels and target circuits respectively corresponding to the plurality of delay control circuits 122, and the delay control circuits 122 of the plurality of channels may delay the test input according to different delay amounts.

According to the above-described embodiments, the semiconductor devices 121_1 to 121_ N, which may consume a large amount of current when operating in a parallel test environment, can be prevented from simultaneously performing the same operation. Accordingly, the peak current and the peak noise of the test apparatus 100 can be reduced, and the characteristics of the DUT can be prevented from deteriorating in the test environment. In addition, since it is not necessary to sequentially provide the test inputs Input _1 to Input _ M for each semiconductor device from the viewpoint of testing the logic device 110, it is possible to prevent the test speed from deteriorating in a parallel test environment.

When the semiconductor devices 121_1 to 121_ N sequentially perform process operations using the test inputs Input _1 to Input _ M, the test logic device 110 may sequentially receive test results from the semiconductor devices 121_1 to 121_ N of the DUT mounting circuit 120, and may determine whether the semiconductor devices 121_1 to 121_ N are defective based on the logic process. For example, the test logic device 110 may determine whether the semiconductor devices 121_1 to 121_ N are defective based on determining whether a pattern (pattern) of test inputs Input _1 to Input _ M supplied to the semiconductor devices 121_1 to 121_ N is the same as a pattern of test outputs supplied from the semiconductor devices 121_1 to 121_ N.

Fig. 2 and 3 are block diagrams showing examples of a delay control circuit provided in a semiconductor device. Referring to fig. 2, the semiconductor apparatus 200A may include a target circuit 220A receiving a test input and the delay control circuit described above. The delay control circuit may also be referred to as a design for test (DFT) circuit 210A, which is a circuit for managing test operations in the semiconductor apparatus 200A. As shown in FIG. 2, test Input (e.g., from an external test logic device) is sent to the target circuit 220A via the DFT circuit 210A.

The DFT circuitry 210A may include buffer circuitry (e.g., DFT buffer 211A) for receiving the test Input from the external test logic device and timing control circuitry 212A for receiving the test Input provided by the DFT buffer 211A and delaying the received test Input. The target circuit 220A may further include a buffer 221A for receiving the delayed test input, and the buffer 221A may provide the delayed test input to another circuit block (not shown) in the semiconductor apparatus 200A. For example, when the semiconductor device 200A corresponds to a memory device including a memory cell array therein, the delayed test input may have a pattern to be stored in the memory cell array and may be provided to the memory cell array.

According to an embodiment, the timing control circuit 212A may include a programmable delay circuit, and the delay amount of the timing control circuit 212A may be programmed by various methods such as fuse cutting. For example, a control logic device (not shown) for generating a delay control signal according to a pattern may be provided in the semiconductor apparatus 200A, and the delay amount of the timing control circuit 212A may be set based on control of the control logic device in the test mode. When the above-described external test logic device supplies the delay control signal to the semiconductor apparatus 200A, the delay amount of the timing control circuit 212A can be set.

For example, a large number of semiconductor devices 200A may be mass-produced, the DFT circuit 210A may be provided in each of the large number of semiconductor devices 200A, and different delay control signals may be provided to the semiconductor devices 200A in the test mode. Therefore, the delay amount of the test Input of the plurality of semiconductor devices 200A mounted on one test board can be set differently, and thus the timing of transferring the test Input to the target circuit 220A in the plurality of semiconductor devices 200A can be adjusted differently. Therefore, when a test operation is performed in a parallel test environment, tests can be performed on a plurality of semiconductor devices 200A at different timings, regardless of when the test Input is applied from the external test logic device. If a plurality of semiconductor devices 200A are set as one group and tests are performed on the semiconductor devices 200A in the same group at the same timing according to the above-described example, the same delay amount may be set in the timing control circuits 212A of the semiconductor devices 200A of the same group. On the other hand, for the semiconductor devices 200A in different groups, different delay amounts may be set for the respective groups.

The semiconductor apparatus 200A may perform signal processing using the received test Input and supply the processing result as a test Output to the external test logic device. For example, the DFT buffer 211A may include an Input buffer and a transmit buffer, and the test Input received by the Input buffer may be provided to the target circuit 220A via the timing control circuit 212A, while the test output from the target circuit 220A may be provided to the DFT buffer 211A without passing through the timing control circuit 212A.

Although an example in which the target circuit 220A (to which the test Input is provided) includes the buffer 221A is shown in fig. 2, the target circuit 220A may be defined differently. For example, when the semiconductor device 200A corresponds to a memory device, the test Input may be supplied to various circuit blocks related to memory operations in the memory device via the buffer 221A, and the target circuit 220A may be defined to include various circuit blocks. For example, according to the delay processing of the timing control circuit 212A, the timing at which the test Input is supplied to at least some of the various circuit blocks can be adjusted.

An example in which one semiconductor device 200B includes a plurality of channels is shown in fig. 3.

Referring to fig. 3, the semiconductor apparatus 200B may include a DFT circuit 210B and a target circuit 220B, and may supply a test input from an external test logic device to the target circuit 220 via the DFT circuit 210B. In addition, the DFT circuitry 210B may include a DFT buffer 211B and timing control circuitry 212B. Assuming that the semiconductor apparatus 200B includes a channels, the target circuit 220B may include first to a-th channel buffers 221B _1 to 221B _ a.

Although fig. 3 shows an example in which one test Input is supplied to the timing control circuit 212B via the DFT buffer 211B, and the timing control circuit 212B branches and supplies the test Input to the first through a-th channel buffers 221B _1 through 221B _ a, embodiments of the inventive concept are not limited thereto. For example, the DFT circuit 210B may include a plurality of DFT buffers 211B, the external test logic device may supply a plurality of test inputs respectively corresponding to a plurality of channels to the DFT circuit 210B, and the timing control circuit 212B may perform a delay processing operation on the plurality of test inputs. For example, different delay amounts may be applied to the plurality of test inputs, and the plurality of test inputs may be supplied to the first through a-th channel buffers 221B _1 through 221B _ a of the target circuit 220B, respectively, at different timings.

The test inputs supplied to the first through a-th channel buffers 221B _1 through 221B _ a may be independently transmitted to circuit blocks included in a plurality of channels. For example, when the test Input corresponds to a pattern to be written to the memory cell array, the test Input may be supplied to the memory cell arrays provided in the plurality of channels at different timings.

Fig. 4A and 4B are schematic diagrams illustrating an example of a DFT circuit according to an embodiment of the inventive concept. Fig. 4A shows a case where a test input in the test mode and a normal input in the normal mode are received via different pads. On the other hand, fig. 4B shows a case where the test input and the normal input are received via the same pad.

Referring to fig. 4A, the semiconductor device may include a first input/output buffer IO Buf _ N for receiving a normal input via the first PAD1 in the normal mode and a second input/output buffer IO Buf _ T for receiving a test input via the second PAD2 in the test mode. Although one first PAD (i.e., the first PAD1) for receiving a normal input and one second PAD (i.e., the second PAD2) for receiving a test input are shown in fig. 4A, the semiconductor device may include a plurality of first PADs for receiving a normal input and a plurality of second PADs for receiving a test input. For example, the semiconductor device may transmit and receive information through the external memory controller and the first PAD1, and may transmit and receive information through the tester (or the test logic device) and the second PAD 2.

According to an embodiment, the Delay control circuit Delay Ctrl may be placed on a path through which the test input is transmitted via the second input/output buffer IOBuf _ T, and a Delay amount of the Delay control circuit Delay Ctrl may be set in response to the Delay control signal in the test mode. As described above, the Delay amount of the Delay control circuit Delay Ctrl may be set in response to a Delay control signal from an external test logic device or a control logic device in the semiconductor apparatus in the test mode.

The test output may be generated after some delay time after the test input is provided to the target circuit. According to an embodiment, the test output may be transmitted to the outside via the second PAD2 without passing through the Delay control circuit Delay Ctrl.

Referring to fig. 4B, the input/output buffer IO Buf of the semiconductor device may receive a normal input via the PAD in the normal mode. In addition, the input/output buffer IOBuf may receive a test input via the PAD in the test mode. In the test mode of the semiconductor apparatus, the Delay amount of the Delay control circuit Delay Ctrl may be set according to the above-described embodiment, and a test input may be supplied to the target circuit through the Delay control circuit Delay Ctrl.

The input/output buffer IO Buf may be used to receive a normal input in the normal mode, and may provide the normal input to the target circuit without delay. According to an embodiment, the Delay control circuit Delay Ctrl may receive the mode control signal Ctrl _ mode, and may enable or disable the Delay operation according to the mode control signal Ctrl _ mode. In an example, the mode control signal Ctrl _ mode may be generated in the semiconductor device, and in the normal mode, the mode control signal Ctrl _ mode may include information for disabling the Delay control circuit Delay Ctrl, and thus the Delay process may not be applied to the normal input. Further, in the embodiment, the Delay control circuit Delay Ctrl may include a transmission path (first path) to which a Delay is applied and a transmission path (second path) to which a Delay is not applied, and may transmit the test input via the first path or the normal input via the second path in response to the mode control signal Ctrl _ mode.

Fig. 5 and 6 are flowcharts of a method of testing a semiconductor device according to an example embodiment of the inventive concept. Referring to fig. 5, a wafer level test and/or a test after the wafer level test may be performed during the manufacturing process of the semiconductor apparatus, so that the semiconductor apparatus may enter a test mode based on a control from an external tester (operation S11). In addition, the semiconductor device may include a delay control circuit for performing a delay process on the test input, and a delay amount of the delay control circuit may be programmed in response to the delay control signal. For example, in the test mode, the semiconductor device may receive a delay control signal from an external tester and may set a delay amount of the delay control circuit in response to the delay control signal (operation S12). For example, when a plurality of semiconductor devices are mass-produced and the plurality of semiconductor devices are tested by the same tester (or mounted on the same test board), the delay amounts applied to the plurality of semiconductor devices may be different from each other.

After the delay amount is set, the semiconductor device may receive a test input from the external tester and perform a delay process on the received test input (operation S13). The delayed test input may be transmitted to a target circuit in the semiconductor apparatus (operation S14). For example, the target circuit may correspond to one or more different types of circuit blocks, and when the semiconductor device is a memory device and the test input has pattern information to be written to the memory cell array, the delayed test input may be provided to the memory cell array via the data input buffer.

Further, according to the above-described embodiments, different delay amounts can be set for a plurality of semiconductor devices to be tested by the same tester based on the delay control signal, and therefore even if test inputs from the tester are simultaneously supplied to the plurality of semiconductor devices, the plurality of semiconductor devices can perform signal processing for testing at different timings.

Fig. 6 illustrates an example of an operation of a test apparatus for a test operation according to an embodiment of the inventive concept. The test apparatus may include a test logic device for generating a test input and DUT mounting circuits on which a plurality of semiconductor devices are mounted as DUTs, respectively. In the operational example of FIG. 6, a first DUT and a second DUT are shown.

The test logic device may output a plurality of test inputs in parallel to test a plurality of DUTs (operation S21), and may simultaneously provide the plurality of test inputs to the DUT mounting circuits. For example, a first test input may be provided to a first DUT and a second test input may be provided to a second DUT, and a time at which the first test input is provided to the first DUT and a time at which the second test input is provided to the second DUT may be substantially the same.

The first DUT may internally perform delay processing on the first test input and then provide the first test input to a target circuit of the first DUT (operation S22). In addition, the second DUT may internally perform a delay process on the second test input, and may provide the second test input to the target circuit of the second DUT after a first delay after providing the first test input to the target circuit of the first DUT according to a result of the internally performing the delay process on the second test input (operation S23). That is, the difference between the amount of delay in the first DUT and the amount of delay in the second DUT may correspond to the first delay.

The first DUT may perform internal signal processing by using the first test input, and may provide a first test result from the first DUT to the test logic device (operation S24). Additionally, a second test result from the second DUT may be provided to the test logic device after a second delay after the first test result is provided to the test logic device (operation S25). That is, from the perspective of testing the logic device, while the first and second test inputs are provided to the first and second DUTs simultaneously, a difference between a time at which the test result is received from the first DUT and a time at which the test result is received from the second DUT, corresponding to the second delay, may be generated.

The test logic device may determine whether the DUT mounted on the DUT mounting circuit is defective by using a plurality of test results including the first test result and the second test result (operation S26).

Fig. 7A and 7B are views illustrating an example of a test operation for a semiconductor wafer according to an example embodiment of the inventive concepts. Referring to fig. 7A, a plurality of semiconductor dies manufactured by a semiconductor manufacturing process on a semiconductor wafer may be arranged in an array, and each of the plurality of semiconductor dies may constitute a DUT in a test operation at a wafer level. For example, each of the semiconductor dies may have contact pads (not shown) for electrically connecting the internal circuitry to an external device. Further, although not shown in fig. 7A, a delay control circuit for performing a delay process on a test input according to the above-described embodiments may be formed in each of the semiconductor dies.

Referring to fig. 7B, a test apparatus 300 according to an example embodiment of the inventive concepts may include a probe card 310 for performing a test at a wafer level, and pins 312, which may make electrical contact with contact pads of a semiconductor die, may be arranged at one side of the probe card 310. In addition, the test apparatus 300 according to example embodiments of the inventive concepts may include various components, and may further include a plurality of semiconductor dies formed in the semiconductor wafer 320 as test objects, for example, in the test apparatus 300. The semiconductor wafer 320 may be placed on a wafer prober and the wafer prober may adjust the position of the semiconductor wafer 320 such that the contact pads of the semiconductor wafer 320 electrically contact the pins 312 of the probe card 310.

The probe card 310 may have a flat structure including a first surface on which the above-described pins are arranged and a second surface on which logic circuits are formed. For example, the probe card 310 may be implemented with a printed circuit board and the test logic devices 311 may be implemented in or near the second surface.

According to example embodiments of the inventive concepts, the test logic device 311 of the probe card 310 may control a test operation on a plurality of semiconductor dies formed in the semiconductor wafer 320. For example, the test logic 311 of the probe card 310 may provide a delay control signal to the semiconductor die that is used to adjust the timing of sending test inputs provided to the semiconductor die to the target circuit. According to the embodiment, a plurality of semiconductor dies formed in the semiconductor wafer 320 may be classified into a plurality of groups, and different delay amounts may be set for the plurality of groups. Each of the semiconductor dies may include a plurality of channels, and different delay amounts may be set for the plurality of channels.

Fig. 8 and 9 are schematic diagrams respectively showing an example of group setting of a plurality of DUTs arranged on a test board and an example of delaying a test input. Referring to fig. 8, a plurality of semiconductor devices are respectively mounted as DUTs on a test board provided in a test apparatus 400A. The plurality of semiconductor devices are classified into first to B-th groups Group 1 to Group B, and each of the first to B-th groups Group 1 to Group B may include a plurality of semiconductor devices. In the example of fig. 8, the first Group 1 to the B-th Group B include the same number of semiconductor devices. However, embodiments of the inventive concept are not limited thereto. For example, the first Group 1 to the B-th Group B may include different numbers of semiconductor devices. In fig. 8, the DUT to be tested may be a semiconductor die or semiconductor package.

Fig. 9 shows timings of transmitting test inputs to target circuits among the plurality of DUTs mounted on the test board of fig. 8. For example, a tester (or test logic device) may provide a bitstream having one or more bits of information as a test input to a plurality of semiconductor devices, and the time at which the test input is provided to the plurality of semiconductor devices may be substantially the same. That is, the tester may provide test inputs to multiple semiconductor devices simultaneously in a parallel test environment.

According to an embodiment, the Delay control circuit of the semiconductor devices in the first Group 1 may Delay the test input according to the first Delay amount Delay 1, and the Delay control circuit of the semiconductor devices in the second Group 2 may Delay the test input according to the second Delay amount Delay 2. Similarly, the Delay control circuit of the semiconductor device in the Group B may Delay the test input according to the B-th Delay amount Delay B. The test input to which the delay is applied and provided to the target circuit may be referred to as a valid bit stream, which is effectively provided for testing.

Fig. 10 and 11 are block diagrams showing examples of setting the delay amount for the DUT according to various methods. Fig. 10 shows an example of setting different delay amounts for DUTs, and fig. 11 shows an example of setting different delay amounts for channels in one DUT.

Referring to the test apparatus 400B in fig. 10, a plurality of semiconductor devices are respectively mounted on the test board as DUTs. For example, although fig. 10 shows an example in which a plurality of semiconductor devices are arranged in a matrix form, a plurality of semiconductor devices may be arranged on a test board in various forms. As shown in fig. 10, a plurality of semiconductor devices may be arranged in I rows and J columns, and thus I × J semiconductor devices may be mounted on the test board, and different Delay amounts Delay 1 to Delay I × J may be set for the I × J semiconductor devices. Therefore, even if test inputs are supplied to the I x J semiconductor devices mounted on the test board at the same time point in the parallel test environment, the test inputs can be transmitted to the target circuits among the I x J semiconductor devices at substantially different time points, and thus the tests for the I x J semiconductor devices can be performed at different time points.

Referring to the test apparatus 400C of fig. 11, a plurality of semiconductor devices 410C are respectively mounted on a test board as DUTs, and each of the semiconductor devices 410C may include a plurality of channels CH1 to CH a. According to the above-described embodiments, the test input supplied to any one of the semiconductor devices 410C may be supplied to the plurality of channels CH1 to CH a in the semiconductor device 410C, and the delay amount of the test input may be set differently for the plurality of channels CH1 to CH a. Fig. 11 shows an example in which the first Delay amount Delay 1 is set for the first channel (i.e., the channel CH 1), the second Delay amount Delay 2 is set for the second channel (i.e., the channel CH 2), and the a-th Delay amount Delay a is set for the a-th channel (i.e., the channel CH a). Therefore, in any one of the semiconductor devices 410C, even if the test inputs are supplied to the plurality of channels CH1 to CH a at the same point in time, the test inputs can be transmitted to the target circuits of the plurality of channels CH1 to CH a at different points in time.

Fig. 12 is a block diagram illustrating an example of implementing a semiconductor device according to an example embodiment of the inventive concepts as a High Bandwidth Memory (HBM) 500. Referring to fig. 12, HBM 500 may include a plurality of semiconductor dies, e.g., a logic die (or buffer die) 510 and one or more core dies 520 including a memory cell array 521. The HBM 500 may have an increased bandwidth by including a plurality of channels CH1 to CH 8 with independent interfaces, and fig. 12 shows an example in which the HBM 500 includes four core dies 520 and each of the four core dies 520 includes two channels. However, the number of core dies 520 and the number of channels CH1 to CH 8 may be changed differently.

Logic die 510 may include a Through Silicon Via (TSV) region 511, a Physical (PHY) region 512, and a direct access region 513. The logic die 510 may also include control logic (not shown) for controlling overall operations in the HBM 500, and may perform, for example, internal control operations in response to commands from an external controller. Additionally, a delay control circuit 514 for delaying the test input may also be included in the logic die 510 according to the embodiments described above.

The TSV region 511 corresponds to a region where TSVs are formed for communication with the core die 520. The PHY region 512 may include a plurality of input and output circuits for communicating with an external controller, and the direct access region 513 may communicate directly with an external tester via conductive devices located on an external surface of the HBM 500 in a test mode for the HBM 500. Various signals provided from an external tester may be provided to the core die 520 via the direct access region 513 and the TSV region 511. Test inputs from an external tester may be provided to the delay control circuit 514 via the direct access region 513 and delayed test inputs may be provided to the core die 520 via the TSV region 511.

According to example embodiments of the inventive concept, the HBM 500 may be mounted on a test board and receive a test input in a test mode, for example, a plurality of HBMs 500 may be mounted on the test board. The delay control circuit 514 may receive a test input commonly provided for the plurality of channels CH1 to CH 8, delay the test input, and then provide the delayed test input to the plurality of channels CH1 to CH 8. In another embodiment, the delay control circuit 514 may receive test inputs provided for the plurality of channels CH1 to CH 8, respectively, and may output the delayed test inputs by a delay operation on the test inputs.

According to yet another embodiment, the test inputs may be provided to the target circuit included in the plurality of channels CH1 to CH 8 at different times. The plurality of channels CH1 to CH 8 may be classified into a plurality of channel groups, and the test input may be provided to the target circuit at different timings for the channel groups. For example, for a first Core Die1 and a second Core Die2, test inputs may be provided to target circuits of a first channel and a third channel (i.e., channels CH1 and CH3) of the first Core Die1, and then to target circuits of a second channel and a fourth channel (i.e., channels CH2 and CH4) of the second Core Die 2. As various example embodiments, test inputs may be provided to the target circuits of channels CH1 through CH 8 regardless of the stacking order of the plurality of core dies stacked on the logic die 510.

Fig. 13 and 14 are circuit diagrams illustrating examples of a delay control circuit according to example embodiments of the inventive concepts. Referring to fig. 13, a semiconductor device 600A may include a delay control circuit and a target circuit 630A, and the delay control circuit may include a DFT buffer 610A and a timing control circuit 620A. In addition, the timing control circuit 620A may include a plurality of transmission paths for transmitting the test input to the target circuit 630A, and different delay amounts may be applied to the plurality of transmission paths. In addition, a plurality of switches SW1 to SWC may also be included in the timing control circuit 620A to select any one of a plurality of transmission paths.

According to the above-described embodiment, the plurality of switches SW1 to SWC may be controlled in response to the delay control signal Ctrl _ delay. For example, the semiconductor apparatus 600A may set the delay amount of the test input by selectively turning on any one of the plurality of switches SW1 through SWC in the test mode. For example, in the test mode of the semiconductor apparatus 600A, any one of the plurality of transmission paths may be selected according to the delay control signal Ctrl _ delay from the test logic device, so that the delay amount of the test input may be adjusted.

Referring to fig. 14, the semiconductor device 600B may include a delay control circuit and target circuits 630B _1 to 630B _ a, and the delay control circuit may include a DFT buffer 610B and a timing control circuit 620B. Fig. 14 shows an example in which one semiconductor device 600B includes a plurality of channels CH1 to CH a. As in the embodiment of fig. 13, the timing control circuit 620B includes a plurality of transmission paths, and different delay amounts may be applied to the plurality of transmission paths. The timing control circuit 620B may further include a plurality of switch blocks SW BLK 1 to SW BLK a corresponding to the plurality of channels CH1 to CH a, respectively, and the plurality of switch blocks SW BLK 1 to SW BLK a may be controlled by the delay control signal Ctrl _ delay.

According to example embodiments, the switching states of the switching blocks SW BLK 1 to SW BLK a in the test mode of the semiconductor apparatus 600B may be differently controlled. Therefore, paths for transmitting the test input to the target circuits of the plurality of channels CH1 to CH a may be different from each other. Therefore, the timing of providing the test input to the target circuit of the plurality of channels CH1 to CH a of the semiconductor apparatus 600B may be adjusted differently.

Fig. 15 is a block diagram illustrating an example of implementing a semiconductor device according to an example embodiment of the inventive concepts as a memory device 700. Referring to fig. 15, the memory device 700 may include a memory cell array 711, a row decoder 712, and a column decoder 713 to perform memory operations of storing data and reading data. The memory device 700 may further include a control logic device 720 for controlling the overall operation in the memory device 700 and a data buffer 730 for temporarily storing input/output data. In addition, memory device 700 may also include various other components related to memory operations, such as voltage generators, write drivers, and sense amplifiers.

The control logic device 720 may control memory operations according to various signals from a memory controller (not shown). For example, control logic device 720 may receive an address ADD from the memory controller, provide row decoder 712 with a row address for selecting a word line of memory cell array 711, and provide column decoder 713 with a column address for selecting a bit line of memory cell array 711. In addition, the control logic device 720 may include a command decoder 721, the command decoder 721 decoding commands CMD from the memory controller to control operations in the memory device 700.

According to example embodiments of the inventive concepts, information to be corresponding to a command CMD and an address ADD may be provided from a test logic device to the memory device 700 as a test input (e.g., a first test input) in a test environment for the memory device 700. In addition, information corresponding to the DATA DATA may be provided to the memory device 700 as a test input (e.g., a second test input). According to the above-described embodiments, in a test environment, each of the first test input and the second test input may be provided to a target circuit in the memory device 700 via the DFT buffer and the timing control circuit. For example, the first test input may be provided to the control logic device 720 after being delayed by a delay amount by the DFT buffer 741 and the timing control circuit 742, and the second test input may be provided to the data buffer 730 after being delayed by a delay amount by the DFT buffer 751 and the timing control circuit 752.

In the test mode, the memory device 700 may perform signal processing using the first test input and the second test input and generate a test output and provide the test output to the external test logic device. In addition, the memory device 700 may receive a command/address CMD/ADD and DATA for memory operation in the normal mode via a Command Address (CA) buffer 743 and a DATA buffer 753, respectively, and may provide the received signals to circuit blocks in the memory device 700 without delay processing. Fig. 15 shows a configuration in which pads and buffers for receiving various types of information in the test mode are provided separately from pads and buffers for receiving various types of information in the normal mode. However, as in the embodiments described above, the memory device 700 may have a configuration in which pads and buffers are shared in the test mode and the normal mode.

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.