阅读说明：本技术 半导体存储器设备 (Semiconductor memory device ) 是由 金东槿 于 2019-08-15 设计创作，主要内容包括：半导体存储器设备。一种半导体存储器设备可以包括存储器存储体、全局缓冲器阵列以及输入和输出电路。所述存储器存储体包括本地数据电路,并且所述全局缓冲器阵列包括全局数据电路。所述本地数据电路可操作地联接到所述全局数据电路。所述全局缓冲器阵列可操作地联接到所述输入和输出电路。所述存储器存储体设置在核心区域中,所述全局缓冲器阵列以及所述输入和输出电路可以设置在与核心区域分开的外围区域中。(A semiconductor memory device. A semiconductor memory device may include a memory bank, a global buffer array, and input and output circuits. The memory bank includes local data circuitry and the global buffer array includes global data circuitry. The local data circuit is operably coupled to the global data circuit. The global buffer array is operably coupled to the input and output circuits. The memory banks are disposed in a core region, and the global buffer array and the input and output circuits may be disposed in a peripheral region separate from the core region.)

1. A semiconductor memory device, the semiconductor memory device comprising:

local data circuitry disposed in a memory bank, coupled between memory cells of the memory bank and bank data lines, and configured to perform a valid write operation and a valid read operation;

a global data circuit disposed outside the memory bank and configured to perform a buffered write operation and a buffered read operation between the bank data line and a global data line; and

an input and output circuit coupled to the global data line and configured to receive data from an external device or output data to the external device.

2. The semiconductor memory device of claim 1, wherein the bank data lines include a bank write line and a bank read line, and

when the valid write operation is performed after the buffered write operation is performed, the local data circuit writes data located on the bank write line to the memory cell.

3. The semiconductor memory device of claim 1, wherein the bank data lines include a bank write line and a bank read line, and

when the valid write operation is performed after the valid read operation is performed, the local data circuitry writes data located on the bank read line to the memory cell.

4. The semiconductor memory device according to claim 3, wherein the local data circuit does not perform a write operation on the memory cell when data on the bank write line and data on the bank read line are equal to each other.

5. The semiconductor memory device of claim 1, wherein the bank data lines include a bank write line and a bank read line, and

when the buffered read operation is performed after the active read operation is performed, the global data circuit outputs data located on the bank read line to the global data line.

6. The semiconductor memory device of claim 1, wherein the bank data lines include a bank write line and a bank read line, and

when the buffered read operation is performed after the buffered write operation is performed, the global data circuit outputs data located on the bank write line to the global data line.

7. The semiconductor memory device of claim 1, wherein the bank data lines include a bank write line and a bank read line, and

the local data circuit includes:

a write driver configured to write select data to the memory cells;

a sense amplifier configured to read data stored in the memory cell and output the read data to the bank read line; and

a write data selector configured to output one of data located on the bank write line and data located on the bank read line as the write selection data based on a write mode signal.

8. The semiconductor memory device of claim 7, wherein the local data circuit further comprises: a comparator configured to generate a write driver off signal by comparing data located on the bank write line and data located on the bank read line based on an address mark,

wherein when the write driver off signal is enabled, the write driver is disabled and does not perform a write operation.

9. The semiconductor memory device of claim 7, wherein the local data circuit further comprises: a write mode signal generator configured to generate the write mode signal based on a buffered write signal and a valid read signal.

10. The semiconductor memory device of claim 7, wherein the local data circuit further comprises:

a first latch configured to latch data of the bank write line; and

a second latch configured to latch data of the bank read line.

11. The semiconductor memory device of claim 1, wherein the bank data lines include a bank write line and a bank read line, and

the global data circuit includes:

a write latch configured to output data transferred through the global data line to the bank write line based on a buffered write signal;

a read latch configured to output read select data to the global data line based on a buffered read signal; and

a read data selector configured to output one of data located on the bank write line and data located on the bank read line as the read selection data based on a read mode signal.

12. The semiconductor memory device of claim 11, wherein the global data circuit further comprises: a read mode signal generator configured to generate the read mode signal based on a buffered write signal and a valid read signal.

13. A semiconductor memory device, the semiconductor memory device comprising:

a memory bank disposed in a core region and including local data circuitry;

a global buffer array disposed in a peripheral region separate from the core region and including a global data circuit operably coupled to the local data circuit; and

input and output circuitry disposed in the peripheral region and coupled to the global buffer array,

wherein the local data circuits perform valid write operations and valid read operations between the memory banks and the global buffer array, and the global buffer array performs buffered write operations and buffered read operations between the local data circuits and the input and output circuits.

14. The semiconductor memory device of claim 13, wherein the global buffer array is disposed closer to the core region than the input and output circuits.

15. The semiconductor memory device of claim 13, wherein the local data circuit is coupled to the global data circuit by a bank write line and a bank read line, and the global data circuit is coupled to the input and output circuits by a global data line.

16. The semiconductor memory device according to claim 15, wherein when the valid write operation is performed, the local data circuit writes data to a selected memory cell of the memory bank based on one of data located on the bank write line and data located on the bank read line.

17. The semiconductor memory device according to claim 16, wherein when the buffered write operation is performed before the valid write operation, the local data circuit writes data to the selected memory cell based on data located on the bank write line.

18. The semiconductor memory device according to claim 16, wherein when the valid read operation is performed before the valid write operation, the local data circuit writes data to the selected memory cell based on data located on the bank read line.

19. The semiconductor memory device according to claim 15, wherein when the buffered read operation is performed, the global data circuit outputs data to the global data line based on one of data located on the bank write line and data located on the bank read line.

20. The semiconductor memory device according to claim 19, wherein when the buffered write operation is performed before the buffered read operation, the global data circuit outputs data to the global data line based on data located on the bank write line.

21. The semiconductor memory device according to claim 20, wherein when the valid read operation is performed before the buffered read operation, the global data circuit outputs data to the global data lines based on data located on the bank read lines.

22. The semiconductor memory device according to claim 15, wherein when the valid write operation is performed on the selected memory cell of the memory bank after the valid read operation is performed on the selected memory cell, the local data circuit compares data located on the bank write line and data located on the bank read line.

23. The semiconductor memory device according to claim 22, wherein the local data circuit writes data to the selected memory cell based on the data on the bank write line when the data on the bank write line and the data on the bank read line are different from each other, and does not perform a write operation on the selected memory cell when the data on the bank write line and the data on the bank read line are equal to each other.

24. The semiconductor memory device according to claim 13, wherein the memory banks are provided as a plurality of memory banks arranged in the core area, and each memory bank includes a local data circuit included in one of the plurality of memory banks in a one-to-one manner, and

wherein the global buffer array further comprises a plurality of global data circuits operably coupled to the local data circuits in a one-to-one manner, each of the local data circuits included in one of the plurality of memory banks in a one-to-one manner.

Technical Field

Various embodiments relate generally to integrated circuit technology and, more particularly, to a semiconductor memory device and a system including the same.

Background

The electronic device may include a number of electronic components. Among the electronic components, a computer system may include a large number of electronic components composed of semiconductors. The computer system may include a memory device. A Dynamic Random Access Memory (DRAM) is capable of storing and outputting data at a high and constant speed and performing random access. Therefore, DRAMs are widely used as general-purpose memory devices. However, since the DRAM includes memory cells each composed of a capacitor, the DRAM has a volatile characteristic of losing data stored therein when power is cut off. To eliminate this drawback of DRAMs, flash memory devices have been developed. Since the flash memory device includes memory cells each composed of a floating gate, the flash memory device may have a nonvolatile characteristic of retaining data stored therein even if power is cut off. However, the flash memory device stores and outputs data at a speed lower than that of the DRAM, and it is difficult to perform random access.

Recently, next-generation memory devices having high operation speed and nonvolatile characteristics have been developed. Examples of next generation memory devices may include phase change ram (pram), magnetic ram (mram), resistive ram (reram), and ferroelectric ram (fram). The next-generation memory device can operate at high speed while having nonvolatile characteristics. In particular, a PRAM including a phase change memory cell formed of chalcogenide may store data by changing a resistance value of the memory cell.

Disclosure of Invention

In one embodiment, a semiconductor memory device may include a local data circuit, a global data circuit, and input and output circuits. The local data circuit may be disposed in a memory bank, coupled between memory cells of the memory bank and a bank data line, and configured to perform a valid write operation and a valid read operation. The global data circuit may be disposed outside of the memory bank and configured to perform buffered write operations and buffered read operations between the bank data lines and the global data lines. The input and output circuits are coupled to the global data lines and configured to receive data from or output data to an external device.

In one embodiment, a semiconductor memory device may include a memory bank, a global buffer array, and input and output circuits. The memory banks may be disposed in the core area and include local data circuits. The global buffer array may be disposed in a peripheral region separate from the core region and include global data circuitry operatively coupled to local data circuitry. Input and output circuits may be disposed in the peripheral region and operably coupled to the global buffer array. The local data circuitry may perform valid write operations and valid read operations between the memory banks and the global buffer array. The global buffer array may perform buffered write operations and buffered read operations between the local data circuits and the input and output circuits.

Drawings

Fig. 1 illustrates a configuration of a semiconductor system and a semiconductor memory device according to an embodiment.

FIG. 2 illustrates a configuration of a local data circuit, according to one embodiment.

Fig. 3 illustrates a configuration of the write data selector illustrated in fig. 2.

Fig. 4 illustrates a configuration of the write mode signal generator illustrated in fig. 2.

FIG. 5 illustrates a configuration of a global data circuit, according to one embodiment.

Fig. 6 illustrates a configuration of the read data selector illustrated in fig. 5.

Fig. 7 illustrates a configuration of the read mode signal generator illustrated in fig. 5.

Fig. 8 illustrates a memory card including a semiconductor memory device according to an embodiment.

Fig. 9 illustrates a block diagram to aid in explaining an electronic device including a semiconductor memory device according to an embodiment.

Fig. 10 illustrates a data storage device including a semiconductor memory device according to an embodiment.

Fig. 11 illustrates an electronic system including a semiconductor memory device according to an embodiment.

Detailed Description

Hereinafter, a semiconductor memory device and a system including the same according to the present disclosure will be described below by way of examples of embodiments with reference to the accompanying drawings.

Fig. 1 illustrates a configuration of a semiconductor system 1 and a semiconductor memory device 100 according to an embodiment. The semiconductor system 1 may include an external device 10 and a semiconductor memory apparatus 100. The external device 10 and the semiconductor memory apparatus 100 can perform data communication with each other. The external device 10 may provide various control signals required for the operation of the semiconductor memory apparatus 100.

The external device 10 may be a host device that controls the semiconductor memory apparatus 100 to perform various operations. For example, the external device 10 may include a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a multimedia processor (MMP), a digital signal processor, an Application Processor (AP), a memory controller, or the like.

The semiconductor memory device 100 may include a nonvolatile memory device. For example, a semiconductor memory device may include any non-volatile memory device having a lower write/read speed than dynamic ram (dram). For example, the semiconductor memory device 100 may include a flash memory, a phase change ram (pram), a magnetic ram (mram), a resistance ram (rram), a ferroelectric ram (fram), and the like. The semiconductor memory device 100 may be a PRAM including a memory cell formed of a phase change material.

The semiconductor memory apparatus 100 may be coupled to an external device 10 through a system bus 11. The system bus 11 may be a signal transmission path, link, or channel for transmitting signals. The system bus 11 may include a command bus, an address bus, a clock bus, a data bus, and the like. The command, address and clock buses may be unidirectional buses, while the data bus may be a bidirectional bus. The external device 10 may supply a command signal CMD to the semiconductor memory apparatus 100 through a command bus, an address signal ADD to the semiconductor memory apparatus 100 through an address bus, and a clock signal CLK to the semiconductor memory apparatus 100 through a clock bus. The external device 10 may transfer data DQ to the semiconductor memory apparatus 100 through a data bus, and receive data DQ transferred from the semiconductor memory apparatus 100 through the data bus.

Referring to fig. 1, a semiconductor memory device 100 may include a core region 101 and a peripheral region 102. The core area 101 may include a memory cell array for storing data. The core area 101 may include a data circuit for storing data in the memory cell array or outputting data stored in the memory cell array. In addition, the core area 101 may include data lines for transferring data between the core area 101 and the peripheral area 102. In fig. 1, a plurality of memory banks (memory banks) may be arranged in the core area 101. For example, the semiconductor memory device 100 may include eight memory banks arranged in the core area 101. However, the number of memory banks included in the semiconductor memory device 100 may not be limited thereto. That is, the number of memory banks may be equal to or less than 8 or greater than 8.

The semiconductor memory apparatus 100 may include a first left memory bank LBK1, a first right memory bank RBK1, a second left memory bank LBK2, a second right memory bank RBK2, a third left memory bank LBK3, a third right memory bank RBK3, a fourth left memory bank LBK4, and a fourth right memory bank RBK 4. Multiple memory banks may operate as one bank or divided into different banks that operate separately. For example, a memory bank may operate as eight independent memory banks. Further, the left and right memory banks may operate as one memory bank. The first through fourth left memory banks LBK1 through LBK4 and the first through fourth right memory banks RBK1 through RBK4 may include local data circuits 111, 112, 113, 114, 115, 116, 117, and 118, respectively. The local data circuits 111 to 118 may be coupled to the peripheral region 102 by bank data lines, respectively. In an embodiment, local data circuits 111-118 are coupled to peripheral region 102 by bank data lines in a one-to-one manner, such that a single local data circuit is coupled to peripheral region 102 by a single bank data line. The bank data lines may include bank write lines and bank read lines.

The peripheral region 102 may be separate from the core region 101 and located outside the core region 101. Peripheral region 102 may include a global buffer array 120 and input and output circuitry 130. Although not illustrated, the peripheral region 102 may include various internal circuits capable of controlling the semiconductor memory device 100 to perform various operations in addition to the global buffer array 120 and the input and output circuits 130. For example, global buffer array 120 may be disposed adjacent to core region 101. Global buffer array 120 may be disposed closer to core region 101 than input and output circuitry 130. In an embodiment, global buffer array 120 may be disposed between core region 101 and input and output circuitry 130. Global buffer array 120 may include a plurality of global data circuits 121, 122, 123, 124, 125, 126, 127, and 128. Global data circuits 121 to 128 may be assigned to respective memory banks and correspond to the number of memory banks. In an embodiment, global data circuits 121 through 128 may be assigned to memory banks in a one-to-one manner, thereby assigning a single global data circuit to a single memory bank. The plurality of global data circuits 121 to 128 may be operatively coupled to the local data circuits 111 to 118 included in the plurality of memory banks through bank data lines, respectively. In an embodiment, the plurality of global data circuits 121 to 128 are operatively coupled to the local data circuits 111 to 118 included in the plurality of memory banks in a one-to-one manner through the bank data lines, such that a single global data circuit is operatively coupled to a single local data circuit included in the plurality of memory banks through a single bank data line. The peripheral region 102 may further include global data lines GIO for transferring data between the global buffer array 120 and the input and output circuits 130.

The coupling relationship between the components of the semiconductor memory device will be described below. Local data circuit 111 of first left memory bank LBK1 may be coupled to global data circuit 121. Local data circuit 111 may be coupled to global data circuit 121 by a bank write line WBIO1 and a bank read line rboo 1. The local data circuit 111 may receive data output from the global data circuit 121 via a bank write line WBIO1 and output data to the global data circuit 121 via a bank read line rboo 1. The global data circuit 121 may output data to the local data circuit 111 through a bank write line WBIO1, and receive data output from the local data circuit 111 through a bank read line rboo 1.

Local data circuit 112 of second left memory bank LBK2 may be coupled to global data circuit 122. Local data circuits 112 may be coupled to global data circuit 122 by bank write line WBIO2 and bank read line rboo 2. The local data circuit 112 may receive data output from the global data circuit 122 via a bank write line WBIO2 and output data to the global data circuit 122 via a bank read line rboo 2. The global data circuit 122 may output data to the local data circuits 112 via a bank write line WBIO2 and receive data output from the local data circuits 112 via a bank read line rboo 2.

Local data circuit 113 of third left memory bank LBK3 may be coupled to global data circuit 123. Local data circuit 113 may be coupled to global data circuit 123 by a bank write line WBIO3 and a bank read line rboo 3. The local data circuit 113 may receive data output from the global data circuit 123 via a bank write line WBIO3 and output data to the global data circuit 123 via a bank read line rboo 3. The global data circuit 123 may output data to the local data circuit 113 via a bank write line WBIO3 and receive data output from the local data circuit 113 via a bank read line rboo 3.

Local data circuit 114 of fourth left memory bank LBK4 may be coupled to global data circuit 124. Local data circuitry 114 may be coupled to global data circuitry 124 by a bank write line WBIO4 and a bank read line rboo 4. The local data circuit 114 may receive data output from the global data circuit 124 via a bank write line WBIO4 and output data to the global data circuit 124 via a bank read line rboo 4. The global data circuit 124 may output data to the local data circuit 114 via a bank write line WBIO4 and receive data output from the local data circuit 114 via a bank read line rboo 4.

Local data circuit 115 of first right memory bank RBK1 may be coupled to global data circuit 125. Local data circuit 115 may be coupled to global data circuit 125 by a bank write line WBIO5 and a bank read line rboo 5. The local data circuit 115 may receive data output from the global data circuit 125 via a bank write line WBIO5 and output data to the global data circuit 125 via a bank read line rboo 5. The global data circuit 125 may output data to the local data circuit 115 via a bank write line WBIO5 and receive data output from the local data circuit 115 via a bank read line rboo 5.

Local data circuit 116 of second right memory bank RBK2 may be coupled to global data circuit 126. Local data circuits 116 may be coupled to global data circuits 126 by bank write lines WBIO6 and bank read lines rboo 6. The local data circuits 116 may receive data output from the global data circuit 126 via a bank write line WBIO6 and output data to the global data circuit 126 via a bank read line rboo 6. The global data circuit 126 may output data to the local data circuits 116 via a bank write line WBIO6 and receive data output from the local data circuits 116 via a bank read line rboo 6.

Local data circuit 117 of third right memory bank RBK3 may be coupled to global data circuit 127. Local data circuit 117 may be coupled to global data circuit 127 by a bank write line WBIO7 and a bank read line rboo 7. The local data circuit 117 may receive data output from the global data circuit 127 through a bank write line WBIO7 and output data to the global data circuit 127 through a bank read line rboo 7. The global data circuit 127 may output data to the local data circuit 117 through a bank write line WBIO7, and receive data output from the local data circuit 117 through a bank read line rboo 7.

The local data circuit 118 of the fourth right memory bank RBK4 may be coupled to the global data circuit 128. Local data circuits 118 may be coupled to global data circuits 128 by bank write lines WBIO8 and bank read lines rboo 8. The local data circuit 118 may receive data output from the global data circuit 128 via a bank write line WBIO8 and output data to the global data circuit 128 via a bank read line rboo 8. The global data circuit 128 may output data to the local data circuits 118 via a bank write line WBIO8 and receive data output from the local data circuits 118 via a bank read line rboo 8.

The input and output circuit 130 can communicate with an external device 10 through the system bus 11 and function as an interface circuit of the semiconductor memory apparatus 100. Input and output circuitry 130 may be operably coupled to global buffer array 120. The input and output circuit 130 may output data transferred from the external device 10 through the system bus 11 to the global data line GIO and output data transferred through the global data line GIO to the external device 10 through the system bus 11. The data transferred through the system bus 11 may be serial data, and the data transferred through the global data line GIO may be parallel data. The input and output circuit 130 may include a deserializer for converting serial data into parallel data and a serializer for converting parallel data into serial data. Through the global data line GIO, the input and output circuit 130 may transmit data to the global buffer array 120 or receive data output from the global buffer array 120.

The semiconductor memory device 100 may perform an effective write operation, an effective read operation, a buffered write operation, and a buffered read operation. The valid write operation, the valid read operation, the buffered write operation, and the buffered read operation may be performed based on the command signal CMD supplied from the external device 10. The valid write operation and the valid read operation may correspond to data communication performed between the core area 101 and the peripheral area 102. The buffered write operation and the buffered read operation may correspond to data communication performed between the peripheral region 102 and the external device 10.

A valid write operation may indicate a write operation performed between memory banks LBK 1-LBK 4 and RBK 1-RBK 4 and global buffer array 120. The local data circuits 111 to 118 may perform effective write operations between memory cells of the memory banks LBK1 to LBK4 and RBK1 to RBK4 and the bank data lines, respectively. In an embodiment, the local data circuits 111-118 may perform valid write operations between memory cells and bank data lines of the memory banks LBK 1-LBK 4 and RBK 1-RBK 4 in a one-to-one manner, thereby causing a single local data circuit to perform valid write operations between memory cells and a single bank data line of a single memory bank. The semiconductor memory device 100 may receive an address signal ADD for selecting a memory bank and a memory cell to perform a valid write operation using a command signal CMD for performing a valid write operation. Based on the address signal ADD, a particular memory cell of a particular memory bank on which an active write operation is to be performed may be selected. For example, a valid write operation for the first left memory bank may indicate an operation in which local data circuit 111 writes data transferred from global data circuit 121 to bank write line WBIO1 to a selected memory cell of first left memory bank LBK 1.

A valid read operation may indicate a read operation performed between memory banks LBK 1-LBK 4 and RBK 1-RBK 4 and global buffer array 120. The local data circuits 111 to 118 may perform effective read operations between memory cells of the memory banks LBK1 to LBK4 and RBK1 to RBK4 and bank data lines, respectively. In an embodiment, the local data circuits 111 to 118 may perform an effective read operation between memory cells and bank data lines of the memory banks LBK1 to LBK4 and RBK1 to RBK4 in a one-to-one manner, thereby causing a single local data circuit to perform an effective read operation between memory cells and a single bank data line of a single memory bank. The semiconductor memory device 100 may receive an address signal ADD for selecting a memory bank and a memory cell to perform an effective read operation using a command signal CMD for performing an effective read operation. Based on the address signal ADD, a particular memory cell of a particular memory bank on which an effective read operation is to be performed may be selected. For example, a valid read operation of first left memory bank LBK1 may indicate an operation in which local data circuit 111 reads data stored in selected memory cells of first left memory bank LBK1 and transfers the read data to global data circuit 122 through bank read line RBIO 1.

The buffered write operation may be a write operation performed between global buffer array 120 and input and output circuitry 130. The global data circuits 121 to 128 of the global buffer array 120 may perform buffered write operations between the respective bank data lines and the global data line GIO. The semiconductor memory device 100 may receive an address signal ADD for selecting a memory bank on which a buffered write operation is to be performed, using a command signal CMD for performing the buffered write operation. Among the plurality of global data circuits 121 to 128 of the global buffer array 120, a specific global data circuit coupled to a memory bank selected based on the address signal ADD may perform a buffered write operation. For example, a buffered write operation for first left memory bank LBK1 may indicate an operation in which global data circuit 121 transfers data transferred from input and output circuit 130 through global data line GIO to bank write line WBIO 1. The global data circuit 121 may latch and store data transferred through the global data line GIO.

The buffered read operation may be a read operation performed between global buffer array 120 and input and output circuitry 130. The global data circuits 121 to 128 of the global buffer array 120 may perform a buffered read operation between each of the bank data lines and the global data line GIO. The semiconductor memory device 100 may receive an address signal ADD for selecting a memory bank on which a buffered read operation is to be performed, using a command signal CMD for performing the buffered read operation. Among the plurality of global data circuits 121 to 128 of the global buffer array 120, a specific global data circuit coupled to a memory bank selected based on the address signal ADD may perform a buffered read operation. For example, a buffered read operation for the first left memory bank LBK1 may indicate an operation in which the global data circuit 121 transfers data transferred from the local data circuit 111 via the bank read line RBIO1 to the input and output circuit 130 through the global data line GIO. Global data circuit 121 may latch and store data transferred through bank read line rboo 1.

The semiconductor memory device 100 may perform a valid write operation, a valid read operation, a buffered write operation, and a buffered read operation separately. When the valid write operation and the valid read operation are performed separately from the buffered write operation and the buffered read operation, the operation speed and efficiency of the semiconductor memory device can be improved. When the nonvolatile memory device including the PRAM writes data to the memory cells or reads data stored in the memory cells, the nonvolatile memory device including the PRAM may take a longer time than the nonvolatile memory device including the DRAM. Accordingly, the semiconductor memory apparatus 100 can perform the buffered write operation and the buffered read operation, so that the semiconductor memory apparatus 100 and the external device 10 can perform data communication at high speed. Further, the semiconductor memory device 100 may perform a write operation and a read operation interleaved (interleaved) with a plurality of memory banks by performing a valid write operation and a valid read operation separately from a buffered write operation and a buffered read operation. Further, by performing the effective write operation and the effective read operation in parallel with the buffered write operation and the buffered read operation, the semiconductor memory device 100 can reduce the time required to write data to the memory cells or read data stored in the memory cells and improve the efficiency of the write operation and the read operation.

During each valid write operation for memory banks LBK 1-LBK 4 and RBK 1-RBK 4, local data circuits 111-118 may write data to memory cells of the plurality of memory banks LBK 1-LBK 4 and RBK 1-RBK 4 based on data on bank write lines WBIO 1-WBIO 8 and bank read lines rboo 1-RBIO 8. During respective valid read operations for memory banks LBK 1-LBK 4 and RBK 1-RBK 4, local data circuits 111-118 may read data stored in memory cells of memory banks LBK 1-LBK 4 and RBK 1-RBK 4 and output the read data to bank read lines rboi 1-rboi 8.

During each buffered write operation for memory banks LBK 1-LBK 4 and RBK 1-RBK 4, global data circuits 121-128 may output data transferred through global data line GIO to local data circuits 111-118 through bank write lines WBIO 1-WBIO 8. During the respective buffered read operations for memory banks LBK 1-LBK 4 and RBK 1-RBK 4, global data circuits 121-128 may output data to global data line GIO based on data on bank write lines WBIO 1-WBIO 8 and bank read lines rboo 1-rboo 8.

For the description of the operation of the semiconductor memory device 100, the operation of the local data circuit 111 of the first left memory bank LBK1 and the global data circuit 121 coupled to the local data circuit 111 will be representatively described. The semiconductor memory apparatus 100 may perform the valid write operation, the valid read operation, the buffered write operation, and the buffered read operation of the first left memory bank LBK1 in various orders. When the semiconductor memory apparatus 100 performs a valid write operation after performing a buffered write operation on the first left memory bank LBK1, a write operation of the local data circuit 111 may be performed after performing a write operation of the global data circuit 121. During a buffered write operation, the global data circuit 121 may receive data transferred from the external device 10 via the input and output circuit 130 through the global data line GIO and output the data received through the global data line GIO to the bank write line WBIO 1. During a valid write operation, local data circuit 111 may write data to the memory cells of first left memory bank LBK1 based on data transferred from global data circuit 121 over bank write line WBIO 1. When performing a buffered write operation prior to a valid write operation, local data circuit 111 may write data to the memory cell based on the data on bank write line WBIO 1.

When the semiconductor memory apparatus 100 performs a valid write operation after performing a valid read operation on the first left memory bank LBK1, the local data circuit 111 may read data stored in the selected memory cells of the first left memory bank LBK1 and output the read data to the bank read line RBIO1 during the valid read operation. During a valid write operation, local data circuitry 111 may write data on bank read line RBIO1 to the selected memory cell or another memory cell during a valid read operation, instead of data on bank write line WBIO 1. In order to perform the valid write operation, the memory cell selected during the valid read operation based on the address signal ADD received from the external device 10 may be newly selected, or another memory cell may be selected. When performing an active read operation prior to an active write operation, local data circuitry 111 may write data to the memory cells based on the data on bank read line RBIO 1.

When the semiconductor memory apparatus 100 performs the buffered read operation after performing the valid read operation on the first left memory bank LBK1, the read operation of the global data circuit 121 may be performed after performing the read operation of the local data circuit 111. During an active read operation, local data circuitry 111 may read data stored in memory cells of first left memory bank LBK1 and output the read data to bank read line RBIO 1. During a buffered read operation, global data circuit 121 may output data to global data line GIO based on data received through bank read line RBIO 1. The input and output circuit 130 may output data transferred through the global data line GIO to the external device 10 through the system bus 11. When performing a valid read operation prior to a buffered read operation, global data circuit 121 may output data to global data line GIO based on the data on bank read line RBIO 1.

When the semiconductor memory apparatus 100 performs the buffered read operation after performing the buffered write operation on the first left memory bank LBK1, the read operation of the global data circuit 121 may be performed after performing the write operation of the global data circuit 121. During a buffered write operation, the global data circuit 121 may output data transferred from the input and output circuit 130 through the global data line GIO to the bank write line WBIO 1. During a buffered read operation, the global data circuit 121 may output data on the bank write line WBIO1, instead of data on the bank read line RBIO1, to the input and output circuit 130 through the global data line GIO, and the input and output circuit 130 may output the data transferred through the global data line GIO to the external device 10 through the system bus 11. When a buffered write operation is performed prior to a buffered read operation, the global data circuit 121 may output data to the global data line GIO based on the data on the bank write line WBIO 1.

When the semiconductor memory device 100 performs an effective read operation on a selected memory cell of the first left memory bank LBK1, the local data circuit 111 may output data stored in the selected memory cell to the bank read line RBIO 1. Then, when performing a valid write operation to a selected memory cell of first left memory bank LBK1, local data circuit 111 may compare data on bank read line RBIO1 with data on bank write line WBIO 1. The data on the bank write line WBIO1 may indicate the data output from global data circuit 121 by a previously performed buffered write operation. When the data on the bank read line rboo 1 and the data on the bank write line WBIO1 are different from each other, the local data circuit 111 may write the data on the bank write line WBIO1 to the selected memory cell. When the data on the bank read line rboo 1 and the data on the bank write line WBIO1 are equal to each other, the local data circuit 111 may not perform a write operation on the selected memory cell.

Fig. 2 illustrates a configuration of a local data circuit 200 according to an embodiment. The local data circuit 200 may be applied as each of the local data circuits 111 to 118 mounted in the plurality of memory banks LBK1 to LBK4 and RBK1 to RBK4 illustrated in fig. 1. Referring to fig. 2, the local data circuit 200 may include a write driver 210, a sense amplifier (sense amplifier)220, and a write data selector 230. The write driver 210 may perform a write operation on memory cells coupled to the write driver 210 during an active write operation. The memory cells may be coupled to write driver 210 by an access line such as a bit line, a global bit line, a word line, or a global word line. The write driver 210 may perform a write operation based on the valid write signal AWT and the write select data WSD. The valid write signal AWT may be generated based on a command signal CMD for performing a valid write operation. The write driver 210 may write the write select data WSD to the memory cell when the valid write signal AWT is enabled.

Sense amplifier 220 may perform a read operation on memory cells coupled to sense amplifier 220 during an active read operation. The memory cells may be coupled to sense amplifiers 220 by access lines such as bit lines, global bit lines, word lines, or global word lines. The sense amplifier 220 may perform a read operation based on the valid read signal ARD. The valid read signal ARD may be generated based on a command signal CMD for performing a valid read operation. The sense amplifier 220 may be coupled to a bank read line RBIO. The sense amplifier 220 may read data stored in the memory cell when the valid read signal ARD is enabled and output the read data to the bank read line RBIO.

The write data selector 230 may be coupled to a bank write line WBIO and a bank read line rboo. The write data selector 230 may receive the write mode signal WTM and output one of data of the bank write line WBIO and data of the bank read line rbo as write selection data WSD based on the write mode signal WTM. The write mode signal WTM may include a flag signal generated based on an operation performed by the semiconductor memory device 100. For example, when a buffered write operation is performed before an active write operation, the write mode signal WTM may have a first level. The write mode signal WTM may have a second level when an active read operation is performed before an active write operation. When the write mode signal WTM has the first level, the write data selector 230 may output the data on the bank write line WBIO as the write select data WSD. When the write mode signal WTM has the second level, the write data selector 230 may output the data on the bank read line rboo as the write select data WSD.

Referring to fig. 2, the local data circuit 200 may further include a comparator 240. Comparator 240 may be coupled to a bank write line WBIO and a bank read line rboo. The comparator 240 may receive the address flag SADD and generate a write driver off signal WOFF. The address flag SADD may have a first level when an active read operation is performed on a specific memory cell before an active write operation is performed on the specific memory cell. That is, the address flag SADD may have the first level when the same memory cell as a memory cell on which an effective read operation is performed before an effective write operation is reselected. The address flag SADD may have the second level when an effective read operation is performed on a certain memory cell before an effective write operation is performed on another memory cell.

When the address flag SADD has the second level, the comparator 240 may be disabled. When the address flag SADD has a first level, the comparator 240 may compare data on the bank write line WBIO with data on the bank read line rbo. When the data on the bank write line WBIO and the data on the bank read line rboo are different from each other, the comparator 240 may disable the write driver turn-off signal WOFF. The write driver 210 can write select data WSD, which is output based on data on the bank write line WBIO, to the memory cell. The comparator 240 may enable the write driver turn-off signal WOFF when data on the bank write line WBIO and data on the bank read line rboo are equal to each other. When the write driver off signal WOFF is enabled, the write driver 210 may be disabled so as not to perform a write operation.

Local data circuit 200 may also include a first latch 250 and a second latch 260. First latch 250 may be coupled to a bank write line WBIO. The first latch 250 may latch and store data transferred through the bank write line WBIO. In an embodiment, the data on the bank write line WBIO refers to the data stored in the first latch 250 of the bank write line WBIO. The first latch 250 then provides the data transferred through the bank write line WBIO to the write data selector 230, the comparator 240, and the read data selector 530 (shown in fig. 5). The second latch 260 may be coupled to a bank read line RBIO. The second latch 260 may latch and store data transferred through the bank read line WBIO. In an embodiment, the data on the bank read line RBIO refers to data stored in the second latch 260 of the bank read line RBIO. Then, the second latch 260 supplies the data transferred through the bank read line rboo to the write data selector 230, the comparator 240, and the read data selector 530.

Local data circuit 200 may also include a write mode signal generator 270. The write mode signal generator 270 may receive the buffered write signal BWT and the valid read signal ARD and generate a write mode signal WTM. The buffered write signal BWT may be generated based on a command signal CMD for performing a buffered write operation. When the buffered write signal BWT is enabled, the write mode signal generator 270 may change the write mode signal WTM to a first level and maintain the voltage level of the write mode signal WTM. When the valid read signal ARD is enabled, the write mode signal generator 270 may change the write mode signal WTM to the second level and maintain the voltage level of the write mode signal WTM.

Fig. 3 illustrates a configuration of the write data selector 230 illustrated in fig. 2. Referring to fig. 3, the write data selector 230 may include a first transfer gate 310 and a second transfer gate 320. The first transmission gate 310 may receive a write mode signal WTM and couple a bank write line WBIO to the output node 331 based on the write mode signal WTM. When the write mode signal WTM has a first level and the complementary signal WTMB of the write mode signal WTM has a second level, the first transmission gate 310 may be turned on to couple the bank write line WBIO to the output node 331 and output data of the bank write line WBIO as write selection data WSD. The first level may be set to a low level, and the second level may be set to a high level. The second transmission gate 320 may receive the write mode signal WTM and couple the bank read line rboo to the output node 331 based on the write mode signal WTM. When the write mode signal WTM has the second level and the complementary signal WTMB of the write mode signal WTM has the first level, the second transfer gate 320 may be turned on to couple the bank read line rbo to the output node 331 and output data of the bank read line rbo as the write select data WSD.

Fig. 4 illustrates a configuration of the write mode signal generator 270 illustrated in fig. 2. Referring to fig. 4, the write mode signal generator 270 may include an inverter 410, a first transistor 420, a second transistor 430, and a latch 450. The inverter 410 may invert and output the buffered write signal BWT. The first transistor 420 may be, for example, a P-channel MOS transistor. The first transistor 420 may have a gate configured to receive the output of the inverter 410, a source coupled to the supply voltage terminal VDD, and a drain coupled to the node 441. The first transistor 420 may drive the node 441 to the power supply voltage VDD when the buffered write signal BWT is enabled at a high level. The second transistor 430 may be, for example, an N-channel MOS transistor. The second transistor 430 may have a gate configured to receive an active read signal ARD, a drain coupled to the node 441, and a source coupled to the ground voltage terminal VSS. When the valid read signal ARD is enabled at a high level, the second transistor 430 may drive the node 441 to the ground voltage VSS. The latch 450 may generate the write mode signal WTM by inverting the voltage level of the node 441, and maintain the level of the write mode signal WTM.

FIG. 5 illustrates a configuration of global data circuit 500 according to one embodiment. The global data circuit 500 may be applied as each of the global data circuits 121 to 128 illustrated in fig. 1. Referring to fig. 5, the global data circuit 500 may include a write latch 510, a read latch 520, and a read data selector 530. The write latch 510 may latch data transferred through the global data line GIO and output the latched data to the bank write line WBIO based on the buffered write signal BWT. Write latch 510 may receive a buffered write strobe signal BWTS. The write latch 510 may gate the data transferred through the global data line GIO and latch the gated data based on the buffered write strobe signal BWTS. The buffered write strobe signal BWTS may be a pulse signal generated based on the buffered write signal BWT.

The read latch 520 may latch the read selection data RSD based on the buffered read signal BRD and output the latched data to the global data line GIO. The buffered read signal BRD may be generated based on a command signal CMD for performing a buffered read operation. The read latch 520 may receive a buffered read strobe signal BRDS. The read latch 520 may gate the read select data RSD based on the buffered read strobe signal BRDS and latch the gated data. The buffered read strobe signal BRDS may be a pulse signal generated based on the buffered read signal BRD.

Read data selector 530 may be coupled to a bank write line WBIO and a bank read line rboo. The read data selector 530 may receive the read mode signal RDM and output one of data located on the bank write line WBIO and data located on the bank read line rboo as read selection data RSD based on the read mode signal RDM. The read mode signal RDM may be generated based on an operation performed by the semiconductor memory device 100. For example, when the buffered write operation is performed before the buffered read operation, the read mode signal RDM may have the first level. When a valid read operation is performed before the buffered read operation, the read mode signal RDM may have the second level. When the read mode signal RDM has a first level, the read data selector 530 may output data located on the bank write line WBIO as read selection data RSD. When the read mode signal RDM has the second level, the read data selector 530 may output data located on the bank read line RBIO as read select data RSD.

Global data circuit 500 may also include a read mode signal generator 540. The read mode signal generator 540 may receive the buffered write signal BWT and the valid read signal ARD and generate a read mode signal RDM. The read mode signal generator 540 may change the read mode signal RDM to a first level and maintain a voltage level of the read mode signal RDM when the buffered write signal BWT is enabled. When the valid read signal ARD is enabled, the read mode signal generator 540 may change the read mode signal RDM to the second level and maintain the voltage level of the read mode signal RDM.

Fig. 6 illustrates a configuration of the read data selector 530 illustrated in fig. 5. Referring to fig. 6, the read data selector 530 may include a first transmission gate 610 and a second transmission gate 620. The first transmission gate 610 may receive a read mode signal RDM and couple a bank write line WBIO to an output node 631 based on the read mode signal RDM. When the read mode signal RDM has a first level and the complement signal RDMB of the read mode signal RDM has a second level, the first transfer gate 610 may be turned on to couple the bank write line WBIO to the output node 631 and output data on the bank write line WBIO as read selection data RSD. The second transfer gate 620 may receive the read mode signal RDM and couple the bank read line RBIO to the output node 631 based on the read mode signal RDM. When the read mode signal RDM has the second level and the complement signal RDMB of the read mode signal RDM has the first level, the second transfer gate 620 may be turned on to couple the bank read line RBIO to the output node 631 and output data on the bank read line RBIO as read selection data RSD.

Fig. 7 illustrates a configuration of the read mode signal generator 540 illustrated in fig. 5. Referring to fig. 7, the read mode signal generator 540 may include an inverter 710, a first transistor 720, a second transistor 730, and a latch 750. The inverter 710 may invert and output the buffered write signal BWT. The first transistor 720 may be, for example, a P-channel MOS transistor. The first transistor 720 may have a gate configured to receive the output of the inverter 710, a source coupled to the supply voltage terminal VDD, and a drain coupled to the node 741. When the buffered write signal BWT is enabled at a high level, the first transistor 720 may drive the node 741 to the power supply voltage VDD. The second transistor 730 may be, for example, an N-channel MOS transistor. The second transistor 730 may have a gate configured to receive an active read signal ARD, a drain coupled to the node 741, and a source coupled to the ground voltage terminal VSS. When the valid read signal ARD is enabled at a high level, the second transistor 730 may drive the node 741 to the ground voltage VSS. The latch 750 may generate the read mode signal RDM by inverting the voltage level of the node 741 and maintain the level of the read mode signal RDM.

Fig. 8 illustrates a memory card including a semiconductor memory device according to some embodiments. Referring to fig. 8, the memory card system 4100 may include a controller 4110, a memory 4120, and an interface member 4130. The controller 4110 and the memory 4120 may be configured to exchange commands and/or data. For example, the memory 4120 may be used to store commands and/or user data to be executed by the controller 4110.

The memory card system 4100 may store data in the memory 4120 or output data from the memory 4120 to the outside. The memory 4120 may include the semiconductor memory device 100 associated with fig. 1.

The interface member 4130 may control input and output of data from and to the outside. The memory card system 4100 may be a multimedia card (MMC), a secure digital card (SD), or a portable data storage device.

FIG. 9 illustrates a block diagram that facilitates explaining an electronic device that includes a semiconductor memory device in accordance with some embodiments. Referring to fig. 9, the electronic device 4200 may include a processor 4210, a memory 4220, and an input and output device 4230. The processor 4210, memory 4220, and input and output devices 4230 may be coupled by a bus 4246.

The memory 4220 may receive control signals from the processor 4210. The memory 4220 may store code and data for the operation of the processor 4210. The memory 4220 may be used to store data to be accessed via the bus 4246. The memory 4220 may include the semiconductor memory device 100 associated with fig. 1. For implementation and modification, additional circuitry and control signals may be provided.

The electronic device 4200 may configure various electronic control devices using the memory 4220. For example, the electronic device 4200 may be used in a computer system, a wireless communication device such as a PDA, a laptop computer, a notebook computer, a web tablet, a wireless phone, a portable phone, a digital music player, an MP3 player, a navigator, a Solid State Drive (SSD), a home appliance, or all devices capable of sending and receiving information in a wireless environment.

A description of implementations and variations of the electronic device 4200 is presented below with reference to fig. 10 and 11.

FIG. 10 illustrates a data storage device including a semiconductor memory device according to some embodiments. Referring to fig. 10, a data storage device such as a Solid State Disk (SSD)4311 may be provided. The Solid State Disk (SSD)4311 may include an interface 4313, a controller 4315, a nonvolatile memory 4318, and a buffer memory 4319.

The solid-state disk 4311 is a device which stores information by using a semiconductor device. The solid state disk 4311 is advantageous in that the speed is high, in addition, mechanical delay, failure rate, heat generation, and noise generation are reduced, and when compared with a Hard Disk Drive (HDD), miniaturization and weight saving can be achieved. The solid state disk 4311 may be widely used in a notebook computer, a netbook, a desktop computer, an MP3 player, or a portable storage device.

Controller 4315 may be formed adjacent to interface 4313 and electrically coupled to interface 4313. Controller 4315 may be a microprocessor that includes a memory controller and a buffer controller. The nonvolatile memory 4318 may be formed adjacent to the controller 4315 and electrically coupled to the controller 4315 via a connection terminal T. The data storage capacity of the solid state disk 4311 may correspond to the non-volatile memory 4318. Buffer memory 4319 may be formed adjacent to controller 4315 and electrically coupled to controller 4315. Each non-volatile memory 4318 may include the semiconductor memory device 100 associated with FIG. 1.

Interface 4313 may be coupled to host 4302 and function to send and receive electrical signals, such as data. For example, interface 4313 may be a device that uses the same protocol as SATA, IDE, SCSI, and/or combinations thereof. Nonvolatile memory 4318 may be coupled to interface 4313 via a controller 4315.

Nonvolatile memory 4318 may function to store data received via interface 4313. The nonvolatile memory 4318 has a characteristic of retaining data stored therein even if power supply to the solid state disk 4311 is cut off.

Buffer memory 4319 may include volatile memory or non-volatile memory. The volatile memory may be DRAM and/or SRAM. The non-volatile memory may include the semiconductor memory device 100 associated with fig. 1.

The data processing speed of interface 4313 may be relatively faster than the operating speed of nonvolatile memory 4318. Buffer memory 4319 may function to temporarily store data. Data received through the interface 4313 may be temporarily stored in the buffer memory 4319 via the controller 4315, and then permanently stored in the nonvolatile memory 4318 in conformity with the data recording speed of the nonvolatile memory 4318.

Frequently used data among data stored in the nonvolatile memory 4318 may be read in advance and temporarily stored in the buffer memory 4319. That is, the buffer memory 4319 may function to increase the effective operating speed and reduce the error occurrence rate of the solid state disk 4311.

FIG. 11 illustrates an electronic system including a semiconductor memory device according to some embodiments. Referring to fig. 11, the electronic system 4400 may include a main body 4410, a microprocessor unit 4420, a power supply unit 4430, a function unit 4440, and a display controller unit 4450.

Main body 4410 may be a motherboard formed of a Printed Circuit Board (PCB). The microprocessor unit 4420, the power supply unit 4430, the function unit 4440, and the display controller unit 4450 may be mounted to the main body 4410. The display unit 4460 may be provided inside the main body 4410 or outside the main body 4410. For example, the display unit 4460 may be disposed on the surface of the main body 4410 and display an image processed by the display controller unit 4450.

The power supply unit 4430 may function to receive a voltage from an external battery or the like, divide the voltage into desired voltage levels, and supply the divided voltage to the microprocessor unit 4420, the function unit 4440, the display controller unit 4450, and the like. The microprocessor unit 4420 may receive a voltage from the power supply unit 4430 and control the function unit 4440 and the display controller unit 4450. The functional unit 4440 may perform various functions of the electronic system 4400. For example, in the case where the electronic system 4400 is a portable telephone, the functional unit 4440 may include various constituent elements capable of performing functions of the portable telephone, such as dialing, outputting images to the display unit 4460 through communication with the external device 4470, outputting voice to a speaker, and the like. The functional unit 4440 may also function as a camera image processor in the case of being mounted with a camera.

In the case where the electronic system 4400 is coupled with a memory card or the like to expand the capacity, the functional unit 4440 may be a memory card controller. The functional unit 4440 may exchange signals with the external device 4470 through the wired or wireless communication unit 4480. In the case where the electronic system 4400 requires a USB or the like to expand the functions, the functional unit 4440 may function as an interface controller. The semiconductor memory device according to the above-described embodiment can be applied as at least any one of the microprocessor unit 4420 and the functional unit 4440.

While various embodiments have been described above, those skilled in the art will appreciate that the described embodiments are merely examples. Accordingly, the semiconductor memory devices described herein should not be limited based on the described implementations.

Cross Reference to Related Applications

This application claims priority from korean application No. 10-2018-.