阅读说明：本技术 用于电力损耗恢复的电路及使用此电路的装置与其方法 (Circuit for power loss recovery and apparatus and method using the same ) 是由 欧伦麦克 金大铉 于 2018-08-17 设计创作，主要内容包括：本发明提供一种用于电力损耗恢复的电路及使用此电路的装置与其方法。电路包含但不限于：存储器电路,包含输出第一存储器输出电压的第一存储器元件以及输出第二存储器输出电压的第二存储器元件；逻辑比较器电路,连接到存储器电路,且包含将第一存储器输出电压与第一电源电压进行比较以产生第一逻辑比较器输出电压的第一逻辑比较器,以及将第二存储器输出电压与第二电源电压进行比较以产生第二逻辑比较器输出电压的第二逻辑比较器；以及逻辑电路,电连接到逻辑比较器电路且接收第一逻辑比较器输出电压及第二逻辑比较器输出电压以执行第一逻辑操作,第一逻辑操作经至少部分地使用以产生上电复位电压。(The invention provides a circuit for power loss recovery, a device using the circuit and a method thereof. Circuits include, but are not limited to: a memory circuit including a first memory element outputting a first memory output voltage and a second memory element outputting a second memory output voltage; a logic comparator circuit connected to the memory circuit and including a first logic comparator comparing the first memory output voltage with a first power supply voltage to generate a first logic comparator output voltage, and a second logic comparator comparing the second memory output voltage with a second power supply voltage to generate a second logic comparator output voltage; and a logic circuit electrically connected to the logic comparator circuit and receiving the first logic comparator output voltage and the second logic comparator output voltage to perform a first logic operation, the first logic operation being used at least in part to generate a power-on-reset voltage.)

1. An electronic device using circuitry for recovering from power loss, comprising:

a power supply circuit; and

a circuit electrically connected to the power supply circuit for recovering from a power loss caused by an output voltage drop from the power supply circuit, wherein the circuit comprises:

a memory circuit including a first memory element outputting a first memory output voltage, and a second memory element outputting a second memory output voltage;

a logic comparator circuit electrically connected to the memory circuit and including a first logic comparator comparing the first memory output voltage with a first power supply voltage received from the power supply circuit to produce a first logic comparator output voltage, and a second logic comparator comparing the second memory output voltage with a second power supply voltage received from the power supply circuit to produce a second logic comparator output voltage; and

a logic circuit electrically connected to the logic comparator circuit and receiving the first and second logic comparator output voltages to perform a first logic operation, the first logic operation used at least in part to generate a power-on reset voltage that resets the memory circuit in response to the output voltage drop from the power supply circuit.

2. The electronic device of claim 1, wherein the first memory output voltage has a binary value opposite the second memory output voltage, the first and second memory output voltages such that the first and second logic comparator output voltages output a same first binary value when a power supply operates normally without the power loss.

3. The electronic device of claim 2, wherein at least one of the first and second logical comparator output voltages outputs a second binary value that is opposite the first binary value when the power source experiences the power loss caused by the output voltage drop from the power source circuit.

4. The electronic device of claim 3, wherein the first logical operation comprises a NAND operation performed by a first logical operation circuit that outputs the second binary value when the power supply operates normally without the power loss and outputs the first binary value when the power supply experiences the power loss caused by the output voltage drop from the power supply circuit.

5. The electronic device of claim 4, wherein the logic comparator circuit further comprises:

a third logic comparator to compare a third memory output voltage with the first power supply voltage received from the power supply circuit to generate a third logic comparator output voltage;

a fourth logic comparator to compare a fourth memory output voltage with the second power supply voltage to generate a fourth logic comparator output voltage; and

a second logic operation circuit receiving the third and fourth logic comparator output voltages to perform a second logic operation on the third and fourth logic comparator output voltages, the second logic operation being a NAND operation.

6. The electronic device of claim 5, wherein the logic circuitry further comprises third logic operation circuitry that receives the NAND operation of the first logic operation circuitry and the NAND operation of the second logic operation circuitry to perform a third logic operation to generate the power-on-reset voltage.

7. The electronic device of claim 6, wherein the third logical operation is an OR operation.

8. The electronic device of claim 1, wherein the first supply voltage received from the power supply circuit is a reference voltage and the second supply voltage received from the power supply circuit is an operating voltage relative to the reference voltage.

9. The electronic device of claim 1, wherein the first memory element of the memory circuit is a virtual memory element dedicated to the circuit.

10. The electronic device of claim 1, wherein the first memory element is a first SR flip-flop set by a power-on-reset and the second memory element is a second SR flip-flop reset by a power-on-reset.

11. A circuit for recovering from power loss, the circuit comprising:

a memory circuit including a first memory element outputting a first memory output voltage, and a second memory element outputting a second memory output voltage;

a logic comparator circuit electrically connected to the memory circuit and comprising a first logic comparator comparing the first memory output voltage to a first power supply voltage to produce a first logic comparator output voltage, and a second logic comparator comparing the second memory output voltage to a second power supply voltage to produce a second logic comparator output voltage; and

a logic circuit electrically connected to the logic comparator circuit and receiving the first and second logic comparator output voltages to perform a first logic operation, the first logic operation used at least in part to generate a power-on-reset voltage.

12. A method for use with an electronic device for recovering power loss of a power supply circuit of the electronic device, the method comprising:

receiving a first memory output voltage from a first memory element and a second memory output voltage from a second memory element;

comparing the first memory output voltage to a first power supply voltage received from the power supply circuit to generate a first logic comparator output voltage; comparing the second memory output voltage to a second power supply voltage received from the power supply circuit and higher than the first power supply voltage to generate a second logic comparator output voltage;

performing a first logical operation by using the first logical comparator output voltage and the second logical comparator output voltage; and

generating a power-on reset voltage based, at least in part, on the first logic operation to reset the power supply circuit in response to the power loss of the power supply circuit.

Technical Field

The present invention relates to a power loss test technology, and more particularly, to a circuit for power loss recovery, and an apparatus and method using the same.

Background

The power loss test may be one of the tests that a chip or Integrated Circuit (IC) manufactured when the chip is evaluated on an assembly line or in a laboratory needs to pass. For example, a mobile phone running on a battery may perform this test. When a chip experiences a sudden loss of power from an internal or external power source, the power level may gradually decrease to a certain level but not directly to zero, which may not trigger a Power On Reset (POR) to generate a reset signal to reset the power circuits of the chip. If the POR is not triggered to reset the chip, the memory element may be in an unknown state.

As shown in fig. 1, after the POR 101 has been triggered, the power supply of the chip may change from 0 volts to the normal bias VCC. However, assuming that the power supply of the chip drops abruptly as shown in power loss region 102, if the power supply drops below the minimum threshold but does not reach a voltage of about 0 volts directly to trigger a POR as shown in dead region 103, the memory elements of the chip may enter an unknown state. The dead zone region 103 refers to the range of supply voltages within which the memory element will not be guaranteed to maintain its recorded state while POR will not be triggered.

The reason that the chip will likely be in an unknown state is that when the power supply level drops too slowly, the recording state of the memory element is lost. When the power supply level drops to the dead band region 103, memory elements such as flip-flops, latches, etc. may not be able to hold their recorded state and thus cause the chip to enter an unknown state. After the chip enters an unknown state, the chip will likely fail because the state machine will not be able to enter the expected state. Therefore, the chip entering an unknown state caused by the power supply entering the dead zone region 103 may be a problem to be solved.

Disclosure of Invention

The invention provides a circuit for power loss recovery, a device using the circuit and a method thereof.

A circuit for recovering from power loss is disclosed, which should include but is not limited to: a memory circuit including a first memory element outputting a first memory output voltage and a second memory element outputting a second memory output voltage; a logic comparator circuit electrically connected to the memory circuit and comprising a first logic comparator comparing the first memory output voltage to a first power supply voltage to produce a first logic comparator output voltage, and a second logic comparator comparing the second memory output voltage to a second power supply voltage higher than the first power supply voltage to produce a second logic comparator output voltage; and a logic circuit electrically connected to the logic comparator circuit and receiving the first logic comparator output voltage and the second logic comparator output voltage to perform a first logic operation, the first logic operation being used at least in part to generate a power-on-reset voltage.

An electronic device using circuitry for recovering from power loss is disclosed, which should include but is not limited to: a power supply circuit; and a circuit electrically connected to the power supply circuit for recovering from a power loss caused by an output voltage drop from the power supply circuit, wherein the circuit includes: a memory circuit having a first memory element outputting a first memory output voltage and a second memory element outputting a second memory output voltage; a logic comparator circuit electrically connected to the memory circuit and including a first logic comparator that compares the first memory output voltage with a first power supply voltage received from the power supply circuit to generate a first logic comparator output voltage, and a second logic comparator that compares the second memory output voltage with a second power supply voltage received from the power supply circuit and higher than the first power supply voltage to generate a second logic comparator output voltage; and a logic circuit electrically connected to the logic comparator circuit and receiving a first logic comparator output voltage and the second logic comparator output voltage to perform a first logic operation, the first logic operation used at least in part to generate a power-on reset voltage that resets the memory circuit in response to the output voltage drop from the power circuit.

A method for use with an electronic device for recovering from power loss is disclosed, which should include, but is not limited to: receiving a first memory output voltage from a first memory element and a second memory output voltage from a second memory element; comparing the first memory output voltage to a first power supply voltage received from the power supply circuit to generate a first logic comparator output voltage; comparing the second memory output voltage to a second power supply voltage received from the power supply circuit and higher than the first power supply voltage to generate a second logic comparator output voltage; performing a first logical operation by using the first logical comparator output voltage and the second logical comparator output voltage; and generating a power-on reset voltage based at least in part on the first logic operation to reset the power source in response to a power loss of the power source.

In order to facilitate an understanding of the foregoing features and advantages of the disclosure, the following detailed description of embodiments is provided with accompanying drawings. It is to be understood that both the foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the disclosure as claimed.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated into and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

Fig. 1 illustrates the phenomenon of "dead zone" regions that may cause the chip to fail.

FIG. 2 illustrates in block diagram hardware for a circuit that recovers from power loss of a power supply within an electronic device.

Fig. 3 illustrates a method for recovering from power loss of a power source for use with an electronic device as described in the present disclosure.

Fig. 4 illustrates an embodiment of a method for recovering from power loss of a power source for use with an electronic device.

FIG. 5 illustrates a circuit for recovering from power loss of a power source within an electronic device in an embodiment in accordance with the disclosure.

FIG. 6 illustrates another circuit for recovering from power loss of a power source within an electronic device in an embodiment in accordance with the disclosure.

Fig. 7 illustrates a phenomenon diagram for moving a memory state of an electronic device from an unknown state to a known state by using the circuit of fig. 6 in an embodiment according to the present disclosure.

Description of the reference numerals

101. 702: power-on reset

102: region of power loss

103. 701, a step of: dead zone region

200: circuit arrangement

201: memory circuit

202: logic comparator circuit

203: logic circuit

S301-S305, S401-S405: step (ii) of

501: first memory element/dummy memory element

501 o: first memory output voltage/output voltage

502: second memory element

502 o: second memory output voltage/output voltage

503: third memory element

503 o: third memory output voltage/output voltage

504: fourth memory element/dummy memory element

504 o: fourth memory output voltage/output voltage

511: first logic comparator/first logic comparator circuit

511 o: first logic comparator output voltage/output voltage

512: second logic comparator/second logic comparator circuit

512 o: second logic comparator output voltage/output voltage

513: third logic comparator/third logic comparator circuit

513 o: third logic comparator output voltage/output voltage

514: fourth logic comparator/fourth logic comparator circuit

514 o: fourth logic comparator output voltage/output voltage

521: first logic operation circuit/logic gate

521 o: first logic operation circuit output

522: second logic operation circuit

522 o: second logic operation circuit output

523: third logic operation circuit/logic gate

601: first SR flip-flop

602: second SR flip-flop

603: third SR flip-flop

604: fourth SR flip-flop

And (3) POR: power-on reset/signal

PORb, DZ _ POR, PWV _ POR, PUMP _ LEVEL _ DETECTOR: signal

Detailed Description

Reference will now be made in detail to the present embodiments of the disclosure.

In the present disclosure, a method and circuit suitable for an electronic device to detect the aforementioned dead zone region 103 and to revert from an unknown memory element state to a known memory element state resulting from the dead zone region 103 is described. When the dead zone region 103 has been detected, a Power On Reset (POR) will be issued to reset the power supply of the electronic device, thereby reverting to a known state. One technique for detecting the dead zone region 103 would include comparing the desired value loaded into the memory element to a predetermined supply voltage value.

During the power-on state, values from the non-volatile memory are loaded into the memory elements. These values are referred to as DZD modes and are analog voltages, which may be, for example, high, low, or bandgap voltages used to test supply voltages using comparators. The memory elements may be, for example, latches, flip-flops, virtual memories, and the like. The DZD mode may be hard wired internal to the IC or loaded into the IC from an external power source. After the sequence of power-on has been completed, the value from the memory element is compared to a power supply voltage, which may be a predetermined value. Under normal operating conditions, these values will be matched by the comparator to produce a match result, and the match result will not trigger POR. In the case of power loss and/or memory element derating, the match result will likely trigger POR when the supply voltage recovers. After triggering POR, a sequence of power-on will be initiated.

In one aspect, the present disclosure provides a circuit that will solve the above-described problem of recovering from power loss caused by an output voltage drop from a power supply circuit. Referring to fig. 2, the circuit will be electrically connected to the power circuit, and both the circuit and the power circuit may be disposed within the electronic device. The circuit 200 will include, but is not limited to, a memory circuit 201, a logic comparator circuit 202, a logic circuit 203 that outputs a POR signal line, and the like.

The memory circuit 201 may include, but is not limited to, a first memory element outputting a first memory output voltage, and a second memory element outputting a second memory output voltage. The logic comparator circuit 202, which is electrically connected to the memory circuit 201, may include, but is not limited to, a first logic comparator that compares a first memory output voltage with a first power supply voltage received from the power supply circuit to generate a first logic comparator output voltage, and a second logic comparator that compares a second memory output voltage with a second power supply voltage received from the power supply circuit to generate a second logic comparator output voltage. Logic circuitry 203, electrically connected to logic comparator circuitry 202, will receive the first and second logic comparator output voltages to perform a first logic operation that is used, at least in part, to generate a power-on-reset (POR) voltage that resets the memory circuitry in response to an output voltage drop from the power circuitry.

In one embodiment, the first memory output voltage has a binary value opposite to the second memory output voltage, and the first memory output voltage and the second memory output voltage cause the first logic comparator output voltage and the second logic comparator output voltage to output the same first binary value when the power supply operates normally without power loss. However, when the power supply experiences a power loss caused by an output voltage drop from the power supply circuit, at least one of the first and second logical comparator output voltages outputs a second binary value opposite to the first binary value.

In an embodiment, the first logic operation may be a nand operation performed by the first logic operation circuit, which outputs the second binary value when the power supply operates normally without power loss, and outputs the first binary value when the power supply experiences power loss caused by an output voltage drop from the power supply circuit.

In an embodiment, the logic comparator circuit 202 may additionally include, but is not limited to: a third logic comparator to compare the third memory output voltage with the first power supply voltage received from the power supply circuit to generate a third logic comparator output voltage; a fourth logic comparator to compare the fourth memory output voltage with the second power supply voltage to generate a fourth logic comparator output voltage; and a second logic operation circuit receiving the third and fourth logic comparator output voltages to perform a second logic operation on the third and fourth logic comparator output voltages, the second logic operation may be a nand operation, for example.

In an embodiment, the logic circuit 203 may additionally include, but is not limited to, a third logic operation circuit that receives a nand operation of the first logic operation circuit and a nand operation of the second logic operation circuit to perform a third logic operation, thereby generating a power-on reset (POR) voltage.

In an embodiment, the first memory element of the memory circuit 201 may be a circuit-specific virtual memory element (i.e., a general-purpose storage medium that is not used as a processor, controller, etc.). Alternatively, the first memory element may be a first SR flip-flop set by a power-on reset, and the second memory element may be a second SR flip-flop reset by a power-on reset.

The present disclosure also provides a method for use with an electronic device having a circuit 200 for recovering from power loss of a power supply as described in the present disclosure. The present disclosure will include, but is not limited to, the steps described below. In step S301, the circuit may receive a first memory output voltage from a first memory element and a second memory output voltage from a second memory element. In step S302, the circuit may compare the first memory output voltage with a first power supply voltage received from a power supply circuit to generate a first logic comparator output voltage. In step S303, the circuit may compare the second memory output voltage with a second power supply voltage received from the power supply circuit to generate a second logic comparator output voltage. In step S304, the circuit may perform a first logic operation by using the first logic comparator output voltage and the second logic comparator output voltage. In step S305, the circuit may generate a power-on reset voltage based at least in part on a first logic operation for resetting the memory circuit in response to a power loss of the power supply.

In an embodiment, the first memory output voltage may have a binary value opposite to the second memory output voltage, the first memory output voltage and the second memory output voltage causing the first logic comparator output voltage and the second logic comparator output voltage to output the same first binary value when the power supply operates normally without power loss. At least one of the first logical comparator output voltage and the second logical comparator output voltage may output a second binary value opposite to the first binary value when the power supply experiences a power loss caused by an output voltage drop from the power supply circuit.

In an embodiment, the first logic operation may be a nand operation that outputs the second binary value when the power supply operates normally without power loss, and outputs the first binary value when the power supply experiences power loss caused by an output voltage drop from the power supply circuit.

To further clarify the above concepts, the present disclosure provides several embodiments as disclosed in fig. 4-6 and their corresponding written descriptions. The method may include, but is not limited to, the steps described below. In step S401, the electronic device will perform a power-on operation, which may include turning on the electronic device, waking the electronic device from a sleep mode, and the like. In step S402, the electronic device may optionally perform a fuse read operation (fuse read operation), which will allow the electronic device to fetch the DZD mode for comparison. In step S403, the electronic device will obtain the DZD mode. The DZD mode can be obtained from the fuse reading in step S402. Alternatively, the DZD mode may be pre-existing because it may be hardwired to a circuit or memory element of the electronic device. Furthermore, the DZD mode may alternatively be obtained from an external power source, such as a Central Processing Unit (CPU) or an external controller. In step S404, once the DZD mode is obtained, the electronic device loads the DZD mode into a memory device such as a virtual memory device, a latch, a flip-flop, etc. Alternatively, the DZD mode may be pre-existing in the memory element or programmed into the memory element from an external power source. In step S405, the circuit should compare the DZD mode with a predetermined voltage value from the power supply through one or more comparators to generate the POR signal. The comparison will be continuous in that the circuit will keep monitoring the dead band region 103. Once the comparison between the DZD mode and the predetermined voltage value does not yield the desired value, the process will continue at step S401, triggering a POR reset.

Referring to FIG. 5, the circuit may include, but is not limited to, a plurality of memory elements 501-504 that are part of the memory circuit 201, a plurality of comparators 511-514 that are part of the logic comparator circuit 202, and a plurality of logic gates 521-523 that are part of the logic circuit 203. The logic circuit will be configured to generate the POR in response to the power supply voltage (i.e., the dead zone region 103) falling below a certain threshold.

The plurality of memory elements 501-504 may be dummy memory elements, meaning that the dummy memory elements are not used as actual memory, but rather the circuit of fig. 5 is dedicated to storing the DZD pattern for subsequent comparison. The dummy memory elements will include a first memory element 501 outputting a first memory output voltage 501o, a second memory element 502 outputting a second memory output voltage 502o, a third memory element 503 outputting a third memory output voltage 503o, and a fourth memory element 504 outputting a fourth memory output voltage 504 o. In this embodiment, the DZD mode may be a sequence of high, low, high, low (e.g., 1010) voltages loaded into virtual memory element 501 through virtual memory element 504, respectively, although it is understood that the disclosure is not limited to this particular set of sequences. Therefore, the output voltage 501o, the output voltage 502o, the output voltage 503o, and the output voltage 504o will be high-low-high (e.g., 1010), respectively.

The logic comparator circuit 202 electrically connected to the memory circuit 201 may include, but is not limited to, a first logic comparator 511 that compares the first memory output voltage 501o with a first power supply voltage (e.g., ground voltage or Vss) received from the power supply circuit to generate a first logic comparator output voltage 511o, a second logic comparator 512 that compares the second memory output voltage 502o with a second power supply voltage (e.g., Vcc) received from the power supply circuit and higher than the first power supply voltage (e.g., ground voltage or Vss) to generate a second logic comparator output voltage 512o, a third logic comparator 513 that compares the third memory output voltage 503o with the first power supply voltage (e.g., ground voltage or Vss) received from the power supply circuit to generate a third logic comparator output voltage 513o, and a fourth memory output voltage 504o with the second power supply voltage (e.g., vcc) to generate a fourth logic comparator output voltage 514 o.

The second logic comparator 512 may be a nor gate that compares the second memory output voltage 502o with a second power supply voltage (e.g., Vcc) to generate a second logic comparator output voltage 512o, such as by performing a nor operation. Similarly, the fourth logic comparator 514 may be a nor gate that compares the fourth memory output voltage 504o with a fourth supply voltage (e.g., Vcc) by performing a nor operation to generate the fourth logic comparator output voltage 514 o.

Comparators 511-514 will generate either a high voltage or a low voltage based on the comparison. It should be noted that the actual voltage level used by the comparators (511-514) as the high or low voltage outputs may not necessarily be the same as the high and low voltages of the dummy memory elements (501-504). Under normal operating conditions, the first logic comparator output voltage 511o may be configured as a high voltage (e.g., 1) because the comparison result between the first memory output voltage 501o and the first power supply voltage (e.g., ground voltage or Vss) is configured to generate a high voltage. The second logic comparator output voltage 512o may be configured as a high voltage (e.g., 1) because the result of the comparison between the second memory output voltage 502o and the second power supply voltage (e.g., Vcc) is configured to generate a high voltage. The third logic comparator output voltage 513o may be configured as a high voltage (e.g., 1) because the comparison between the third memory output voltage 503o and the first power supply voltage (e.g., ground voltage or Vss) is configured to generate a high voltage. The fourth logic comparator output voltage 514o is configured as a high voltage (e.g., 1) because the comparison between the fourth memory output voltage 504o and the second power supply voltage (e.g., Vcc) is configured to generate a high voltage. It should be noted that since the DZD mode is programmable, the actual logic gates and output values can be arbitrary.

In one embodiment, assuming the DZD mode is 1010, the first logic comparator 511 may be an and gate, the second logic comparator 512 may be a nor gate, the third logic comparator 513 may be an and gate, and the fourth logic comparator 514 may be a nor gate. For example, under normal operating conditions, the first memory output voltage 501o will output a high voltage (e.g., 1), and thus the first logic comparator output voltage 511o will also output a high voltage. However, assuming that a dead-band phenomenon has occurred, resulting in the first memory output voltage 501o outputting a low voltage, the first logic comparator output voltage 511o will also be a low voltage.

Also, for example, under normal operating conditions, assume that the second memory output voltage 502o is configured to output a low voltage, so the second logic comparator output voltage 512o outside the nor gate will also output a high voltage as a result of comparison with a reference voltage (e.g., a low voltage). However, assuming an abnormal operating condition has occurred, resulting in the second memory output voltage 502o outputting a high voltage, the second logic comparator output voltage 512o will also be a low voltage. The third logic comparator circuit 513 and the fourth logic comparator circuit 514 will operate in a similar manner as the first logic comparator circuit 511 and the second logic comparator circuit 512, respectively.

However, in the event of power loss in the dead zone region, the voltage Vcc will drop but will not reach zero very quickly. The drop in Vcc will cause a drop in the voltage of at least a second power supply voltage (e.g., Vcc) in the second logic comparator 512, e.g., the voltage of the comparison result with the second memory output voltage 502o may result in a low voltage (e.g., 0). Similarly, a drop in Vcc will cause a drop in the voltage of at least a second power supply voltage (e.g., Vcc) in the fourth logic comparator 514, e.g., the comparison with the fourth memory output voltage 504o may result in a low voltage (e.g., 0). Furthermore, since power loss may cause the voltages of the dummy memory cell 501 to the memory cell 504 to be unstable, the comparison results of the first and third logic comparators 511 and 513 may not produce the expected high voltage (e.g., 1) result, but may instead output a low voltage (e.g., 0).

The logic circuit 203 may include a first logic operation circuit 521, a second logic operation circuit 522, and a third logic operation circuit 523. In this embodiment, the first logic operation circuit 521 and the second logic operation circuit 522 are both circuits that can perform nand operations (e.g., nand gates), and the third logic operation circuit 523 is a circuit that can perform or operations (e.g., or gates). Under normal operation, since the first and second logic comparator output voltages 511o and 512o are both high, the first logic operation circuit output 521o will be low (e.g., 0), and since the third and fourth logic comparator output voltages 513o and 514o are both high, the second logic operation circuit output 522o will also be low (e.g., 0).

However, in an abnormal operating condition, such as when the dead band region 103 has occurred, at least one or more of the comparator output voltage 511o, the comparator output voltage 512o, the comparator output voltage 513o, the comparator output voltage 514o may be a low voltage. As long as any one of the output voltage 511o, the output voltage 512o, the output voltage 513o, and the output voltage 514o can be a low voltage, at least one of the first logic operation circuit output 521o and the second logic operation circuit output 522o will be a high voltage due to the operation principle of the nand gate. As long as either one of the first and second logical operation circuit outputs 521o and 522o is a high voltage, the output of the third logical operation circuit 523 will be a high voltage due to the operating principle of the or gate. The high voltage of the third logic operation circuit 523 will trigger POR.

Conceptually, the first memory output voltage 501o has a binary value opposite to the second memory output voltage 502o, and the first memory output voltage 501o and the second memory output voltage 502o cause the first logic comparator output voltage 511o and the second logic comparator output voltage 512o to output the same high voltage when the power supply operates normally without power loss. However, when the power supply experiences a power loss caused by an output voltage drop from the power supply circuit, at least one of the first logical comparator output voltage 511o and the second logical comparator output voltage 512o will output a low voltage. Any of the comparators 511 to 514 outputting a low voltage will be processed by the logic circuit 203 to trigger POR.

In an embodiment, as an alternative to memory element 501-memory element 504 being virtual memory elements, the memory elements may be other types of memory elements, such as latches, flip-flops, and the like. Referring to fig. 6, the memory element may be implemented by using a plurality of SR flip-flops, which may include, but are not limited to, a first SR flip-flop 601 receiving a first voltage of a DZD mode from an S terminal of the first SR flip-flop, and a second SR flip-flop 602 receiving a second voltage of the DZD mode from an R terminal of a second SR flip-flop (e.g., 602). Fig. 6 also shows a third SR flip-flop 603 and a fourth SR flip-flop 604, which are identical to the first SR flip-flop 601 and the second SR flip-flop 602. In this way, the DZD mode can be received externally and programmed into the SR flip-flops according to typical operating principles of the SR flip-flops. The operating principle of the rest of fig. 7 will be the same as that of fig. 6, since the DZ _ POR terminal of fig. 6 will trigger POR after the polarity switching of the DZ _ POR output.

Fig. 7 shows that the state of the memory elements of the electronic device should be in a known state under normal operating conditions. However, when the dead zone region 701 has occurred, the memory element state of the electronic device may become an unknown state. By using the circuit of fig. 6, since Vcc of the power supply of the electronic device has been restored to a certain level, the output of the POR signal line (DZ _ POR) will switch polarity to trigger the POR 702. After POR702 occurs, the memory element state of the electronic device will revert to a known state.

In view of the foregoing, the present disclosure is applicable in electronic devices and is capable of detecting a power loss state to generate a power-on reset during the power loss state to change the state of a memory element of the electronic device from an unknown state back to a known state. By using the invention, the electronic device (1) can recover (2) from an unknown state when the power supply drops below a certain level to a "dead zone region" can be a monitor and detect power loss by comparing the output voltages of the memory elements (3) will increase application reliability in case of power loss, especially in mobile applications (4) can increase security (5) by generating a chip reset in case a hacker tries to put the IC chip in an unknown state to attack it and can save power, using less power for the provided design than an accurate VCC level detector.

It will be apparent to those skilled in the art that various modifications and variations can be made in the structure of the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they come within the scope of the appended claims and their equivalents.