阅读说明：本技术 半导体存储器装置及其操作方法 (Semiconductor memory device and method of operating the same ) 是由 金荣均 李显雨 于 2019-04-26 设计创作，主要内容包括：本公开提供了半导体存储器装置及其操作方法。半导体存储器装置包括存储器单元阵列、外围电路、控制逻辑和温度传感器。存储器单元阵列包括多个存储器单元。外围电路对存储器单元阵列执行操作。控制逻辑控制外围电路的操作,并且生成表示外围电路的操作是否完成的就绪-忙碌信号。温度传感器测量半导体存储器装置的温度。控制逻辑基于温度来生成就绪-忙碌信号。(The present disclosure provides a semiconductor memory device and an operating method thereof. A semiconductor memory device includes a memory cell array, peripheral circuitry, control logic, and a temperature sensor. The memory cell array includes a plurality of memory cells. The peripheral circuits perform operations on the memory cell array. The control logic controls operation of the peripheral circuit and generates a ready-busy signal indicating whether operation of the peripheral circuit is complete. The temperature sensor measures a temperature of the semiconductor memory device. The control logic generates a ready-busy signal based on the temperature.)

1. A semiconductor memory device, comprising:

a memory cell array including a plurality of memory cells;

peripheral circuitry configured to perform operations on the array of memory cells;

control logic configured to control operation of the peripheral circuitry and to generate a ready-busy signal indicating whether operation of the peripheral circuitry is complete; and

a temperature sensor configured to measure a temperature of the semiconductor memory device,

wherein the control logic generates the ready-busy signal based on the temperature.

2. The semiconductor memory device of claim 1, wherein the control logic provides a virtual busy time to generate the ready-busy signal when the temperature is above a predetermined reference temperature.

3. The semiconductor memory device according to claim 2, wherein the control logic maintains a busy state of the ready-busy signal during the virtual busy time after an operation of the peripheral circuit is completed.

4. The semiconductor memory device according to claim 3, wherein the control logic includes a ready-busy signal generator having:

a reference temperature storage section configured to store the reference temperature;

a virtual busy determiner configured to generate a virtual busy activation signal by comparing the temperature and the reference temperature; and

a signal generator configured to generate the ready-busy signal based on the virtual busy activation signal.

5. The semiconductor memory device according to claim 4, wherein the virtual busy determiner:

enable the virtual busy activation signal when the temperature is above the reference temperature; and

disabling the virtual busy activation signal when the temperature is equal to or below the reference temperature.

6. The semiconductor memory device according to claim 5, wherein when the virtual busy activation signal is enabled, the signal generator changes a state of the ready-busy signal to a ready state after the signal generator stands by for the virtual busy time from a time when an operation of the peripheral circuit is completed.

7. The semiconductor memory device according to claim 5, wherein the signal generator changes a state of the ready-busy signal to a ready state at a time when an operation of the peripheral circuit is completed when the virtual busy activation signal is disabled.

8. The semiconductor memory device according to claim 3, wherein the control logic includes a ready-busy signal generator having:

a reference temperature storage part configured to store a virtual busy table including a plurality of reference temperature ranges and respectively corresponding virtual busy times;

a virtual busy determiner configured to generate a virtual busy activation signal by comparing the temperature to the virtual busy table; and

a signal generator configured to generate the ready-busy signal based on the virtual busy activation signal.

9. A method for operating a semiconductor memory device, the method comprising:

receiving an operation command from a controller;

executing an operation corresponding to the received operation command; and

controlling a ready-busy signal output from the semiconductor memory device to the controller according to a temperature of the semiconductor memory device.

10. The method of claim 9, wherein the ready-busy signal maintains a busy state during the operation.

11. The method of claim 10, wherein controlling the ready-busy signal comprises:

checking a temperature of the semiconductor memory device;

comparing the temperature to a predetermined reference temperature; and

controlling the ready-busy signal based on a comparison result.

12. The method of claim 11, wherein controlling the ready-busy signal based on the comparison result comprises:

waiting for a predetermined virtual busy time when the temperature is higher than the reference temperature; and

changing the state of the ready-busy signal from a busy state to a ready state after the predetermined virtual busy time.

13. The method of claim 11, wherein controlling the ready-busy signal based on the comparison result comprises:

changing a state of the ready-busy signal from a busy state to a ready state when the temperature is equal to or lower than the reference temperature.

14. The method of claim 10, wherein controlling the ready-busy signal comprises:

checking a temperature of the semiconductor memory device;

comparing the temperature to a predetermined virtual busy table; and

controlling the ready-busy signal based on a comparison result.

15. The method of claim 14, wherein the virtual busy table comprises a plurality of reference temperature ranges and respective corresponding virtual busy times.

16. The method of claim 15, wherein controlling the ready-busy signal based on the comparison result comprises: changing a state of the ready-busy signal from a busy state to a ready state after a virtual busy time corresponding to a reference temperature portion to which the temperature of the semiconductor memory device belongs.

17. The method of claim 9, wherein the operation command is a program command.

18. The method of claim 9, wherein the operation command is an erase command.

19. A memory device for performing data operations in response to commands from a controller, the memory device comprising:

a sensor configured to measure a temperature of the memory device during the data operation; and

control logic configured to provide a busy signal to the controller during the data operation and a ready signal to the controller upon completion of the data operation,

wherein when the temperature is above a threshold, the control logic provides the busy signal to the controller instead of the ready signal for a predetermined time even after the completion.

Technical Field

The present disclosure relates generally to electronic devices. In particular, the present disclosure relates to semiconductor memory devices and methods of operating the same.

Background

The memory device may be formed in a two-dimensional structure in which strings are horizontally arranged with respect to the semiconductor substrate; or in a three-dimensional structure in which the strings are vertically aligned with respect to the semiconductor substrate. The three-dimensional semiconductor device is a memory device formed to overcome the integration limit of the two-dimensional semiconductor device, and may include a plurality of memory cells vertically stacked on a semiconductor substrate.

Disclosure of Invention

Drawings

Various exemplary embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

In the drawings, the scale of the drawings may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. Like reference numerals refer to like elements throughout.

Fig. 1 is a block diagram showing a memory system including a semiconductor memory device and a controller.

Fig. 2 is a block diagram illustrating a structure of the semiconductor memory device of fig. 1.

FIG. 3 is a diagram illustrating an embodiment of the memory cell array of FIG. 2.

FIG. 4 is a diagram illustrating an embodiment of the memory cell array of FIG. 2.

FIG. 5 is a diagram illustrating an embodiment of the memory cell array of FIG. 2.

Fig. 6 is a diagram showing a pin configuration of the semiconductor memory device.

Fig. 7 is a block diagram illustrating an exemplary embodiment of the ready-busy signal generator of fig. 2.

Fig. 8A and 8B are timing diagrams illustrating operations of the semiconductor memory apparatus according to an embodiment of the present disclosure.

Fig. 9 is a flowchart illustrating an operating method of a semiconductor memory device according to another embodiment of the present disclosure.

FIG. 10 is a flow diagram illustrating an embodiment of the steps of FIG. 9.

FIG. 11 is a flow diagram illustrating an embodiment of the steps of FIG. 9.

FIG. 12 is a diagram illustrating an exemplary embodiment of a virtual busy table.

Fig. 13 is a block diagram illustrating a memory system including the semiconductor memory device of fig. 2.

Fig. 14 is a block diagram showing an application example of the memory system of fig. 13.

Fig. 15 is a block diagram illustrating a computing system including the memory system described with reference to fig. 14.

Embodiments provide a semiconductor memory device having improved reliability and an operating method thereof.

According to an aspect of the present disclosure, there is provided a semiconductor memory device including: a memory cell array including a plurality of memory cells; peripheral circuitry configured to perform operations on the array of memory cells; control logic configured to control operation of the peripheral circuit and to generate a ready-busy signal indicating whether operation of the peripheral circuit is complete; and a temperature sensor configured to measure a temperature of the semiconductor memory device, wherein the control logic generates the ready-busy signal based on the temperature.

The control logic may provide a virtual busy time to generate the ready-busy signal when the temperature is above a predetermined reference temperature.

The control logic may maintain a busy state of the ready-busy signal during the virtual busy time after operation of the peripheral circuit is completed.

The control logic may include a ready-busy signal generator. The ready-busy signal generator may have: a reference temperature storage section configured to store the reference temperature; a virtual busy determiner configured to generate a virtual busy activation signal by comparing the temperature and the reference temperature; and a signal generator configured to generate the ready-busy signal based on the virtual busy activation signal.

The virtual busy determiner may enable the virtual busy activation signal when the temperature is above the reference temperature and disable the virtual busy activation signal when the temperature is equal to or below the reference temperature.

When the virtual busy activation signal is enabled, the signal generator may change a state of the ready-busy signal to a ready state after the signal generator stands by for the virtual busy time from a time when an operation of the peripheral circuit is completed.

When the virtual busy activation signal is disabled, the signal generator may change the state of the ready-busy signal to a ready state at a time when the operation of the peripheral circuit is completed.

The control logic may include a ready-busy signal generator. The ready-busy signal generator may include: a reference temperature storage section configured to store a virtual busy table including a plurality of reference temperature ranges and respectively corresponding virtual busy times; a virtual busy determiner configured to generate a virtual busy activation signal by comparing the temperature to the virtual busy table; and a signal generator configured to generate the ready-busy signal based on the virtual busy activation signal.

According to another aspect of the present disclosure, there is provided a method for operating a semiconductor memory device, the method including: receiving an operation command from a controller; executing an operation corresponding to the received operation command; and controlling a ready-busy signal output from the semiconductor memory device to the controller according to a temperature of the semiconductor memory device.

The ready-busy signal may maintain a busy state during the operation.

Controlling the ready-busy signal may include: checking a temperature of the semiconductor memory device; comparing the temperature to a predetermined reference temperature; and controlling the ready-busy signal based on the comparison result.

Controlling the ready-busy signal based on the comparison result may include: waiting for a predetermined virtual busy time when the temperature is higher than the reference temperature; and changing the state of the ready-busy signal from a busy state to a ready state after the predetermined virtual busy time.

Controlling the ready-busy signal based on the comparison result may include: changing a state of the ready-busy signal from a busy state to a ready state when the temperature is equal to or lower than the reference temperature.

Controlling the ready-busy signal may include: checking a temperature of the semiconductor memory device; comparing the temperature to a predetermined virtual busy table; and controlling the ready-busy signal based on the comparison result.

The virtual busy table may include a plurality of reference temperature ranges and corresponding virtual busy times, respectively.

Controlling the ready-busy signal based on the comparison result may include: changing a state of the ready-busy signal from a busy state to a ready state after a virtual busy time corresponding to a reference temperature portion to which the temperature of the semiconductor memory device belongs.

The operation command may be a program command.

The operation command may be an erase command.

According to another aspect of the present disclosure, there is provided a memory device for performing a data operation in response to a command from a controller, the memory device including: a sensor configured to measure a temperature of the memory device during the data operation; and control logic configured to provide a busy signal to the controller during the data operation and a ready signal to the controller upon completion of the data operation, wherein when the temperature is above a threshold, the control logic provides the busy signal to the controller instead of the ready signal for a predetermined time even after the completion.