阅读说明：本技术 半导体存储器装置 (Semiconductor memory device with a memory cell having a plurality of memory cells ) 是由 孙昌万 申铉守 全哉垠 黄盛炫 于 2018-12-11 设计创作，主要内容包括：一种半导体存储器装置,该半导体存储器装置包括：多条位线,其沿着与第一方向交叉的第二方向设置在存储器单元上方；以及多条第一布线和多条第二布线,其沿着第二方向交替地设置在位线上方,并且在弯曲成锯齿形的同时在第一方向上延伸。(A semiconductor memory device, the semiconductor memory device comprising: a plurality of bit lines disposed over the memory cells along a second direction crossing the first direction; and a plurality of first wirings and a plurality of second wirings alternately disposed above the bit lines along the second direction and extending in the first direction while being bent in a zigzag shape.)

1. A semiconductor memory device, the semiconductor memory device comprising:

a plurality of bit lines disposed over the memory cells; and

a plurality of first wirings and a plurality of second wirings alternately disposed above the bit lines along a second direction and extending in a first direction crossing the second direction while being bent in a zigzag shape.

2. The semiconductor memory device according to claim 1, wherein the bit line is arranged along the second direction and extends in the first direction.

3. The semiconductor memory device according to claim 1, further comprising:

a source plate supporting the memory cell; and

a logic circuit disposed above the substrate and below the source plate,

wherein the first wiring is electrically coupled with the logic circuit, and the second wiring is electrically coupled with the source board.

4. The semiconductor memory device according to claim 1, wherein a ground voltage is supplied to the first wiring, and a source voltage is supplied to the second wiring.

5. The semiconductor memory device according to claim 1,

wherein each of the first wirings includes a plurality of convex portions and a plurality of concave portions on each of one surface and the other surface facing away from each other in the second direction,

wherein the convex portion provided on one surface of each of the first wirings is aligned in the first direction with the concave portion provided on one surface of an adjacent first wiring facing the one surface of each of the first wirings, and

wherein the convex portion provided on the other surface of each of the first wirings is aligned with the concave portion provided on the other surface of the adjacent first wiring facing the other surface of each of the first wirings along the first direction.

6. The semiconductor memory device according to claim 1,

wherein each of the second wirings includes a plurality of convex portions and a plurality of concave portions on each of one surface and the other surface facing away from each other in the second direction,

wherein the convex portion provided on one surface of each of the second wirings is aligned with the concave portion provided on one surface of an adjacent second wiring facing the one surface of each of the second wirings along the first direction, and

wherein the convex portion provided on the other surface of each of the second wirings is aligned with the concave portion provided on the other surface of the adjacent second wiring facing the other surface of each of the second wirings along the first direction.

7. The semiconductor memory device according to claim 1, wherein each of the first wiring and the second wiring includes a crack-suppressing structure.

8. The semiconductor memory device according to claim 7, wherein the crack suppression structure includes a slit that divides each of the first wiring and the second wiring into a plurality of sub-wirings.

9. The semiconductor memory device according to claim 8, wherein the slit extends in the first direction while being bent in a zigzag shape.

10. A semiconductor memory device, the semiconductor memory device comprising:

a plane disposed in the cell region and including a plurality of memory cells;

a plurality of bit lines disposed above the plane along a second direction crossing a first direction and extending in the first direction;

a plurality of wirings provided above the bit lines along the second direction and extending in the first direction while being bent in a zigzag shape; and

a plurality of contact pads respectively coupled to the convex portions of the wiring at the edge of the cell region.

11. The semiconductor memory device according to claim 10, wherein the convex portion of the wiring at the edge of the cell region is exposed outside the cell region, and the contact pad is provided outside the cell region.

12. The semiconductor memory device according to claim 10,

wherein the plurality of wirings include a plurality of first wirings and a plurality of second wirings alternately arranged along the second direction, and

wherein the contact pad is coupled to a first wiring located at the edge of the cell region.

13. The semiconductor memory device according to claim 12, further comprising:

a source plate supporting the plane and electrically coupled to the second wiring;

a logic circuit disposed above the substrate and below the source plate; and

a plurality of contacts electrically coupling the plurality of contact pads and the logic circuit.

14. A semiconductor memory device, the semiconductor memory device comprising:

a plurality of planes, each plane including a plurality of memory cells;

a plurality of bit lines disposed above the plane along a second direction crossing a first direction and extending in the first direction; and

a plurality of first wirings and a plurality of second wirings alternately disposed above the bit lines along the second direction and extending in the first direction while being bent in a zigzag shape.

15. The semiconductor memory device according to claim 14,

wherein the plurality of planes include a first plane and a second plane disposed along the second direction, and

wherein the semiconductor memory device further comprises:

a plurality of contact pads respectively coupled to a protrusion of a first wiring disposed at an edge of a first cell region where the first plane is located and a protrusion of a first wiring disposed at an edge of a second cell region where the second plane is located.

16. The semiconductor memory device according to claim 15, wherein the convex portion of the first wiring located at the edge of the first cell region and the edge of the second cell region is exposed to a spacing region between the first cell region and the second cell region, and the contact pad is provided in the spacing region.

17. The semiconductor memory device according to claim 16, further comprising:

a source plate supporting the plane and electrically coupled to the second wiring;

a logic circuit disposed above the substrate and below the source plate; and

a plurality of contacts disposed in the spaced-apart area and electrically coupling the contact pads and the logic circuit.

18. The semiconductor memory device according to claim 16, further comprising:

a third wiring provided at the same layer as the first wiring and the second wiring in the spaced-apart region and extending in the first direction.

19. The semiconductor memory device according to claim 14,

wherein the plurality of planes are arranged along the first direction and the second direction, and

wherein a plurality of first wirings located above a plane disposed along the first direction are electrically coupled to each other, and a plurality of second wirings located above different planes are electrically isolated from each other.

20. The semiconductor memory device according to claim 19, further comprising:

a coupling wiring line which is located between the plurality of planes disposed along the first direction and is commonly coupled with the first wiring line located above the plurality of planes disposed along the first direction.

Technical Field

Various embodiments of the present invention relate generally to semiconductor memory devices, and more particularly, to a semiconductor memory device having an improved wiring structure, which allows for enhanced integration and performance and lower power consumption.

Background

In recent years, as the versatility and capacity of information communication apparatuses employing memory devices increase, the memory devices tend to have larger capacities and higher integration degrees. As the size of memory cells is reduced in order to achieve higher integration, the structure of operating circuits and wiring included in the memory device for operation and electrical coupling of the memory device becomes more complex and a potential bottleneck in efforts to improve the memory device. Accordingly, a memory device having an improved integration and excellent electrical characteristics due to an improved wiring structure would be highly desirable in the art.

Disclosure of Invention

Various embodiments of the present invention provide a semiconductor memory device having an improved wiring structure, which allows for enhanced integration and performance, and lower power consumption.

In an embodiment, a semiconductor memory device may include: a plurality of bit lines disposed over the memory cells along a second direction crossing the first direction; and a plurality of first wirings and a plurality of second wirings alternately disposed above the bit lines along the second direction and extending in the first direction while being bent in a zigzag shape.

In an embodiment, a semiconductor memory device may include: a plane disposed in the cell region and including a plurality of memory cells; a plurality of bit lines disposed above the plane along a second direction crossing the first direction and extending in the first direction; a plurality of wirings provided above the bit lines along the second direction and extending in the first direction while being bent in a zigzag shape; and a plurality of contact pads respectively coupled to the convex portions of the wirings at the edge of the cell region.

In an embodiment, a semiconductor memory device may include: a plurality of planes each including a plurality of memory cells; a plurality of bit lines disposed above the plane along a second direction crossing the first direction and extending in the first direction; and a plurality of first wirings and a plurality of second wirings alternately disposed above the bit lines along the second direction and extending in the first direction while being bent in a zigzag shape.

In an embodiment, a semiconductor memory device includes: a plurality of bit lines disposed over the memory cells; and a plurality of first wirings and a plurality of second wirings alternately disposed above the bit lines along the second direction and extending in the first direction while being bent in a zigzag shape. Each of the first wiring and the second wiring includes a crack-suppressing structure.

These and other features and advantages of the present invention will become apparent to those skilled in the art from the following detailed description of exemplary embodiments, which, taken in conjunction with the annexed drawings, discloses the present invention.

Drawings

Fig. 1 is a block diagram showing an exemplary configuration of a semiconductor memory device according to an embodiment of the present disclosure.

Fig. 2 is an equivalent circuit diagram showing an exemplary configuration of one of the plurality of memory blocks shown in fig. 1.

Fig. 3 is a layout diagram schematically showing an exemplary configuration of the semiconductor memory apparatus shown in fig. 1.

Fig. 4 is a perspective view schematically showing an exemplary configuration of the semiconductor memory device shown in fig. 3.

Fig. 5 is a cross-sectional view showing an exemplary configuration of a semiconductor memory device according to an embodiment of the present disclosure.

Fig. 6 is a top view schematically showing an exemplary configuration of a semiconductor memory device according to an embodiment of the present disclosure.

Fig. 7 is a top view showing an exemplary configuration of a layout relationship between bit lines and first and second wirings.

Fig. 8 is a plan view showing an exemplary configuration of the structures of the first wiring and the second wiring.

Fig. 9 is an enlarged plan view illustrating a portion a of fig. 6.

Fig. 10 is a top view showing an exemplary configuration of first and second wirings of a semiconductor memory device according to an embodiment of the present disclosure.

Fig. 11 is a top view schematically showing an exemplary configuration of a semiconductor memory device according to an embodiment of the present disclosure.

Fig. 12 is a diagram schematically showing an exemplary configuration of a memory system including a semiconductor memory device according to an embodiment of the present disclosure.

Fig. 13 is a block diagram schematically showing an exemplary configuration of a computing system including a semiconductor memory device according to an embodiment of the present disclosure.

Detailed Description

Hereinafter, a semiconductor memory device will be described below with reference to the accompanying drawings by various examples of embodiments.

The figures are schematic illustrations of various embodiments (and intermediate structures). Variations from the illustrated configurations and shapes, for example, due to manufacturing techniques and/or tolerances, are therefore contemplated. Accordingly, the described embodiments should not be construed as limited to the particular configurations and shapes shown herein but are to include deviations in configurations and shapes that do not depart from the spirit and scope of the invention as defined in the appended claims.

The present invention is described herein with reference to cross-sectional and/or plan views of idealized embodiments of the present invention. However, the embodiments of the present invention should not be construed as limiting the concept of the present invention. Although a few embodiments of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another. Accordingly, a first element described below may also be referred to as a second element or a third element without departing from the spirit and scope of the present invention.

It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly on, connected or coupled to the other element or one or more intervening elements may be present. In addition, it will also be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It will be further understood that the terms "comprises" and "comprising," when used in this specification, specify the presence of stated elements, but do not preclude the presence or addition of one or more other elements. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs in view of this disclosure.

It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the present disclosure and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be practiced without some or all of these specific details. In other instances, well known process structures and/or processes have not been described in detail in order to not unnecessarily obscure the present invention.

It is also noted that, in some instances, features or elements described in connection with one embodiment may be used alone or in combination with other features or elements of another embodiment unless expressly stated otherwise, as would be apparent to one skilled in the art.

Hereinafter, in the drawings, a direction perpendicular to the top surface of the substrate is defined as a third direction TD, and two directions parallel to the top surface of the substrate and crossing each other are defined as a first direction FD and a second direction SD, respectively. The substrate may correspond to a single-layer or multi-layer substrate. The second direction SD may correspond to an extending direction of the word lines, and the first direction FD may correspond to an extending direction of the bit lines. The first direction FD and the second direction SD may substantially perpendicularly cross each other. In the drawings, the direction indicated by an arrow and the direction opposite thereto represent the same direction.

Fig. 1 is a block diagram showing an exemplary configuration of a semiconductor memory device according to an embodiment of the present disclosure.

Referring to fig. 1, a semiconductor memory device 100 according to an embodiment may include first and second planes 110-1 and 110-2, first and second row decoders 120-1 and 120-2, first and second page buffer circuits 130-1 and 130-2, and a peripheral circuit 140.

The first plane 110-1 and the second plane 110-2 may each include a plurality of memory cells having states corresponding to data stored therein. The memory cells may be accessed by word lines and bit lines. The memory cell may be a volatile memory cell that loses data stored therein in the event of power interruption, or may be a nonvolatile memory cell that retains data stored therein even if power is interrupted.

Although it is described below that the semiconductor memory device 100 is a vertical NAND flash memory device, it will be understood that the technical spirit of the present disclosure is not limited thereto.

Each of the first plane 110-1 and the second plane 110-2 may include a plurality of memory blocks BLK1 through BLKz (z is a natural number of 2 or more). Although not shown, each of the memory blocks BLK1 through BLKz may include a plurality of cell strings. The cell string may include at least one drain select transistor, a plurality of memory cells, and at least one source select transistor coupled in series.

The first plane 110-1 may be coupled to the first row decoder 120-1 by row lines LRL1 through LRLz. The second plane 110-2 may be coupled to the second row decoder 120-2 by row lines LRL1 through LRLz. An ith (i is a natural number of z or less) memory block BLKi included in the first plane 110-1 or the second plane 110-2 may be coupled to the corresponding row decoder 120-1 or 120-2 through a row line LRLi. The row lines RL may include one or more drain select lines, a plurality of word lines, and one or more source select lines. An ith memory block BLKi may be defined as one of memory blocks BLK1 through BLKz included in the first plane 110-1 and the second plane 110-2, and a row line LRLi may be defined as a row line coupled to the ith memory block BLKi.

The first plane 110-1 may be coupled to the first page buffer circuit 130-1 through a bit line BL. The second plane 110-2 may be coupled to the second page buffer circuit 130-2 through a bit line BL.

The first plane 110-1 and the second plane 110-2 may be controlled in their operations (e.g., program operation and read operation) independently of each other by the first page buffer circuit 130-1 and the second page buffer circuit 130-2. By thus controlling independently of each other, the first plane 110-1 and the second plane 110-2 may perform specific operations in parallel or individually. For example, in the case where the size of each page of the first and second planes 110-1 and 110-2 is 16KB, the first and second planes 110-1 and 110-2 may operate in parallel and process 32KB of data, or only one of the first and second planes 110-1 and 110-2 may operate and process 16KB of data.

In response to the row address X _ a1 provided from the peripheral circuit 140, the first row decoder 120-1 may select any one of the memory blocks BLK1 through BLKz included in the first plane 110-1. First row decoder 120-1 may transfer an operating voltage X _ V1 provided from peripheral circuitry 140 to a local row line LRLi coupled to the selected memory block. The second row decoder 120-2 may also operate in a similar manner as the first row decoder 120-1.

The first and second page buffer circuits 130-1 and 130-2 may include a plurality of page buffers PB respectively coupled to the bit lines BL.

The first page buffer circuit 130-1 may receive the first page buffer control signal PB _ C1 from the peripheral circuit 140, and may transmit the data signal D1 to the peripheral circuit 140 and receive the data signal D1 from the peripheral circuit 140. The first page buffer circuit 130-1 may control the bit line BL arranged in the first plane 110-1 in response to a first page buffer control signal PB _ C1. For example, the first page buffer circuit 130-1 may detect data stored in the memory cells of the first plane 110-1 by sensing signals of the bit lines BL of the first plane 110-1 in response to the first page buffer control signal PB _ C1, and may transmit a data signal D1 to the peripheral circuit 140 according to the detected data. The first page buffer circuit 130-1 may apply a signal to the bit line BL based on the data signal D1 received from the peripheral circuit 140 in response to the first page buffer control circuit PB _ C1, and thus, data may be written in the memory cells of the first plane 110-1. The first page buffer circuit 130-1 may write data in or read data from memory cells coupled to word lines enabled by the first row decoder 120-1. The second page buffer circuit 130-2 may also operate in a similar manner to the first page buffer circuit 130-1.

The peripheral circuit 140 may receive a command signal CMD, an address signal ADD, and a control signal CTRL from the outside of the semiconductor memory device 100, and may transmit and receive DATA to and from a device (e.g., a memory controller) outside the semiconductor memory device 100. The peripheral circuit 140 may output signals (e.g., row addresses X _ a1 and X _ a2, page buffer control signals PB _ C1 and PB _ C2, etc.) for writing data in the first plane 110-1 and the second plane 110-2 or reading data from the first plane 110-1 and the second plane 110-2 based on the command signals CMD, the address signals ADD, and the control signals CTRL. The peripheral circuit 140 may generate various voltages (including the operation voltages X _ V1 and X _ V2) required in the semiconductor memory device 100.

Hereinafter, in the drawings, two directions parallel to the top surface of the substrate and crossing each other are defined as a first direction FD and a second direction SD, respectively, and a direction perpendicularly projected from the top surface of the substrate is defined as a third direction TD. The first direction FD may correspond to an extending direction of bit lines or an arranging direction of row lines, and the second direction SD may correspond to an arranging direction of bit lines or an extending direction of row lines. The first direction FD and the second direction SD may substantially perpendicularly cross each other. In the drawings, the direction indicated by an arrow and the direction opposite thereto represent the same direction.

Fig. 2 is an equivalent circuit diagram showing an exemplary configuration of one memory block BLKi among the memory blocks shown in fig. 1.

Referring to fig. 2, the memory block BLKi may include a plurality of cell strings CSTR coupled between a plurality of bit lines BL and a common source line CSL.

The bit lines BL may extend in the first direction FD and be arranged along the second direction SD. A plurality of cell strings CSTR may be coupled to each bit line BL in parallel. The cell strings CSTR may be commonly coupled to a common source line CSL. That is, a plurality of cell strings CSTR may be disposed between a plurality of bit lines BL and one common source line CSL.

Each cell string CSTR may include a drain select transistor DST coupled to the bit line BL, a source select transistor SST coupled to the common source line CSL, and a plurality of memory cells MC coupled between the drain select transistor DST and the source select transistor SST. The drain select transistor DST, the memory cell MC, and the source select transistor SST may be coupled in series along the third direction TD.

The drain select line DSL, the plurality of word lines WL, and the source select line SSL extending in the second direction SD may be stacked between the bit line BL and the common source line CSL along the third direction TD. The drain select lines DSL may be respectively coupled to gates of the corresponding drain select transistors DST. Word lines WL may be respectively coupled to gates of corresponding memory cells MC. The source select line SSL may be coupled to the gate of the source select transistor SST.

Fig. 3 is a layout diagram schematically showing an exemplary configuration of the semiconductor memory device shown in fig. 1, and fig. 4 is a perspective view schematically showing an exemplary configuration of the semiconductor memory device shown in fig. 3.

Referring to fig. 3 and 4, the memory structure C may include a first plane 110-1 and a second plane 110-2. Logic structure P may include first and second row decoders 120-1 and 120-2, first and second page buffer circuits 130-1 and 130-2, and peripheral circuit 140. At least a portion of the logic structure P may be disposed below the memory structure C. That is, the semiconductor memory device 100 may have a PUC (lower periphery of cell) structure. In the embodiment described with reference to fig. 3 and 4, the first and second page buffer circuits 130-1 and 130-2 of the logic structure P and the peripheral circuit 140 are shown to be disposed under the memory structure C.

The first and second row decoders 120-1 and 120-2, the first and second page buffer circuits 130-1 and 130-2, and the peripheral circuit 140 may be disposed on the substrate 10, and the first and second planes 110-1 and 110-2 may be disposed on the source board 11.

The semiconductor memory device 100 may include first and second cell regions CR1 and CR2, a spacing region IR, and first and second peripheral regions PR1 and PR 2. The first and second cell regions CR1 and CR2 may be arranged along the second direction SD. The spacing region IR may be disposed between the first cell region CR1 and the second cell region CR 2. The first peripheral region PR1 may be disposed at the periphery of the substrate 10 adjacent to the first cell region CR1 in the second direction SD, and the second peripheral region PR2 may be disposed at the periphery of the substrate 10 adjacent to the second cell region CR2 in the second direction SD.

The first plane 110-1 may be disposed on the source plate 11 of the first cell region CR1, and the second plane 110-2 may be disposed on the source plate 11 of the second cell region CR 2.

Input/output PADs PAD, which are external contacts for the semiconductor memory device 100 electrically coupled with an external device, may be arranged at an edge of the substrate 10 along the second direction SD. Although not shown, the input/output PAD may be electrically coupled with the peripheral circuit 140 through a plurality of wirings.

The peripheral circuit 140 may be disposed adjacent to the input/output PAD in the first direction FD. At least a portion of the peripheral circuit 140 may overlap the first plane 110-1 and the second plane 110-2 in the third direction TD.

The first page buffer circuit 130-1 may be disposed in the first cell region CR1, and may overlap the first plane 110-1 in the third direction TD. The second page buffer circuit 130-2 may be disposed in the second cell region CR2, and may overlap the second plane 110-2 in the third direction TD.

The first and second page buffer circuits 130-1 and 130-2 may be arranged to have a shape extending along the second direction SD that is an arrangement direction of the bit lines BL. Elements included in the respective first and second page buffer circuits 130-1 and 130-2, that is, the page buffer PB (see fig. 1) may be arranged along the second direction SD. The first page buffer circuit 130-1 may be arranged to have substantially the same length as the first plane 110-1 in the second direction SD, and the second page buffer circuit 130-2 may be disposed to have substantially the same length as the second plane 110-2 in the second direction SD.

The first row decoder 120-1 may be arranged to have a shape extending along the first direction FD, which is an arrangement direction of the row lines RL, in the first peripheral region PR1, and the second row decoder 120-2 may be arranged to have a shape extending along the first direction FD in the second peripheral region PR 2.

Fig. 5 is a cross-sectional view showing an exemplary configuration of a part of a semiconductor memory device according to an embodiment.

Referring to fig. 5, the substrate 10 may be a semiconductor substrate having a first conductivity type (e.g., P-type conductivity). The semiconductor substrate may be formed of or include at least one selected from the group consisting of a single crystal silicon layer, an SOI (silicon on insulator), a silicon layer formed on a silicon germanium (SiGe) layer, a single crystal silicon layer formed on a dielectric layer, and a polycrystalline silicon layer formed on a dielectric layer.

The logic structure P may be disposed on the substrate 10. As described above with reference to fig. 3 and 4, the logic structure P may include logic circuits such as the first and second row decoders 120-1 and 120-2, the first and second page buffer circuits 130-1 and 130-2, and the peripheral circuit 140. The logic circuit may include a plurality of logic transistors TR. The logic transistor TR may be a planar transistor. Although fig. 5 shows a case where the logic transistor is a planar transistor, the form of the logic transistor is not limited thereto. For example, the logic transistor TR may be a vertical transistor. The logic transistor TR may be disposed in an active region defined by the isolation layer 10A. The logic structure P may include a plurality of bottom wirings UM electrically coupled to the logic circuit. The bottom wiring UM may be electrically coupled to the logic circuit through the bottom contact UCT. The logic structure P may include a bottom dielectric layer covering the logic circuit, the bottom wiring UM, and the bottom contact UCT. The bottom dielectric layer may be formed of or include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and any combination thereof. The bottom dielectric layer may be a single layer or multiple layers. The bottom dielectric layer is shown to be composed of the first to third bottom dielectric layers 21, 22 and 23 in the embodiment of fig. 5, however, the present invention may not be limited thereto.

The source plate 11 may be disposed on the third bottom dielectric layer 23. The source plate 11 may be formed of polysilicon. Unlike the substrate 10, which may use a single crystalline silicon substrate, since the source plate 11 should be formed on the third bottom dielectric layer 23, the source plate 11 may be formed of polycrystalline silicon. The source plate 11 may not be disposed in the spacing region IR. In other words, the source plate 11 may expose the third bottom dielectric layer 23 of the spacer region IR.

The memory structure C may be disposed on the source plate 11. As described above with reference to fig. 3 and 4, the memory structure C may include a first plane 110-1 and a second plane 110-2. The first plane 110-1 may be disposed on the source plate 11 of the first cell region CR1, and the second plane 110-2 may be disposed on the source plate 11 of the second cell region CR 2.

Each of the first plane 110-1 and the second plane 110-2 may include a stack structure ST and a plurality of channel structures CH penetrating the stack structure ST. The stack structure ST may include a plurality of gate layers 30 and a plurality of dielectric layers 32 that are alternately stacked. At least one lowermost layer among the gate layers 30 may be used as a source select line. At least one uppermost layer among the gate layer 30 may serve as a drain select line. The gate layer 30 between the source select line and the drain select line may function as a word line.

Channel structure CH may be coupled to source plate 11 by passing through gate layer 30 and dielectric layer 32. Each channel structure CH may include a channel layer 40 and a gate dielectric layer 42. The channel layer 40 may include polycrystalline silicon or monocrystalline silicon, and may include a P-type impurity such as boron (B) in some regions. The channel layer 40 may have a pillar or solid cylindrical shape completely filling up to the center thereof. Although not shown, in a variation of this embodiment, the channel layer 40 may have a shape of a tube with a central region opened. In this case, a buried dielectric layer may be formed in the open central region of the channel layer 40.

The gate dielectric layer 42 may have the shape of a straw or cylindrical shell surrounding the outer wall of the channel layer 40. Although not shown, the gate dielectric layer 42 may include a tunnel dielectric layer, a charge storage layer, and a blocking layer, which are sequentially stacked from an outer wall of the channel layer 40. The tunnel dielectric layer may be formed of or include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, or tantalum oxide. The charge storage layer may be formed of or include silicon nitride, boron nitride, silicon boron nitride, or polysilicon doped with impurities. The barrier layer may be formed of or include a single layer or a stacked layer of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, and tantalum oxide. In some embodiments, the gate dielectric layer 42 may have an ONO (oxide-nitride-oxide) stack structure in which an oxide layer, a nitride layer, and an oxide layer are sequentially stacked. The source select transistor may be formed where the source select line surrounds the channel structure CH, the memory cell may be formed where the word line surrounds the channel structure CH, and the drain select transistor may be formed where the drain select line surrounds the channel structure CH. With the above structure, a plurality of cell strings may be provided, each cell string including a source selection transistor, a memory cell, and a drain selection transistor provided along each channel structure CH.

The first top dielectric layer 51 may be disposed in the spacing region IR to cover the top surface of the third bottom dielectric layer 23 and the side surfaces of the source plate 11. The second top dielectric layer 52 may be disposed on the first top dielectric layer 51 and cover a side surface of the stack structure ST. A third top dielectric layer 53 may be disposed on the stack structure ST and the second top dielectric layer 52. A plurality of bit lines BL may be disposed on the third top dielectric layer 53 of the first and second cell regions CR1 and CR 2.

The bit lines BL may extend along the first direction FD and may be arranged at regular intervals along the second direction SD. A bit line contact BLC may be formed in the third top dielectric layer 53 under the bit line BL to electrically couple the bit line BL and the channel structure CH. The channel structures CH arranged in a row along the first direction FD may be electrically coupled to a single bit line BL. A fourth top dielectric layer 54 may be formed on the third top dielectric layer 53 to cover the bit lines BL. The first to fourth top dielectric layers 51 to 54 may be formed of or include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and any combination thereof.

A plurality of wirings M1, M2, and M3 may be disposed on the fourth top dielectric layer 54.

The wirings M1, M2, and M3 may include first and second wirings M1 and M2 disposed in the first and second cell regions CR1 and CR2, and a third wiring M3 disposed in the spacing region IR. The first and second wirings M1 and M2 may be alternately disposed in the first and second cell regions CR1 and CR2 along the second direction SD.

The voltage applied to the first wiring M1 and the voltage applied to the second wiring M2 may be different from each other. The voltage applied to the third wiring M3 may be different from the voltage applied to the first wiring M1 and the voltage applied to the second wiring M2. For example, a ground Voltage (VSS) may be applied to the first wiring M1, a source Voltage (VSL) may be applied to the second wiring M2, and a power supply Voltage (VCC) may be applied to the third wiring M3. The first wiring M1 may function to transmit the ground Voltage (VSS) to the logic circuit, and the second wiring M2 may function to transmit the source Voltage (VSL) to the source plate 11. The third wiring M3 may function to transmit the power supply Voltage (VCC) to the logic circuit.

The first and second wirings M1 and M2 disposed in the first and second cell regions CR1 and CR2 may overlap the underlying bit line BL in the third direction TD, and may cause a coupling capacitance where the first and second wirings M1 and M2 and the bit line BL overlap each other.

The area where the bit line BL overlaps the first wiring M1 may be different for each bit line BL. Similarly, the area where the bit line BL overlaps the second wiring M2 may be different for each bit line BL. Since the bit line BL has a coupling capacitance proportional to the overlapping area with the first wiring M1 or/and the second wiring M2, in the case where the overlapping areas with the first wiring M1 or/and the second wiring M2 are different from each other, deviation of the coupling capacitance occurs between the bit lines BL, and thus, variation in the distribution of memory cells coupled to the bit line BL may increase.

If the first and second wirings M1 and M2 are disposed outside the first and second cell regions CR1 and CR2, since the first and second wirings M1 and M2 do not overlap the bit lines BL, variation in the distribution of the memory cells due to deviation in coupling capacitance between the bit lines BL can be suppressed. In this case, however, since the arrangement of the first wiring M1 and the second wiring M2 requires an additional area, the size of the semiconductor memory device 100 increases.

Therefore, in the described embodiments, a semiconductor memory device capable of suppressing variation in the distribution of memory cells by reducing the deviation of the coupling capacitance between bit lines without increasing the size can be provided.

Fig. 6 is a plan view schematically showing an exemplary configuration of a semiconductor memory device according to an embodiment, fig. 7 is a plan view showing an exemplary configuration of a layout relationship between bit lines and first and second wirings, fig. 8 is a plan view showing an exemplary configuration of structures of the first and second wirings, and fig. 9 is an enlarged plan view showing a portion a of fig. 6.

Referring to fig. 6 and 7, the first and second wirings M1 and M2 may be alternately disposed in the first and second cell regions CR1 and CR2 along the second direction SD. The first wiring M1 and the second wiring M2 may extend in the first direction FD that is an extending direction of the bit line BL while being bent in a zigzag shape.

The first and second wirings M1 and M2 may be formed by a photolithography process and an etching process. In the case where the bending angle θ of the first wiring M1 and the second wiring M2 is small, pattern distortion may occur by an Optical Proximity Effect (OPE) in a photolithography process. Although the pattern distortion may be corrected to some extent using Optical Proximity Correction (OPC), if the bending angle θ of the first wiring M1 and the second wiring M2 is smaller than the threshold reference capable of correcting the pattern distortion by Optical Proximity Correction (OPC), the pattern distortion cannot be corrected even by OPC. Therefore, the bending angle θ of the first wiring M1 and the second wiring M2 should have a value equal to or greater than a threshold reference capable of correcting pattern distortion by OPC. The threshold reference may be 90 degrees.

The width of the first wiring M1 in the second direction SD may be constant as the first width W1, and the width of the second wiring M2 in the second direction SD may be constant as the second width W2. Although it is shown in the present embodiment that the second width W2 is smaller than the first width W1, it is to be noted that the present disclosure is not limited thereto. The second width W2 may be the same as the first width W1, or may be greater than the first width W1. The first width W1 and the second width W2 may vary depending on the desired specification.

Referring to fig. 8, each of the first wirings M1 may have a pair of side surfaces S1 and S2 facing away from each other. One side surface S1 of each first wiring M1 may have a zigzag shape in which a plurality of first convex portions Pa1 and a plurality of first concave portions Pb1 are alternately repeated, and the other side surface S2 may have a zigzag shape in which a plurality of second concave portions Pb2 and a plurality of second convex portions Pa2 are alternately repeated. The first protrusion Pa1 of the one side surface S1 and the second recess Pb2 of the other side surface S2 may form a pair while facing away from each other in the second direction SD, and the first recess Pb1 of the one side surface S1 and the second protrusion Pa2 of the other side surface S2 may form a pair while facing away from each other in the second direction SD. Each of the first and second protrusions Pa1 and Pa2 and the first and second recesses Pb1 and Pb2 may have no tip, but a rounded end. Unlike the present embodiment, in the case where each of the first and second convex portions Pa1 and Pa2 and the first and second concave portions Pb1 and Pb2 has a tip, since an electric field is concentrated in the first and second convex portions Pa1 and Pa2 and the first and second concave portions Pb1 and Pb2, electrical characteristics may be deteriorated. In the present embodiment, since each of the first and second convex portions Pa1 and Pa2 and the first and second concave portions Pb1 and Pb2 has a rounded end, an electric field concentration phenomenon can be suppressed.

Each of the first wirings M1 may be formed such that the first convex Pa1 on one side surface S1 thereof is aligned in a row along the first direction FD with the first concave Pb1 of the adjacent first wiring M1 facing the one side surface S1. That is, the first convex portion Pa1 of the first wiring M1 and the first concave portion Pb1 of the adjacent first wiring M1 facing the one side surface S1 of the first wiring M1 may be aligned on the first virtual straight line L1 extending along the first direction FD.

Each of the first wirings M1 may be formed such that the second protrusion Pa2 on the other side surface S2 thereof is aligned in a row along the first direction FD with the second recess Pb2 of the adjacent first wiring M1 facing the other side surface S2. That is, the second protrusion Pa2 of the first wiring M1 and the second recess Pb2 of the adjacent first wiring M1 facing the other side surface S2 of the first wiring M1 may be aligned on the second virtual straight line L2 extending along the first direction FD. The second wiring M2 may be disposed between the first wirings M1 side by side with the first wiring M1, and may be formed in substantially the same shape as the first wiring M1.

Referring again to fig. 6, the first wiring M1 disposed above the first plane 110-1 may be coupled in parallel to the first common wiring CM1, and the first wiring M1 disposed above the second plane 110-2 may be coupled in parallel to the second common wiring CM 2. The first and second common wirings CM1 and CM2 may be disposed between the PADs PAD and the first and second planes 110-1 and 110-2, and each may be electrically coupled to at least one of the plurality of PADs PAD. The PAD electrically coupled to the first common wiring CM1 and the second common wiring CM2 may be an input/output PAD for a ground voltage.

Referring to fig. 5, 6, and 9, the convex portion of the first wiring M1 disposed at the edge of the first and second cell regions CR1 and CR2 among the first wiring M1 may be exposed to the outside of the first and second cell regions CR1 and CR2 (e.g., exposed to the spacing region IR between the first and second cell regions CR1 and CR 2). The contact pads CP may be disposed in the spacing region IR. The contact pads CP may be coupled to the convex portions of the first wiring M1 disposed at the edges of the first and second cell regions CR1 and CR2, respectively. The contact pad CP may be electrically coupled to the underlying logic structure P by an electrical path defined in the spacing region IR.

For example, as shown in fig. 5, the contact pad CP may be coupled to a wiring TM1 formed on the third top dielectric layer 53 through a contact CNT1 of the fourth top dielectric layer 54 that passes through the spacing region IR. The wiring TM1 may be electrically coupled to the bottom wiring UM of the logic structure P through the contact CNT2 passing through the first top dielectric layer 51 to the third top dielectric layer 53 and the third bottom dielectric layer 23 of the spacing region IR.

In the present embodiment configured as described above, by forming the first wiring M1 and the second wiring M2 to be bent in a zigzag shape, the deviation of the area where the bit line BL overlaps with the first wiring M1 and the deviation of the area where the bit line BL overlaps with the second wiring M2 can be reduced. Due to this fact, since the deviation of the coupling capacitance between the bit lines BL is reduced, the variation in the distribution of the memory cells coupled to the bit lines BL can be suppressed.

Further, by forming the first wiring M1 to be bent in a zigzag shape and providing the contact pad at the convex portion of the first wiring M1 located at the edge of the cell regions CR1 and CR2, the number of electrical paths connecting the first wiring M1 and the underlying logic circuit can be reduced. Accordingly, a jump of a voltage to be transmitted to the logic circuit can be suppressed, and the operation characteristics of the semiconductor memory device can be improved.

Fig. 10 is a top view schematically showing an exemplary configuration of first and second wirings of a semiconductor memory device according to an embodiment of the present disclosure.

Referring to fig. 10, each of the first and second wirings M1 and M2 may have a crack-inhibiting structure. In detail, the first slits X1 may be formed in each of the first wirings M1. The first slit X1 may extend in the first direction FD as the extending direction of the bit line BL while being bent in a zigzag shape. Each of the first wirings M1 may be divided into a plurality of first sub-wirings SM1 by the first slit X1. The widths of the first sub-wirings SM1 measured in the second direction SD may be the same as each other. In this case, the width of the first sub-wiring SM1 measured in the second direction SD may have a size less than half of the width of the first wiring M1 (W1 of fig. 7) measured in the second direction SD.

Similar to the first wiring M1, second slits X2 may be formed in each of the second wirings M2. The second slit X2 may extend in the first direction FD as the extending direction of the bit line BL while being bent in a zigzag shape. Each of the second wirings M2 may be divided into a plurality of second sub-wirings SM2 by the second slits X2. The widths of the second sub-wirings SM2 measured in the second direction SD may be the same as each other. In this case, the width of the second sub-wiring SM2 measured in the second direction SD may have a size less than half of the width of the second wiring M2 (W2 of fig. 7) measured in the second direction SD.

After being manufactured on a wafer, the semiconductor memory device may be commercialized through an individualization process and a packaging process. In the individualization process and the packaging process, stress may be applied to the semiconductor memory device, and cracks may occur in the first wiring M1 and the second wiring M2 due to the stress. The slits X1 and X2 formed in the first wiring M1 and the second wiring M2 can suppress propagation of cracks by absorbing and/or reflecting stress. That is, since the boundary of the crack is defined by the slits X1 and X2, the propagation of the crack can be suppressed.

According to the present embodiment, since the propagation of cracks is suppressed by the slits X1 and X2 defined in the first wiring M1 and the second wiring M2, the open failure of the first wiring M1 and the second wiring M2 can be reduced.

Fig. 11 is a top view schematically showing an exemplary configuration of a semiconductor memory device according to an embodiment of the present disclosure.

Referring to fig. 11, planes 210-1 to 210-4 may be arranged in a2 × 2 matrix along a first direction FD and a second direction SD. Although it is shown in the present embodiment that the number of planes arranged along the first direction FD is 2, it is to be noted that the present disclosure is not limited thereto. The number of planes arranged along the first direction FD may be 3 or more.

The first wire M1 may be used to carry signals to be provided in common to the planes 210-1 to 210-4. The second wiring M2 may be used to carry signals to be provided separately to each of the planes 210-1 through 210-4. For example, the first wiring M1 may be used to transmit a ground Voltage (VSS), and the second wiring M2 may be used to transmit a source Voltage (VSL).

The first wirings M1 disposed on the planes 210-1 and 210-3 arranged in a row along the first direction FD may be electrically coupled to each other, and the first wirings M1 disposed on the planes 210-2 and 210-4 arranged in a row along the first direction FD may be electrically coupled to each other. The second wirings M2 disposed on different planes 210-1 to 210-4 may be electrically isolated from each other.

The third coupling wiring CM3 may be disposed between the first plane 210-1 and the third plane 210-3 arranged in a row along the first direction FD, and the first wirings M1 located on the first plane 210-1 and the third plane 210-3 may be commonly coupled to the third coupling wiring CM 3. Similarly, the fourth coupling wiring CM4 may be disposed between the second plane 210-2 and the fourth plane 210-4 arranged in a row along the first direction FD, and the first wirings M1 located on the second plane 210-2 and the fourth plane 210-4 may be commonly coupled to the fourth coupling wiring CM 4.

Fig. 12 is a simplified block diagram schematically illustrating a memory system including a semiconductor memory device according to an embodiment of the present invention.

Referring to fig. 12, a memory system 600 may include a semiconductor memory device 610 and a memory controller 620.

The semiconductor memory device 610 may include a semiconductor memory device according to an embodiment of the present invention as described above, and may operate in the above-described manner. The memory controller 620 may control the semiconductor memory device 610. For example, the combination of the semiconductor memory device 610 and the memory controller 620 may be configured as a memory card or a Solid State Disk (SSD). The memory controller 620 may include an SRAM 621, a Central Processing Unit (CPU)622, a host interface 623, an ECC block 624, and a memory interface 625.

The SRAM 621 can be used as a working memory of the CPU 622. The host interface 623 may include data exchange protocols for hosts that may interface with the memory system 600.

The ECC block 624 may detect and correct errors included in data read from the semiconductor memory device 610.

The memory interface 625 may interface with the semiconductor memory device 610. The CPU 622 can perform general control operations for data exchange of the storage controller 620.

Although not shown, it should be apparent to those skilled in the art that the memory system 600 may also be provided with a ROM storing code data for interfacing with a host. The semiconductor memory device 610 may be provided as a multi-chip package composed of a plurality of flash memory chips.

The memory system 600 can be used as a high-reliability storage medium with a low probability of an error occurring. The above-described nonvolatile memory device may be provided for a memory system such as a Solid State Disk (SSD). The storage controller 620 may communicate with an external device (e.g., a host) through one of various interface protocols such as a USB (universal serial bus) protocol, an MMC (multimedia card) protocol, a PCI-E (peripheral component interconnect express) protocol, an SATA (serial advanced technology attachment) protocol, a PATA (parallel advanced technology attachment) protocol, a SCSI (small computer system interface) protocol, an ESDI (enhanced small disk interface) protocol, and an IDE (integrated device electronics) protocol.

Fig. 13 is a simplified block diagram schematically illustrating a computing system including a semiconductor memory device according to an embodiment of the present invention.

Referring to fig. 13, a computing system 700 according to an embodiment may include a memory system 710, a microprocessor (or CPU)720, a RAM 730, a user interface 740, a modem 750 (e.g., a baseband chipset), electrically coupled to a system bus 760. In an embodiment, the computing system 700 may be a mobile device, in which case a battery (not shown) for supplying an operating voltage of the computing system 700 may be additionally provided. Although not shown in the drawings, it should be apparent to those skilled in the art that the computing system 700 may further include an application chipset, a CMOS Image Sensor (CIS), a mobile DRAM, and the like. The memory system 710 may be configured as, for example, an SSD (solid state drive/disk) that uses non-volatile memory to store data. Further by way of example, the memory system 710 may be configured as a flash memory fusion (e.g., NAND or NOR flash memory).

It is to be noted that the above-described embodiments are not realized only by the apparatus and method, but may also be realized by a program that executes functions corresponding to the configuration of each embodiment or a recording medium in which the program is recorded. Such implementation can be easily derived from the description of the above embodiments by those skilled in the art to which the embodiments belong.

Although various embodiments have been described for purposes of illustration, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Cross Reference to Related Applications

The present application claims priority from korean patent application No.10-2018-0095331, filed on 8/16/2018, which is incorporated herein by reference in its entirety.