阅读说明：本技术 嵌入式存储器的单元边界结构、集成电路及其形成方法 (Cell boundary structure of embedded memory, integrated circuit and forming method thereof ) 是由 林孟汉 谢智仁 吴伟成 黄志斌 于 2018-12-17 设计创作，主要内容包括：本申请的各种实施例涉及具有边界侧壁间隔件的嵌入式存储器边界结构及相关形成方法。在一些实施例中,在半导体衬底中形成隔离结构以将存储区与逻辑区分离。在所述存储区上形成存储单元结构,并在所述隔离结构上形成伪结构。形成覆盖所述伪结构的边界侧壁间隔件。保护介质层形成在所述边界侧壁间隔件的顶面上。所述边界侧壁间隔件和所述保护介质层提供平滑的边界侧壁以在所述逻辑器件结构的形成期间不会经受损坏,因此,在使用HKMG技术形成所述逻辑器件结构期间不会吸收高k蚀刻残余物。本发明的实施例还提供了集成电路及其形成方法。(Various embodiments of the present application relate to embedded memory boundary structures having boundary sidewall spacers and related methods of formation. In some embodiments, isolation structures are formed in the semiconductor substrate to separate the memory region from the logic region. And forming a memory cell structure on the memory region, and forming a dummy structure on the isolation structure. Forming a boundary sidewall spacer covering the dummy structure. A protective dielectric layer is formed on a top surface of the boundary sidewall spacer. The boundary sidewall spacers and the protective dielectric layer provide smooth boundary sidewalls to not experience damage during formation of the logic device structure and, therefore, do not absorb high-k etch residues during formation of the logic device structure using the HKMG technique. Embodiments of the invention also provide integrated circuits and methods of forming the same.)

1. A method for forming an Integrated Circuit (IC), the method comprising:

providing a semiconductor substrate comprising a logic region and a storage region;

forming a lower bonding pad layer and an upper bonding pad layer on the logic area;

forming a dummy structure between the logic region and the storage region and defining a dummy sidewall of the dummy structure facing the logic region;

forming a boundary sidewall spacer to cover the dummy structure and to at least partially define a boundary sidewall of the boundary sidewall spacer facing the logic region;

forming a protective dielectric layer on the top surface of the boundary sidewall spacer;

removing the lower bonding pad layer and the upper bonding pad layer in the logic area, wherein the protective medium layer is removed at the same time; and

and forming a logic device structure on the logic area.

2. The method of claim 1, wherein the protective dielectric layer is formed by thermal processing such that an uppermost portion of the boundary sidewall spacer forms the protective dielectric layer.

3. The method of claim 1, wherein the dummy structure is formed by forming and patterning a multi-layer film to form a memory cell structure on the storage region and to form the dummy structure on an isolation structure.

4. The method of claim 3, wherein the boundary sidewall spacers and upper portions of the isolation structures collectively define the boundary sidewall facing the logic region, wherein the boundary sidewall is sloped, and wherein portions of the boundary sidewall defined by the boundary sidewall spacers are continuous with portions of the boundary sidewall defined by the isolation structures.

5. The method of claim 3, further comprising:

a planarization process is performed to form a planar top surface of the isolation structure.

6. The method of claim 3, wherein forming the memory cell structure and the boundary sidewall spacer comprises:

patterning the multilayer film to form the memory cell structure on the memory region;

forming a dummy capping layer to cover the memory cell structure and a remaining portion of the multi-layered film;

performing a first etch of the multilayer film and the dummy cap layer to remove the multilayer film and the dummy cap layer from the logic region and to define the dummy sidewalls on the isolation structures;

forming the boundary sidewall spacers to cover the dummy capping layer, the isolation structure and the logic region, and further to line the dummy sidewalls; and

a second etch is performed on the boundary sidewall spacers to remove horizontal segments of the boundary sidewall spacers and form the boundary sidewall spacers on dummy sidewalls.

7. The method of claim 1, further comprising:

forming a precursor oxide layer with a top surface of the semiconductor substrate and reducing a height of the top surface of the storage region of the semiconductor substrate using the upper pad layer as a mask; and

an upper portion of the precursor oxide layer is removed to form a storage dielectric layer with the precursor oxide layer.

8. The method of claim 1, wherein forming the logic device structure comprises:

forming a conformal high-k dielectric layer over the dummy cap layer, the boundary sidewall spacers, and the logic region;

forming a polysilicon layer on the conformal high-k dielectric layer; and

etching the common high-k dielectric layer and the polysilicon layer to form a polysilicon gate electrode and a high-k gate dielectric layer stacked on the logic region; and

the polysilicon gate electrode is replaced with a metal gate.

9. An Integrated Circuit (IC), the IC comprising:

an isolation structure disposed within a semiconductor substrate and separating a logic region and a storage region of the semiconductor substrate, the isolation structure comprising a dielectric material;

a storage unit provided in the storage area;

a dummy control gate structure disposed on the isolation structure, wherein the dummy control gate structure defines a dummy sidewall facing the logic region and comprising a plurality of different materials;

a boundary sidewall spacer disposed on the isolation structure along the dummy sidewall of the dummy control gate structure, wherein the boundary sidewall spacer and an uppermost portion of the isolation structure collectively define a boundary sidewall, wherein the boundary sidewall faces the logic region and continuously slopes downward toward the logic region; and

a logic device formed on the logic region.

10. A method for forming an Integrated Circuit (IC), the method comprising:

providing a semiconductor substrate comprising a logic region and a storage region;

forming an isolation structure in the semiconductor substrate, the isolation structure separating the logic region and the storage region;

forming a dummy structure on the isolation structure and defining a dummy sidewall of the dummy structure facing the logic region;

forming a boundary sidewall spacer covering the dummy structure and at least partially defining a boundary sidewall of the boundary sidewall spacer facing the logic region;

forming a protective dielectric layer on the top surface of the boundary sidewall spacer;

removing the protective medium layer; and

and forming a logic device structure on the logic area.

Technical Field

The present invention relates generally to semiconductor devices, and more particularly, to integrated circuits and methods of operating the same.

Background

Over the past few decades, the Integrated Circuit (IC) manufacturing industry has experienced exponential growth. As ICs evolve, the functional density (i.e., the number of interconnected devices per chip area) generally increases, while the geometry (i.e., the smallest component (or line) that can be produced) decreases. Some advances in IC development include embedded memory technology and high-k metal gate (HKMG) technology. Embedded memory technology is the integration of a memory device with a logic device on the same semiconductor chip such that the memory device supports the operation of the logic device. The high-K metal gate (HKMG) technique is the fabrication of semiconductor devices using a metal gate electrode and a high-K gate dielectric layer.

Disclosure of Invention

According to an aspect of the invention, there is provided a method for forming an Integrated Circuit (IC), the method comprising: providing a semiconductor substrate comprising a logic region and a storage region; forming a lower bonding pad layer and an upper bonding pad layer on the logic area; forming a dummy structure between the logic region and the storage region and defining a dummy sidewall of the dummy structure facing the logic region; forming a boundary sidewall spacer to cover the dummy structure and to at least partially define a boundary sidewall of the boundary sidewall spacer facing the logic region; forming a protective dielectric layer on the top surface of the boundary sidewall spacer; removing the lower bonding pad layer and the upper bonding pad layer in the logic area, wherein the protective medium layer is removed at the same time; and forming a logic device structure on the logic region.

According to another aspect of the present invention, there is provided an Integrated Circuit (IC) comprising: an isolation structure disposed within a semiconductor substrate and separating a logic region and a storage region of the semiconductor substrate, the isolation structure comprising a dielectric material; a storage unit provided in the storage area; a dummy control gate structure disposed on the isolation structure, wherein the dummy control gate structure defines a dummy sidewall facing the logic region and comprising a plurality of different materials; a boundary sidewall spacer disposed on the isolation structure along the dummy sidewall of the dummy control gate structure, wherein the boundary sidewall spacer and an uppermost portion of the isolation structure collectively define a boundary sidewall, wherein the boundary sidewall faces the logic region and continuously slopes downward toward the logic region; and a logic device formed on the logic region.

According to yet another aspect of the present invention, there is provided a method for forming an Integrated Circuit (IC), the method comprising: providing a semiconductor substrate comprising a logic region and a storage region; forming an isolation structure in the semiconductor substrate, the isolation structure separating the logic region and the storage region; forming a dummy structure on the isolation structure and defining a dummy sidewall of the dummy structure facing the logic region; forming a boundary sidewall spacer covering the dummy structure and at least partially defining a boundary sidewall of the boundary sidewall spacer facing the logic region; forming a protective dielectric layer on the top surface of the boundary sidewall spacer; removing the protective medium layer; and forming a logic device structure on the logic region.

Drawings

Aspects of the invention are better understood by the following detailed description when read in conjunction with the accompanying drawings. It is noted that, in accordance with standard practice in the industry, many of the components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 and 2 illustrate cross-sectional views of some embodiments of an Integrated Circuit (IC) including an embedded memory boundary structure with boundary sidewall spacers.

Fig. 3 illustrates a cross-sectional view of additional embodiments of the IC of fig. 1.

Fig. 4-22 illustrate a series of cross-sectional views of a method for forming an IC including an embedded memory boundary structure with boundary sidewall spacers.

Fig. 23 illustrates a flow diagram of some embodiments of the method of fig. 4-22.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatial relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated for ease of description. Spatially relative terms are intended to encompass different orientations of the device or apparatus in use or operation in addition to the orientation depicted in the figures. The device or apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, the terms "first," "second," "third," "fourth," and the like are merely generic identifiers and thus may be interchanged in various embodiments. For example, while an element (e.g., an opening) may be referred to as a "first" element in some embodiments, the element may be referred to as a "second" element in other embodiments.

According to some methods for fabricating Integrated Circuits (ICs) with embedded memory technology and high-k metal gate (HKMG) technology, a boundary isolation structure is formed to separate a storage region of a semiconductor substrate from a logic region of the semiconductor substrate. The multilayer film is formed to cover the memory and logic areas and the boundary isolation structure. A memory device is formed on the storage region with the multilayer film, and a Dummy Polysilicon (DPO) layer is formed to cover the memory device and the remaining multilayer film. Etching is performed on the multilayer film and the DPO layer, removing the multilayer film and the DPO layer from the logic region such that a remaining portion of the multilayer film and a remaining portion of the DPO layer collectively define a boundary sidewall that is smooth and faces the logic region on the boundary isolation structure. A logic device is formed over the logic region using a high-k gate dielectric layer and a polysilicon gate electrode. Subsequently, an HKMG replacement process is performed to replace the polysilicon gate electrode with a metal gate electrode.

The challenge of the method is that the formation of the logic device involves dielectric material removal and redeposition, which can damage the boundary sidewalls so that they are no longer smooth. For example, an etch process that removes a previous pad dielectric layer or hard mask may result in lateral undercuts, pits, etc. of the boundary sidewalls. Damaging the boundary sidewalls may lead to filling problems, contamination, and/or other reliability problems during subsequent processing. For example, during the formation of logic devices, a high-k dielectric layer and a polysilicon layer may be formed to line the logic region and the boundary sidewalls. The high-k dielectric layer and the polysilicon layer may then be patterned into logic devices. Since the boundary sidewalls are damaged during the third etch, high-k residues may remain on the boundary sidewalls (e.g., within the pits or within the lateral undercuts) after patterning the high-k dielectric layer. High-k residue contamination can change parameters and even cause device failure on the semiconductor substrate. In addition, the high-k residues may contaminate processing tools used in subsequent processing, thereby contaminating other semiconductor substrates subsequently processed by the contaminated processing tools.

In view of the foregoing, various embodiments of the present application are directed to a method for forming an IC that includes an embedded memory boundary structure with boundary sidewall spacers. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a storage region of the semiconductor substrate from a logic region of the semiconductor substrate. The multilayer film is formed and patterned to form a memory cell structure on the memory region and a dummy structure on the isolation structure. A boundary sidewall spacer layer is formed and patterned to form a boundary sidewall spacer overlying the dummy structure. A protective dielectric layer is formed on the top surface of the boundary sidewall spacer. And removing the protective dielectric layer while removing the lower bonding pad layer and the upper bonding pad layer in the logic area. The boundary sidewall spacer protects the dummy structure from damage while forming the logic device structure. The protective dielectric layer protects the boundary isolation structures during the pad removal process and prevents formation of undercuts at the connection points of the boundary sidewall spacers and the boundary isolation structures (as will be described in more detail later, see, for example, the contents corresponding to fig. 15). Thus, no lateral undercuts, pits, etc. are formed along the dummy structures and/or the boundary sidewall spacers. Furthermore, the boundary sidewall spacers may provide smooth boundary sidewalls that are not damaged during formation of the logic device structure (e.g., due to the material of the boundary sidewalls, as shown below), and therefore do not absorb high-k etch residues during formation of the logic device structure using the HKMG technique. This in turn allows for complete removal of the high-k etch residues, thereby improving the reliability of semiconductor devices formed on the semiconductor substrate.

Referring to fig. 1, a cross-sectional view 100 of some embodiments of an IC including a cell boundary structure 102 for an embedded memory is provided. The cell boundary structure 102 is located on the boundary region 104b of the semiconductor substrate 104. The boundary region 104b separates the storage region 104m of the semiconductor substrate 104 from the logic region 1041 of the semiconductor substrate 104. The semiconductor substrate 104 may be or include, for example, a bulk silicon substrate, a III-V substrate, a silicon-on-insulator (SOI) substrate, or some other suitable semiconductor substrate. As used herein, a term (e.g., semiconductor substrate) with the suffix "(s)" may be, for example, singular or plural. In addition, the cell boundary structure 102 overlaps the boundary isolation structure 106 on the boundary region 104 b. The boundary isolation structures 106 extend into the boundary region 104b and provide physical and electrical separation between the embedded memory 108 on the storage region 104m and the logic devices 110 on the logic region 1041. The boundary isolation structure 106 may be or include, for example, a Shallow Trench Isolation (STI) structure, a Deep Trench Isolation (DTI) structure, some other suitable trench isolation structure, or some other suitable isolation structure.

The cell boundary structure 102 includes a dummy control gate structure 112 and boundary sidewall spacers 114. The dummy control gate structure 112 defines dummy sidewalls 112s facing the logic device 110 and comprising a plurality of different materials. The plurality of different materials may include, for example, silicon nitride, silicon oxide, polysilicon, some other suitable material, or any combination of the preceding. Further, in some embodiments, the dummy sidewall 112s has an upper vertical portion and a lower vertical portion connected by a lateral portion. The upper vertical portion is recessed relative to the lower vertical portion toward storage region 104 m. Boundary sidewall spacers 114 laterally overlie the boundary isolation structures 106 between the dummy control gate structures 112 and the logic devices 110 and are adjacent to the dummy sidewalls 112 s. In some embodiments, the boundary sidewall spacers 114 directly contact the dummy sidewalls 112s and/or extend continuously along the dummy sidewalls 112s from the bottommost edge of the dummy sidewalls 112s to the topmost edge of the dummy sidewalls 112 s. The boundary sidewall spacer 114 may be or include, for example, silicon oxide, silicon nitride, silicon oxynitride, some other suitable dielectric, polysilicon, aluminum copper, tantalum, some other suitable metal or metal alloy, tantalum nitride, titanium nitride, some other suitable metal nitride, or some other suitable material. Further, the boundary sidewall spacers 114 may be or include, for example, a homogeneous material (e.g., a single material).

The boundary sidewall 114s facing the logic device 110 is at least partially defined by the boundary sidewall spacer 114. In some embodiments, the boundary sidewalls 114s are completely defined by the boundary sidewall spacers 114. In other embodiments, the boundary sidewalls 114s are collectively defined by the boundary sidewall spacers 114 and the boundary isolation structures 106. In some other embodiments, a portion of the boundary sidewalls 114s defined by the boundary isolation structures 106 is continuous and/or flush with a portion of the boundary sidewalls 114s defined by the boundary sidewall spacers 114. The boundary sidewall 114s slopes downward toward the logic device 110. Further, the boundary sidewall 114s is smooth from top to bottom, and in some embodiments, extends continuously from top to bottom. For example, the boundary sidewall 114s may be smooth and/or extend continuously from a top edge of the boundary sidewall 114s to a bottom edge of the boundary sidewall 114 s. For example, the top edge of the boundary sidewall 114s may be flush or substantially flush with the top edge of the dummy sidewall 112s and/or the top surface of the boundary sidewall spacer 114. The bottom edge of the boundary sidewall 114s may be spaced above the bottom surface of the boundary sidewall spacer 114, for example.

During formation of the IC, the boundary sidewall spacers 114 protect the dummy control gate structures 112 from damage and/or retain residue when forming the logic device 110. Without the boundary sidewall spacers 114, lateral undercuts, pits, etc. may be formed along the dummy sidewalls 112s, which may absorb the resulting high-k etch residues during formation of the logic device 110 utilizing the HKMG technique. In addition, the boundary sidewall spacers 114 have smooth boundary sidewalls 114s that are not damaged during the formation of the logic device 110 (e.g., due to the material of the boundary sidewalls 114s and due to the formation of a protective dielectric layer, as described below), and therefore do not absorb high-k etch residues during the formation of the logic device 110 using the HKMG technique. This, in turn, allows for the complete removal of high-k etch residues generated during the formation of the logic device 110 using the HKMG technique, thereby improving the yield and reliability of semiconductor devices formed on the semiconductor substrate 104.

In some embodiments, dummy control gate structure 112 includes a dummy control gate electrode 116 and a dummy control gate dielectric layer 118 stacked on boundary isolation structure 106. Dummy control gate electrode 116 overlies dummy control gate dielectric layer 118, and dummy control gate electrode 116 and dummy control gate dielectric layer 118 together define dummy sidewalls 112 s. The dummy control gate electrode 116 may be or include, for example, doped polysilicon, a metal, some other suitable conductive material, or any combination of the preceding. The dummy control gate dielectric layer 118 may be or include, for example, silicon oxide, silicon nitride, silicon oxynitride, some other suitable dielectric, or any combination of the preceding. In some embodiments, dummy control gate dielectric layer 118 comprises a multi-layer oxide-nitride-oxide (ONO) film, the components of which are shown but not separately labeled for ease of illustration. For example, referring to fig. 2, the various layers of the ONO film are labeled in detail.

In some embodiments, cell boundary structure 102 also includes a dummy select gate electrode 120. Dummy select gate electrode 120 is located laterally on boundary region 104b between boundary isolation structure 106 and embedded memory 108. In addition, dummy select gate electrode 120 has a bottom surface spaced below dummy control gate dielectric layer 118. Dummy select gate electrode 120 overlies dummy select gate dielectric layer 122 and is laterally spaced from dummy control gate electrode 116 by dummy gate spacers 124. In some embodiments, the dummy gate spacers 124 may include first dummy gate spacers 124a and second dummy gate spacers 124 b. The dummy gate spacers 124 cover the boundary isolation structures 106. Dummy select gate electrode 120 may be or include, for example, doped polysilicon, a metal, or some other suitable conductive material. Both the dummy select gate dielectric layer 122 and the dummy gate spacers 124 may be or include, for example, silicon oxide, silicon nitride, silicon oxynitride, some other suitable dielectric, or any combination of the preceding.

The embedded memory 108 is located on the storage region 104m and may be or include, for example, a third generation embedded super flash (ESF3) memory, a first generation embedded super flash (ESF1) memory, a silicon-oxide-nitride-oxide-silicon (SONOS) memory, a metal-oxide-nitride-oxide-silicon (MONOS) memory, or some other suitable type of memory. In some embodiments, the embedded memory 108 includes a pair of individual memory source/drain regions 126, a common memory source/drain region 128, and a pair of selectively conductive memory channels 130. The individual memory source/drain regions 126 and the common memory source/drain region 128 are located on top of the semiconductor substrate 104, and the common memory source/drain region 128 is laterally spaced between the individual memory source/drain regions 126. Further, the individual memory source/drain regions 126 and the common memory source/drain region 128 are doped semiconductor regions having a first doping type (e.g., p-type or n-type). The selectively conductive memory channel 130 is a doped semiconductor region having a second doping type (e.g., p-type or n-type), wherein the second doping type is opposite the first doping type.

A pair of floating gate dielectric layers 132, a pair of floating gate electrodes 134, a pair of control gate dielectric layers 136, and a pair of control gate electrodes 138 are stacked on the selectively conductive memory channel 130. For ease of illustration, only one of the floating gate dielectric layers 132 is labeled 132, only one of the floating gate electrodes 134 is labeled 134, only one of the control gate dielectric layers 136 is labeled 136, and only one of the control gate electrodes 138 is labeled 138. The floating gate dielectric layers 132 respectively overlie the selectively conductive memory channels 130 and may be or include, for example, silicon oxide or some other suitable dielectric. The floating gate electrodes 134 respectively cover the floating gate dielectric layers 132. The control gate dielectric layers 136 respectively cover the floating gate electrodes 134. The control gate electrodes 138 respectively cover the control gate dielectric layers 136. The control gate electrode 138 and the floating gate electrode 134 may be or include, for example, doped polysilicon, a metal, or some other suitable conductive material. Control gate dielectric layer 136 may be or include, for example, silicon nitride, silicon oxide, some other suitable dielectric, or any combination of the preceding. In some embodiments, each control gate dielectric layer 136 comprises an ONO film such that each control gate dielectric layer 136 comprises a lower oxide layer, an upper oxide layer, and an intermediate nitride layer sandwiched between the lower oxide layer and the upper oxide layer.

A pair of control gate spacers 140 covers each floating gate electrode 134, and the control gate spacers 140 of each control gate electrode respectively oppose sidewalls of the control gate electrode, which covers the floating gate electrode. For ease of illustration, only some of the control gate spacers 140 are labeled 140. The floating gate spacers 142 respectively overlie the selectively conductive memory channels 130, each being laterally spaced from the common memory source/drain region 128 by one of the floating gate electrodes 134. In addition, each floating gate spacer 142 lines a sidewall of one of the floating gate electrodes 134. In some embodiments, the first dummy gate spacers 124a have the same width and composition as the control gate spacers 140 and the second dummy gate spacers 124b have the same width and composition as the floating gate spacers 142. Control gate spacer 140 and floating gate spacer 142 may be or include, for example, silicon nitride, silicon oxide, some other suitable dielectric, or any combination of the foregoing. In some embodiments, control gate spacers 140 are both ONO films, components of which are not shown for ease of illustration.

An erase gate electrode 144 and an erase gate dielectric layer 146 laterally overlie the common memory source/drain region 128 between the floating gate electrodes 134. The erase gate electrode 144 overlies the erase gate dielectric layer 146 and, in some embodiments, has a top surface that is flush with a top surface of the control gate electrode 138 and/or a top surface of the dummy control gate structure 112, respectively. The erase gate dielectric layer 146 is formed as a cup on the underside of the erase gate electrode 144 to vertically space the erase gate electrode 144 from the common memory source/drain region 128 and to laterally space the erase gate electrode 144 from the floating gate electrode 134 and the control gate spacer 140. The erase gate electrode 144 may be or include, for example, doped polysilicon, a metal, or some other suitable conductive material. The erase gate dielectric layer 146 may be or include, for example, silicon oxide, silicon nitride, or some other suitable dielectric.

A pair of select gate dielectric layers 148 and a pair of select gate electrodes 150 are stacked on the selectively conductive memory channel 130. For ease of illustration, only one of the marks 148 in the gate dielectric layer 148 is selected, and only one of the gate electrodes 150 is selected and designated 150. Select gate dielectric layers 148 respectively overlie the selectively conductive memory channels 130, each laterally separated from the common memory source/drain region 128 by a respective one of the floating gate electrodes 134. Select gate dielectric layer 148 may be or include, for example, silicon oxide, silicon nitride, or some other suitable dielectric. Select gate electrode 150 may be or include, for example, doped polysilicon, a metal, or some other suitable conductive material.

Logic device 110 is located over logic region 1041 and may be or include, for example, an insulated field effect transistor (IGFET), a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a double-Diffused Metal Oxide Semiconductor (DMOS) device, a bipolar Complementary Metal Oxide Semiconductor (CMOS) DMOS (bcd) device, some other suitable transistor device, or some other suitable semiconductor device. In some embodiments, the logic device 110 includes a pair of source/drain regions 152 and a selectively conductive logic channel 154. The logic source/drain regions 152 are doped semiconductor regions having a first doping type (e.g., p-type or n-type), while the selectively conductive logic channel 154 is a doped semiconductor region having a second, opposite doping type (e.g., p-type or n-type).

A logic gate dielectric layer 156 overlies the selectively conductive logic channel 154, and a logic gate electrode 158 overlies the logic gate dielectric layer 156. The logic gate electrode 158 may be or include, for example, doped polysilicon, a metal, or some other suitable conductive material. Logic gate dielectric layer 156 may be or include, for example, silicon nitride, silicon oxide, a high-k dielectric, some other suitable dielectric, or any combination of the preceding. As used herein, the dielectric constant k of a high-k dielectric is greater than about 3.9, 5, 10, 15, or 20. In some embodiments, the logic gate dielectric layer 156 is a high-k dielectric and the logic gate electrode 158 is a metal. In addition, some embodiments of the select gate electrode 150, the erase gate electrode 144, the control gate electrode 138, and the floating gate electrode 134 may be or include doped polysilicon.

In some embodiments, main side wall spacers 160 line the sidewalls of select gate electrode 150, the sidewalls of dummy select gate electrode 120, and the sidewalls of logic gate electrode 158. For ease of illustration, only some of the major side wall spacers 160 are labeled. The main sidewall spacers 160 may be or include, for example, silicon nitride, silicon oxide, or some other suitable dielectric, or any combination of the preceding. Furthermore, in some embodiments, an interlayer dielectric (ILD) layer 162 covers the embedded memory 108, the logic device 110, and the cell boundary structure 102. ILD layer 162 may alternatively comprise, for example, silicon oxide, silicon nitride, a low-k dielectric, some other suitable dielectric, or any combination of the preceding. As used herein, a low-k dielectric is a dielectric having a dielectric constant k of less than about 3.9, 3, 2, or 1. Furthermore, in some embodiments, contact vias 164 extend through ILD layer 162 to logic source/drain regions 152 and respective memory source/drain regions 126. The contact vias 164 are conductive and may be or include, for example, tungsten, aluminum copper, aluminum, some other suitable metal, or some other suitable conductive material. In some embodiments, a silicide layer 202 is disposed on the dummy control gate electrodes 116, the dummy select gate electrodes 120, and the boundary sidewall spacers 114. A silicide layer 202 is also disposed on the select gate electrode 150 and the erase gate electrode 144 for contact. The silicide layer 202 may be omitted in other figures below for simplicity reasons, but may be disposed in a similar location, for example, on a dummy control gate electrode, a dummy select gate electrode, a boundary sidewall spacer, the select gate electrode 150, or an erase gate electrode.

Referring to fig. 2, an enlarged cross-sectional view 200 of some embodiments of the cell boundary structure 102 of fig. 1 is provided. In some embodiments, the dummy control gate dielectric layer 118 includes a lower oxide layer 1181, an upper oxide layer 118u overlying the lower oxide layer 1181, and an intermediate nitride layer 118m vertically sandwiched between the lower oxide layer 1181 and the upper oxide layer 118 u. Further, in such embodiments, the dummy sidewalls 112s are heterogeneous and include at least three different materials (e.g., silicon nitride, silicon oxide, and polysilicon).

The boundary sidewall 114s is inclined downward away from the dummy sidewall 112s and has an inclination angle θ with respect to the lateral surface of the boundary sidewall spacer 114. The tilt angle θ may be or include, for example, less than about 60 degrees.

Although fig. 1 and 2 illustrate specific configurations of the dummy control gate structure 112, the embedded memory 108, and the logic device 110, it should be understood that other configurations of the dummy control gate structure 112, the embedded memory 108, the logic device 110, or any combination of the preceding are suitable. For example, a different embedded memory type may be employed in place of the embedded memory 108 (see FIG. 1).

Referring to fig. 3, a cross-sectional view 300 of some additional embodiments of the IC of fig. 1 and 2 is provided. As shown in cross-sectional view 300 of fig. 3, a cross-sectional view 300 of some more detailed embodiments of the integrated circuit of fig. 1 and 2 is provided. As shown, dummy liner layer 302 underlies main side wall spacers 160 on memory region 104m and border region 104b and further separates main side wall spacers 160 from select gate electrode 150 and dummy select gate electrode 120. As described above, only some of the main side wall spacers 160 are labeled 160 and only one select gate electrode 150 is labeled 150. The dummy liner layer 302 may be or include, for example, silicon oxide, silicon nitride, some other suitable dielectric, or any combination of the preceding.

The logical boundary structure 304 overlays the boundary isolation structure 106 on the opposite side of the boundary isolation structure 106 from the cell boundary structure 102. Logic boundary structure 304 includes a dummy logic gate dielectric layer 306 and a dummy logic gate electrode 308 overlying dummy logic gate dielectric layer 306. The dummy logic gate electrode 308 may be or include, for example, doped polysilicon, a metal, or some other suitable conductive material. Dummy logic gate dielectric layer 306 may be or include, for example, silicon nitride, silicon oxide, a high-k dielectric, some other suitable dielectric, or any combination of the preceding. In some embodiments, the main side wall spacers 160 comprise a pair of main side wall spacers lining opposite sides of the dummy logic gate electrode 308 and/or covering the dummy logic gate dielectric layer 306, respectively.

The first logic device 110a and the second logic device 110b are located on the logic region 1041 of the semiconductor substrate 104, physically and electrically isolated by a logic isolation structure 310 located laterally between the first logic device 110a and the second logic device 110 b. The logic isolation structure 310 may be or include, for example, an STI structure, a DTI structure, or some other suitable isolation structure. The first and second logic devices 110a, 110b may each be, for example, IGFETs, MOSFETs, DMOS devices, BCD devices, some other suitable transistor device, or some other suitable semiconductor device. In some embodiments, the first logic device 110a is an IGFET and the second logic device 110b is a power MOFSET configured to operate at a higher voltage (e.g., an order of magnitude higher voltage) than the first logic device 110 a. The power MOSFET may be or comprise, for example, a double-Diffused Metal Oxide Semiconductor (DMOS) device or some other suitable power MOSFET.

The first and second logic devices 110a, 110b each include a pair of logic source/drain regions 152 and a selectively conductive logic channel 154. For ease of illustration, only some of the logic source/drain regions 152 are labeled. Each pair of logic source/drain regions 152 is laterally spaced on top of the semiconductor substrate 104. Further, each pair of logic source/drain regions 152 is a doped semiconductor region having a first doping type (e.g., p-type or n-type). The selectively conductive logic channel 154 is a doped semiconductor region having a second doping type (e.g., p-type or n-type) that is opposite the first doping type of the corresponding pair of logic source/drain regions 152.

The first logic device 110a and the second logic device 110b may have different gate dielectric compositions for different operating voltages. By way of non-limiting example, the first logic gate dielectric layer 156a,

The second logic gate dielectric layer 156b and the logic gate electrode 158 are stacked on the selectively conductive logic channel 154 of the second logic device 110b, while the first logic gate dielectric layer 156a is not present in the first logic device 110 a. The logic gate electrode 158 may be or include, for example, doped polysilicon, a metal, or some other suitable conductive material. The first and second logic gate dielectric layers 156a, 156b may be or include, for example, silicon nitride, silicon oxide, a high-k dielectric, some other suitable dielectric, or any combination of the preceding. In some embodiments, the first logic gate dielectric layer 156a is silicon oxide, the second logic gate dielectric layer 156b is a high-k dielectric, and the logic gate electrode 158 is a metal. In some embodiments, main side wall spacers 160 comprise a plurality of main side wall spacers lining the sidewalls of logic gate electrode 158, respectively.

Lower ILD layer 1621 and upper ILD layer 162u are stacked on semiconductor substrate 104 and house contact vias 164. For ease of illustration, only some of the contact vias 164 are labeled. The lower ILD layer 1621 is located on the side of the embedded memory 108, laterally between the cell boundary structure 102 and the logic boundary structure 304, and on the side of the first and second logic devices 110a, 110 b. In addition, a top surface of the lower ILD layer 1621 is flush (e.g., planar or substantially planar) with a top surface of the embedded memory 108, a top surface of the cell boundary structure 102, a top surface of the logic boundary structure 304, a top surface of the first logic device 110a, and a top surface of the second logic device 110 b. The upper ILD layer 162u covers the lower ILD layer 1621, the embedded memory 108, the cell boundary structure 102, the logic boundary structure 304, the first logic device 110a, and the second logic device 110 b. Lower ILD layer 1621 and upper ILD layer 162u may be or include, for example, silicon oxide, silicon nitride, a low-k dielectric, some other suitable dielectric, or any combination of the preceding.

In some embodiments, the dummy select gate electrode 120 and the dummy control gate electrode 116 are laterally spaced apart by first and second dummy gate spacers 124a and 124 b. The first and second dummy gate spacers 124a and 124b cover the boundary isolation structure 106 laterally interposed between the dummy select gate electrode 120 and the dummy control gate electrode 116. In some embodiments, the first dummy gate spacers 124a have the same width as the control gate spacers 140 and the second dummy gate spacers 124b have the same width as the floating gate spacers 142. The first and second dummy gate spacers 124a, 124b may be or include, for example, silicon nitride, silicon oxide, some other suitable dielectric, or any combination of the preceding. In some embodiments, the first dummy gate spacer 124a is an ONO film, components of which are shown but not labeled for ease of illustration. Furthermore, in some embodiments, control gate spacers 140 overlying floating gate electrodes 134 are or include an ONO film, and/or silicide pads 312 overlie logic source/drain regions 152 and separate memory source/drain regions 126, respectively. For ease of illustration, only one of the control gate spacers 140 is labeled 140 and only one of the silicide pads 312 is labeled 312. For example, the ONO films may each include a first oxide layer 140f, a second oxide layer 140s, and an intermediate nitride layer 140m laterally sandwiched between the first and second oxide layers 140f, 140 s. Silicide pads 312 may be or include, for example, nickel silicide or some other suitable silicide.

Referring to fig. 4-22, a series of cross-sectional views 400-2200 illustrate some embodiments of methods for forming an IC including an embedded memory boundary structure having boundary sidewall spacers.

As shown in the cross-sectional view 400 of fig. 4, the semiconductor substrate 104 including the memory region 104m and the logic region 1041 separated by the boundary region 104b is prepared. Semiconductor substrate 104 is recessed into memory region 104m and sacrificial dielectric layer 406 is formed in memory region 104 m.

In some embodiments, sacrificial lower pad layer 402 ' is formed first overlying semiconductor substrate 104, and then sacrificial upper pad layer 404 ' is formed overlying sacrificial lower pad layer 402 '. The sacrificial lower pad layer 402 'and the sacrificial upper pad layer 404' are formed of different materials and may be formed, for example, by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), sputtering, thermal oxidation, or some other suitable growth or deposition process. As used herein, terms (e.g., processes) with the suffix "(es)" may be, for example, singular or plural. Sacrificial lower pad layer 402 'may be formed, for example, of silicon oxide or some other suitable dielectric, and/or sacrificial upper pad layer 404' may be formed, for example, of silicon nitride or some other suitable dielectric.

Then, the sacrificial upper pad layer 404' is patterned to form an opening corresponding to the storage region 104m and cover the logic region 1041. Precursor layer 408 is formed from the top surface of semiconductor substrate 104, thus reducing the height of the top surface of semiconductor substrate 104. In some embodiments, the precursor layer 408 is an oxide layer and is formed by a wet process. Precursor layer 408 is then partially removed, after which the lower remaining portion of precursor layer 408 forms sacrificial dielectric layer 406.

As shown in cross-sectional view 500 of fig. 5, sacrificial dielectric layer 406 and sacrificial lower pad layer 402' may be removed and replaced with storage dielectric layer 604 in storage region 104m and lower pad layer 402 in logic region 1041. Sacrificial upper pad layer 404' is removed and replaced with storage pad layer 502 formed on storage dielectric layer 604 in storage region 104m and upper pad layer 404 formed on lower pad layer 402 in logic region 1041. The upper pad layers 502, 404 can be dielectric material deposited as a conformal layer. Then, the portion of the conformal dielectric material in the storage region 104m is etched and patterned to align the top surface with the top surface of the portion of the conformal dielectric material in the logic region 1041. Storage pad layer 502 and top pad layer 404 may be made of the same or different materials. The boundary isolation structure 106 is formed in the boundary region 104b of the semiconductor substrate 104. The boundary isolation structure 106 provides electrical isolation between semiconductor devices formed on the storage region 104m and semiconductor devices formed on the logic region 1041, hereinafter. The boundary isolation structure 106 may, for example, have a stepped bottom surface that rises from the storage region 104m to the logic region 1041, and/or may, for example, include a dielectric material. Furthermore, the boundary isolation structure 106 may be or include, for example, an STI structure, a DTI structure, or some other suitable isolation region. The semiconductor substrate 104 may be or include, for example, a bulkA silicon substrate, an SOI substrate, a III-V substrate, or some other suitable semiconductor substrate. The cross-sectional view 600 of fig. 6 also illustrates that the logic isolation structure 310 may be formed in the logic region 1041 to divide the logic region 1041 into the first logic region 1041₁And a second logic region 1041₂. First logic region 1041₁Laterally located in the boundary isolation structure 106 and the second logic region 1041₂In the meantime. First logic region 1041₁May, for example, support the core logic devices formed below, while the second logic region 1041₂The high voltage logic device formed below may be supported, for example. For example, a high voltage logic device may be configured as a logic device that operates at a higher voltage (e.g., an order of magnitude higher) than the core logic device. The logic isolation structure 310 may, for example, comprise a dielectric material, and/or may be or comprise, for example, an STI structure, a DTI structure, or some other suitable isolation region. In some embodiments, the process for forming the boundary isolation structure 106 and the logic isolation structure 310 includes patterning the upper pad layers 404, 502 using the layout of the boundary isolation structure 106 and the logic isolation structure 310, and performing etching on the semiconductor substrate 104 and the appropriate locations of the lower pad layer 402 and the upper pad layers 404, 502 to form trenches. A dielectric layer covering the upper pad layers 404, 502 is formed to fill the trenches, and planarization is performed on the upper pad layers 404 and 502 to form the boundary isolation structures 106 and the logic isolation structures 310 in the trenches. For example, the planarization may be performed by Chemical Mechanical Polishing (CMP) or some other suitable planarization process. For example, the patterning may be performed with photolithography and etching processes. A dielectric capping layer 504 is then formed on the upper pad layers 404, 502 and the boundary isolation structures 106 and logic isolation structures 310. The dielectric layer and the dielectric cap layer 504 may be formed, for example, of silicon oxide, silicon nitride, and/or some other suitable dielectric material, and/or may be performed, for example, by CVD, PVD, sputtering, or some other suitable deposition process.

As shown in cross-sectional view 600 of fig. 6, a capping layer 504 is formed and patterned to serve as a mask layer for patterning a floating gate layer 602. The capping layer 504 is formed and patterned to have an opening corresponding to the memory region 104m and a portion of the isolation structure 106 closer to the memory region 104m, and to cover the logic region 1041 and the remaining portion of the isolation structure 106 closer to the logic region 1041. A floating gate layer 602 is formed and patterned on the storage dielectric layer 604. A floating gate layer 602 is first formed on the storage dielectric layer 604 and the capping layer 504 to cover the storage region 104m, the boundary region 104b, and the logic region 1041. The floating gate layer 602 may be formed, for example, conformally, and/or may be formed, for example, from doped polysilicon, a metal, or some other suitable conductive material. In some embodiments, the floating gate layer 602 is formed by CVD, PVD, or some other suitable deposition process. Then, planarization is performed on top of the floating gate layer 602 until the capping layer 504 is reached, thereby removing the floating gate layer 602 from the capping layer 504. In some embodiments, the planarization recesses the topmost surface of the floating gate layer 602 to be approximately flush with the topmost surface of the capping layer 504. For example, planarization may be performed by CMP or some other suitable planarization process.

As shown in cross-sectional view 700 of fig. 7, the floating gate layer 602 is further lowered to obtain a better coupling ratio. In some embodiments, the portion of the isolation structure 106 exposed by the capping layer 504 and closer to the storage region 104m is lowered along with the floating gate layer 602. The floating gate layer 602 may be lowered by a wet etch back process. After lowering the floating gate layer 602, the capping layer 504 may be subsequently removed.

As shown in the cross-sectional view 800 of fig. 8, a multi-layer memory film 702 is formed to cover the floating gate layer 602, the boundary isolation structures 106 and the logic isolation structures 310, and the upper pad layer 404. The multilayer memory film 702 includes a control gate dielectric layer 704, a control gate layer 706, and a control gate hard mask layer 708.

Control gate dielectric layer 704 is formed to cover floating gate layer 602, boundary isolation structure 106 and logic isolation structure 310, and upper pad layer 404. In some embodiments, control gate dielectric layer 704 comprises silicon oxide, silicon nitride, some other suitable dielectric, or any combination of the foregoing. For example, the control gate dielectric layer 704 may be an ONO film, and/or may include a lower oxide layer 7041, an intermediate nitride layer 704m overlying the lower oxide layer 7041, and an upper oxide layer 704u overlying the intermediate nitride layer 704 m. For example, control gate dielectric layer 704 may be formed by CVD, PVD, some other suitable deposition process, or any combination of the preceding.

A control gate layer 706 is formed to cover the control gate dielectric layer 704. Control gate layer 706 may be formed, for example, conformally, and/or may be formed, for example, from doped polysilicon, a metal, or some other suitable conductive material. Furthermore, in some embodiments, control gate layer 706 is formed by CVD, PVD, or some other suitable deposition process.

A control gate hard mask layer 708 is formed to cover the control gate layer 706. In some embodiments, control gate hard mask layer 708 comprises silicon oxide, silicon nitride, some other suitable dielectric, or any combination of the foregoing. For example, the control gate hard mask layer 708 may be a nitride-oxide-nitride (NON) film, and/or may include a lower nitride layer 7081, an intermediate oxide layer 708m overlying the lower nitride layer 7081, and an upper nitride layer 708u overlying the intermediate oxide layer 708 m. For example, control gate hard mask layer 708 may be formed by CVD, PVD, some other suitable deposition process, or any combination of the preceding.

As shown in a cross-sectional view 900 of fig. 9, etching is performed on the multilayer memory film 702 to remove a portion of the multilayer memory film 702 from the memory region 104m, thereby forming a pair of control gate electrodes 138 on the floating gate layer 602. In addition, the etching forms a pair of control gate dielectric layers 136 and a pair of control gate hard masks 210. Control gate dielectric layers 136 are respectively located below control gate electrodes 138, and control gate hard masks 210 are respectively located above control gate electrodes 138. In some embodiments, the process for performing the etching includes forming and patterning a mask layer (e.g., a photoresist layer not shown in the figure) on the multi-layer memory film 702 to cover the boundary region 104b and the logic region 1041, and partially covering the storage region 104m with the layout of the control gate electrode 138. An etchant is then applied to the multi-layer memory film 702 through the mask layer in place until the etchant reaches the floating gate layer 602, and then the mask layer is removed.

As shown in the cross-sectional view 1000 of fig. 10, a series of manufacturing processes are performed so that a memory cell structure is formed on the memory region 104m from the multilayer memory film 702 while leaving the remaining portion of the multilayer memory film 702 on the boundary isolation structure 106 and the logic region 1041. Some of the manufacturing processes are described below as examples and not for purposes of limitation.

Forming control gate spacers 140 along sidewalls of the control gate electrodes 138; the first dummy gate spacer 124a is formed along a sidewall of the multi-layer memory film 702 facing the memory region 104m to cover the boundary isolation structure 106. In some embodiments, the control gate spacers 140 and the first dummy gate spacers 124a are formed by: a control gate spacer lining the structure of fig. 9 is deposited, followed by an etch over the control gate spacer until the horizontal segments of the control gate spacer are removed. The control gate spacers may be formed, for example, conformally, and/or may be formed, for example, from silicon oxide, silicon nitride, some other suitable dielectric, or any combination of the preceding. In some embodiments, the control gate spacer is or includes an ONO film. Further, the control gate spacer layer may be formed by CVD, PVD or some other suitable deposition process, for example.

With the control gate spacers 140 and the first dummy gate spacers 124a in place, etching is performed on the floating gate layer 602 (see fig. 9) and the storage dielectric layer 604 to form a pair of floating gate electrodes 134 and a pair of floating gate dielectric layers 132. The floating gate electrodes 134 are respectively located below the control gate electrodes 138, and are formed of a floating gate layer 602. The floating gate dielectric layers 132 are respectively located under the floating gate electrodes 134, and are formed of a storage dielectric layer 604. During the etch, control gate spacers 140 and control gate hard mask 210 are used as a mask.

Floating gate spacer 142 is formed on the sidewalls of floating gate electrode 134 and control gate spacer 140. In addition, second dummy gate spacers 124b are formed on sidewalls of the first dummy gate spacers 124 a. In some embodiments, the floating gate spacer 142 and the second dummy gate spacer 124b comprise silicon oxide, some other suitable oxide, or some other suitable dielectric. Furthermore, in some embodiments, the process for forming the floating gate spacers 142 and the second dummy gate spacers 124b includes depositing a floating gate spacer and then etching to remove horizontal segments of the floating gate spacer and not to remove vertical segments of the floating gate spacer. The floating gate spacer layer may be deposited, for example, conformally, and/or may be formed, for example, by CVD, PVD, or some other suitable deposition process.

Common memory source/drain regions 128 are formed laterally in the semiconductor substrate 104 between the floating gate electrodes 134. In some embodiments, the process for forming the common memory source/drain regions 128 includes forming and patterning a mask layer to cover the logic region 1041 and the boundary region 104b, and further to cover the storage region 104m outside the common region 104m laterally between the floating gate electrodes 134. Ion implantation or some other suitable doping process is performed with the mask layer in place, and the mask layer is then removed.

An erase gate dielectric layer 146 is formed to cover the common memory source/drain regions 128 and further line the sidewalls of the floating gate electrodes 134 and the sidewalls of the control gate spacers 140 within the common source/drain gaps. The erase gate dielectric layer 146 may be formed, for example, of oxide, nitride, or some other suitable dielectric. In some embodiments, the process used to form erase gate dielectric layer 146 includes High Temperature Oxidation (HTO), in situ water vapor generation (ISSG) oxidation, some other suitable deposition or growth process, or any combination of the foregoing. Further, in some embodiments, the process includes removing dielectric material formed on portions of the storage region 104m outside the common source/drain gap.

The storage dielectric layer 1502 is formed to cover portions of the storage region 104m on opposite sides of the floating gate electrode 134. The storage dielectric layer 1502 may be formed, for example, of oxide, nitride, or some other suitable dielectric. The storage dielectric layer 1502 may be formed, for example, by HTO, ISSG oxidation, some other suitable deposition or growth process, or any combination of the foregoing. A storage gate layer and a storage hard mask layer are formed on the storage dielectric layer 1502. The storage hardmask layer is patterned to form a pair of select gate hardmask 208 on opposite sides of the common memory source/drain region 128, an erase gate hardmask 212 covering the common memory source/drain region 128, and a dummy select gate hardmask 206 abutting sidewalls of the boundary isolation structure 106. The memory gate layer is additionally etched with select gate hard mask 208, erase gate hard mask 212, and dummy select gate hard mask 206 in place to form a pair of select gate electrode 150, erase gate electrode 144, and dummy select gate electrode 120. The storage gate layer may be formed, for example, conformally, and/or may be formed, for example, from doped polysilicon, a metal, or some other suitable conductive material. The memory gate layer may be formed, for example, by CVD, PVD, or some other suitable deposition process.

Then, a first hard mask ARC 1002 is formed to cover the above structure, followed by a planarization process. Thus, once the first hard mask ARC 1002 is sufficiently etched to expose the lower portion of the hard masks 210, 212, 208, 206 and the control gate hard mask layer 708, the top surface of the first hard mask ARC 1002, the top surface of the hard masks 210, 212, 208, 206, and the top surface of the control gate hard mask layer 708 are etched back together. Furthermore, in some embodiments, the first hard mask ARC 1002 is removed after etching, for example, by another etching process or some other suitable removal process. The first hard mask ARC 1002 may be formed by a coating process or may be deposited by, for example, CVD, PVD, or some other suitable deposition process. For example, planarization may be performed by CMP or some other suitable planarization process.

As shown in cross-sectional view 1100 of fig. 11, a dummy pad layer 302 is formed to cover the structure of fig. 10. The dummy liner layer 302 may be formed conformally, for example. In some embodiments, dummy liner layer 302 is formed of silicon oxide or some other suitable dielectric. A first dummy capping layer 1104 is formed to cover the dummy pad layer 302. In some embodiments, the first dummy capping layer 1104 is formed of polysilicon or some other suitable material. Further, the dummy pad layer 302 and/or the first dummy capping layer 1104 may be formed, for example, by CVD, PVD, some other suitable deposition process, or any combination of the preceding, followed by a planarization process.

Further, as shown in the cross-sectional view 1100 of fig. 11, etching is performed on the first dummy capping layer 1104, the dummy liner layer 302, and the multilayer memory film 702 (see fig. 10) to form the dummy control gate dielectric layer 118, the dummy control gate electrode 116 covering the dummy control gate dielectric layer 118, and the dummy control gate hard mask 204 covering the dummy control gate electrode 116. In some embodiments, the etching is performed by forming and patterning a photoresist layer 1102 covering the memory region 104m and a portion of the boundary isolation structure 106. An etchant is then applied to the first dummy capping layer 1104, the dummy liner layer 302, the control gate hard mask layer 708 (see fig. 10), and the control gate layer 706 (see fig. 10) according to the patterned photoresist layer 1102 to stop on the upper oxide layer 704u of the control gate dielectric layer 704. Control gate dielectric layer 704 is then etched and a portion of dummy control gate hard mask 204 facing the logic region is simultaneously removed with control gate dielectric layer 704 (the portion removed by this process is shown by the dashed lines). As such, dummy control gate hard mask 204 has sidewalls that are recessed relative to sidewalls of dummy control gate dielectric layer 118 and dummy control gate electrode 116. In summary, the dummy control gate dielectric layer 118, the dummy control gate electrode 116, the dummy control gate hard mask 204, the dummy liner layer 302 and the first dummy capping layer 1104 define a dummy sidewall 112s that covers the boundary isolation structure 106 and faces the logic region 1041. The dummy sidewalls 112s are heterogeneous (e.g., multiple materials) and have an upper vertical portion and a lower vertical portion connected by a lateral portion, wherein the upper vertical portion is recessed relative to the lower vertical portion toward the storage region 104 m. The photoresist layer 1102 is then stripped.

As shown in cross-sectional view 1200 of fig. 12, boundary sidewall spacers 1202 are formed to cover the first dummy capping layer 1104, the boundary isolation structures 106, and the logic region 1041, and are further formed to line the dummy sidewalls 112S. In some embodiments, the boundary sidewall spacers 1202 are formed of: polysilicon, amorphous silicon, a metal nitride, a dielectric, the same material as the first dummy cap layer 1104, a different material than the upper pad layer 404, or some other suitable material. For example, the boundary sidewall spacers 1202 may be formed of tungsten, aluminum copper, tantalum nitride, or some other suitable metal or metal nitride. As another example, boundary sidewall spacers 1202 may be formed of oxide, silicon nitride, silicon oxynitride, or some other suitable dielectric. The boundary sidewall spacers 1202 may be formed, for example, conformally, and/or may be formed, for example, by CVD, PVD, some other suitable deposition process, or any combination of the preceding.

As shown in cross-sectional view 1300 of fig. 13, an etch is performed in boundary sidewall spacers 1202 (see fig. 12) to remove horizontal segments of boundary sidewall spacers 1202 and not to remove vertical segments of boundary sidewall spacers 1202, thereby forming boundary sidewall spacers 114 on dummy sidewalls 112 s. The boundary sidewall spacer 114 and the first dummy capping layer 1104 collectively define a boundary sidewall 114s that covers the boundary isolation structure 106 and faces the logic region 1041. In some embodiments, a portion of the boundary sidewalls 114s defined by the first dummy capping layer 1104 is continuous with a portion of the boundary sidewalls 114s defined by the boundary sidewall spacers 114. Further, the boundary sidewall 114s is smooth or substantially smooth and slopes downward toward the logic region 1041. In some embodiments, boundary sidewalls 114s extend continuously from the top surface of first dummy capping layer 1104 to the bottom surface of boundary sidewall spacers 114. For example, the etching may be performed by dry etching or some other suitable etching process. For example, the dry etch may use a halogen chemistry, a fluorine chemistry, some other suitable chemistry, or some other suitable chemistry. Halogen chemistries may include, for example, chlorine (e.g., Cl)₂) Hydrogen bromide (e.g., HBr), oxygen (e.g., O)₂) Argon, some other suitable halogen, or any combination of the foregoing. The fluorochemical can, for example, comprise tetrafluoromethane (e.g., CF)₄) Fluoroform (e.g., CHF)₃) Difluoromethane (e.g., CH)₂F₂) Sulfur hexafluoride (e.g. SF)₆) Hexafluoroethane (e.g. C)₂F₆) Hexafluoropropene (e.g., C)₃F₆) Octafluorocyclobutane (e.g. C)₄F₈) Perfluorocyclopentene (C)₅F₈) Some other suitable fluorine, or any combination of the foregoing.

As shown in cross-sectional view 1400 of fig. 14, a protective dielectric layer 1402 is formed on the top surface of the boundary sidewall spacers 114. In some embodiments, protective dielectric layer 1402 is an oxide layer. The protective dielectric layer 1402 may be formed by a heat treatment without an additional mask such that the uppermost portion of the first dummy capping layer 1104 and the boundary sidewall spacers 114 are oxidizedTo form a protective dielectric layer 1402. The protective dielectric layer 1402 is formed entirely on the first dummy capping layer 1104 and the boundary sidewall spacers 114, and is not formed on the boundary isolation structures 106 or other dielectric components. The thickness of protective dielectric layer 1402 may be between about

To aboutPreferably between aboutTo about

Within the range of (1). In some embodiments, the protective dielectric layer 1402 is formed to have a thickness comparable to the thickness of the lower pad layer 402, or the total thickness of the lower pad layer 402 and the upper pad layer 404. Protective dielectric layer 1402 may protect boundary isolation structures 106 during the pad removal process and prevent formation of undercuts at the connection points of boundary sidewall spacers 114 and boundary isolation structures 106, as shown and described below in connection with fig. 15.

As shown in cross-sectional view 1500 of fig. 15, etching is performed in the upper pad layer 404 and the lower pad layer 402 (see fig. 14) to remove the upper pad layer 404 and the lower pad layer 402 in the logic region 1041. In some embodiments, the etching produces a logic recess having sidewalls defined by the boundary isolation structures 106 and the logic isolation structures 310. In some embodiments, the etching is performed with an etchant that has a high etch rate for the top pad layer 404 relative to the boundary sidewall spacers 114 and the first dummy capping layer 1104, such that the boundary sidewall spacers 114 and the first dummy capping layer 1104 serve as a mask for the etching.

Without the boundary sidewall spacer 114 and the protective dielectric layer 1402, the etching of the upper pad layer 404 and the lower pad layer 402 may result in the formation of lateral undercuts, recesses, etc. along the dummy sidewalls 112 s. For example, the dummy sidewalls 112s may be heterogeneous (e.g., multiple materials) and include the same material (e.g., silicon nitride) as the upper pad layer 404, whereby the etchant used to remove the upper pad layer 404 may also partially remove a portion of the dummy sidewalls 112 s. In addition, the boundary sidewall spacers 114 provide smooth boundary sidewalls 114s, which remain smooth after etching. For example, the boundary sidewall 114s may be a material having a low or negligible etch rate for the etchant used to remove the upper pad layer 404. As another example, the boundary sidewall 114s may be homogenous (e.g., a single material) such that the etching of the boundary sidewall 114s is uniform or substantially uniform across the boundary sidewall 114 s. Since the boundary sidewall 114s remains smooth after etching, the boundary sidewall 114s does not absorb etch residues (e.g., high-k etch residues) generated during subsequent processing and facilitates complete removal of the etch residues.

As described above, the uppermost portion of the protective dielectric layer 1402 (see fig. 14) and the boundary isolation structure 106 are simultaneously removed together with the lower pad layer 402. Without the protective dielectric layer 1402 formed on the boundary sidewall spacer 114, when the boundary isolation structure 106 is removed simultaneously with the lower pad layer 402 due to the etch selectivity, the boundary sidewall spacer 114 remains unchanged and thus an undercut is formed at the connection point 1502 below the boundary sidewall spacer 114. With the protective dielectric layer 1402 formed on the boundary sidewall spacer 114, the protective dielectric layer 1402 may protect the boundary isolation structure 106 during a pad removal process and prevent an undercut from being formed at a connection point 1502 between the boundary sidewall spacer 114 and the boundary isolation structure 106, thereby preventing residual contamination during a subsequent process, thereby improving device reliability. The resulting boundary sidewall 114s has an upper portion defined by the boundary sidewall spacer 114 and a lower portion defined by the boundary isolation structure 106, wherein the upper portion is continuous and/or flush with the lower portion. The boundary sidewall 114s slopes downward toward the logic device 110. Further, the boundary sidewall 114s is smooth from top to bottom, and in some embodiments, extends continuously from top to bottom. For example, the boundary sidewall 114s may be smooth and/or extend continuously from a top edge of the boundary sidewall 114s to a bottom edge of the boundary sidewall 114 s. The top edge of the boundary sidewall 114s may be flush or substantially flush with the top edge of the dummy sidewall 112s and/or the top surface of the boundary sidewall spacer 114, for example. For example, the bottom edge of the boundary sidewall 114s may be spaced above the bottom surface of the boundary sidewall spacer 114.

As shown in cross-sectional view 1600 of fig. 16, HV dielectric layer 1602 is formed and patterned to extend from first logic region 1041₁Is removed and formed in the second logic region 1041₂The above. The HV dielectric layer 1602 may be formed, for example, from an oxide, a high-k dielectric, some other suitable dielectric, or any combination of the preceding. HV dielectric layer 1602 may also be formed on first dummy capping layer 1104 and boundary sidewall spacers 114. HV dielectric layer 1602 may be formed conformally, and/or by CVD, PVD, electroless plating, electroplating, some other suitable growth or deposition process, or any combination of the preceding.

As shown in cross-sectional view 1700 of fig. 17, a logic dielectric layer 1702 is formed to cover and line the structure of fig. 16. Further, a logic gate layer 1704 is formed to cover the logic dielectric layer 1702, and a logic hard mask layer 1706 is formed to cover the logic gate layer 1704. The logic dielectric layer 1702 may be formed, for example, from an oxide, a high-k dielectric, some other suitable dielectric, or any combination of the preceding. Logic gate layer 1704 may be formed, for example, of doped or undoped polysilicon, metal, some conductive material, or some other suitable material. The logic hard mask layer 1706 may be formed, for example, of silicon nitride, silicon oxide, some other suitable dielectric, or any combination of the foregoing materials. In some embodiments, logic dielectric layer 1702, logic gate layer 1704, and logic hard mask layer 1706 are formed conformally and/or by CVD, PVD, electroless plating, electroplating, some other suitable growth or deposition process, or any combination of the foregoing.

As shown in cross-sectional view 1800 of fig. 18, an etch is performed on logic hard mask layer 1706, logic gate layer 1704, and logic dielectric layer 1702 (see fig. 17) to form dummy logic gate dielectric layer 306, dummy logic gate electrode 308, and dummy logic gate hard mask 2702. Dummy logic gate dielectric layer 306 and dummy logic gate electrode 308 overlie the gate region between the boundary sidewall spacer 114 and the logic region 1041The boundary isolation structure 106 and the dummy logic gate hard mask 2702 cover the dummy logic gate electrode 308. In addition, the etching forms a pair of second logic gate dielectric layers 156b, a pair of sacrificial logic gate electrodes 2704, and a pair of logic gate hard masks 2706. A second logic gate dielectric layer 156b and a sacrificial logic gate electrode 2704 cover the first and second logic regions 1041, respectively₁、1041₂The logic gate hard masks 2706 then cover the sacrificial logic gate electrodes 2704, respectively.

As shown in the cross-sectional view 1900 of fig. 19, etching is performed on the logic gate dielectric layer 1702 and the first dummy capping layer 1104 to remove the logic gate dielectric layer 1702 and the first dummy capping layer 1104 from the storage region 104 m. In some embodiments, the etching is performed by forming and patterning a photoresist layer 1902 that covers the logic region 1041 and the boundary isolation structure 106 but does not cover the memory region 104 m. An etchant is then applied to the logic dielectric layer 1702 and the first dummy capping layer 1104 with the photoresist layer 1902 in place until the etchant reaches the dummy liner layer 302, and then the photoresist layer 1902 is stripped. The dummy liner layer 302 may, for example, serve as an etch stop layer for the etching.

As shown in cross-sectional view 2000 of fig. 20, main sidewall spacers 160 are formed along sidewalls of select gate electrode 150, sidewalls of dummy select gate electrode 120, sidewalls of first dummy capping layer 1104, sidewalls of dummy logic gate electrode 308, and sidewalls of sacrificial logic gate electrode 2704. For ease of illustration, only some of the major side wall spacers 160 are labeled 160. In some embodiments, the primary sidewall spacers 160 comprise silicon oxide, silicon nitride, some other suitable dielectric, or any combination of the preceding. Furthermore, in some embodiments, the process for forming the main sidewall spacers 160 includes depositing a main boundary sidewall spacer overlying and lining the structure of fig. 19. Then, an etch-back is performed in the main boundary sidewall spacers to remove the horizontal segments of the main boundary sidewall spacers, but not the vertical segments of the main boundary sidewall spacers. The main boundary sidewall spacers may be deposited, for example, conformally, and/or may be formed, for example, by CVD, PVD, some other suitable deposition process, or any combination of the preceding.

Also shown by the cross-sectional view 2000 of fig. 20, individual memory source/drain regions 126 are formed in the storage regions 104m, respectively adjacent to the select gate electrodes 150. In addition, logic source/drain regions 152 are formed in pairs in logic region 1041, wherein the source/drain regions of each pair are respectively adjacent opposing sidewalls of sacrificial logic gate electrode 2704. In some embodiments, the process for forming the single memory source/drain region 126 and logic source/drain region 152 includes ion implantation into the semiconductor substrate 104. For example, the dopant and/or doping energy may be selected to perform ion implantation through the dummy pad layer 302, the storage dielectric layer 1502, the logic dielectric layer 1702, and the lower pad layer 402. In other embodiments, separate memory source/drain regions 126 and logic source/drain regions 152 are formed using some process other than ion implantation.

Also shown by cross-sectional view 2000 of fig. 20, an etch is performed on the dummy liner layer 302, the storage dielectric layer 1502 (see fig. 19), and the logic dielectric layer 1702 (see fig. 19) to remove these layers from the individual storage source/drain regions 126 and logic source/drain regions 152, thereby exposing the individual storage source/drain regions 126 and logic source/drain regions 152. In addition, the etching forms a pair of select gate dielectric layers 148, a dummy select gate dielectric layer 122, a dummy logic gate dielectric layer 306, and a pair of second logic gate dielectric layers 156 b.

Since the formation of the boundary sidewall spacers 114 and the formation and removal of the protective dielectric layer 1402 (as described above with reference to fig. 12-15) provide a smooth boundary sidewall 114s that is defect-free, the boundary sidewall 114s does not absorb etch residues (e.g., high-k etch residues) during etching. This facilitates complete removal of the etch residue. The boundary sidewall spacers 114 may increase the yield and reliability of semiconductor devices (e.g., logic or memory devices) on the semiconductor substrate 104 by facilitating complete removal of etch residues.

Also shown by cross-sectional view 2000 of fig. 20, silicide pads 312 are formed on the individual memory source/drain regions 126 and logic source/drain regions 152. For ease of illustration, only some of the silicide pads 312 are labeled 312. The silicide pads 312 may be or include, for example, nickel silicide or some other suitable silicide, and/or may be formed, for example, by a silicidation process or some other suitable growth process.

As shown in the cross-sectional view 2100 of fig. 21, a mask layer is formed to cover the structure of fig. 20, and then a planarization process is performed. The planarization process may remove the control gate hard mask 210, the select gate hard mask 208, the erase gate hard mask 212, and the logic gate hard mask 2706, the dummy control gate hard mask 204, the select gate hard mask 206, and the logic gate hard mask 2702, and the first dummy capping layer 1104 (see fig. 20). The planarization process may be, for example, CMP or some other suitable planarization process.

Also shown by cross-sectional view 2100 of fig. 21, lower ILD layer 1621 is formed with a top surface that is flat or substantially flat, as well as the flat surface of the structure of fig. 21. The lower ILD layer 1621 may be, for example, an oxide, a low-k dielectric, some other suitable dielectric, or any combination of the preceding. The lower ILD layer 1621 may be deposited, for example, by CVD, PVD, sputtering, or any combination of the foregoing, followed by a planarization process. The planarization process may be, for example, CMP or some other suitable planarization process. The planarization process recesses a top surface of the lower ILD layer 1621 to be substantially flush with a top surface of the sacrificial logic gate electrode 2704 (see fig. 20), thereby exposing the sacrificial logic gate electrode 2704. Then, a replacement gate process is performed: etching is performed on the sacrificial logic gate electrode 2704 to remove the sacrificial logic gate electrode 2704. In some embodiments, an etch is performed with the mask layer in place to protect other regions of the structure until the sacrificial logic gate electrode 2704 is removed. The logic gate electrode 158 is formed in place of the sacrificial logic gate electrode 2704. The logic gate electrode 158 may be, for example, a metal, doped polysilicon, a different material than the sacrificial logic gate electrode 2704, or some other suitable conductive material. In some embodiments, the process for forming the logic gate electrode 158 includes forming a conductive layer by, for example, CVD, PVD, electroless plating, electroplating, or some other suitable growth or deposition process. Planarization is then performed in the conductive layer until reaching the lower ILD layer 1621. For example, planarization may be performed by CMP or some other suitable planarization process.

As shown in cross-sectional view 2200 of fig. 22, an upper ILD layer 162u is formed to cover the structure of fig. 21 and has a planar or substantially planar top surface. In some embodiments, the upper ILD layer 162u may be, for example, an oxide, a low-k dielectric, some other suitable dielectric, or any combination of the preceding. Furthermore, upper ILD layer 162u may be formed, for example, by depositing upper ILD layer 162u and then performing planarization in the top surface of upper ILD layer 162 u. The deposition may be performed, for example, by CVD, PVD, sputtering, or any combination of the foregoing. For example, planarization may be performed by CMP or some other suitable planarization process.

Also shown by cross-sectional view 2200 of fig. 22, contact vias 164 are formed that extend through upper ILD layer 162u and lower ILD layer 1621 to individual memory source/drain regions 126, logic source/drain regions 152, common memory source/drain region 128, control gate electrode 138, select gate electrode 150, erase gate electrode 144, logic gate electrode 158, or any combination of the foregoing.

Referring to fig. 23, a flow diagram 2300 of some embodiments of a method for forming an IC including an embedded memory boundary structure with boundary sidewall spacers is provided. For example, the IC may correspond to the IC of fig. 4-22.

At step 2302, a substrate is provided. The substrate includes a storage region and a logic region. For example, referring to fig. 4, a storage dielectric layer is formed in the storage region.

At step 2304, see, e.g., FIG. 5, a boundary isolation structure is formed to separate the memory region from the logic region.

At step 2306, for example, see fig. 6-8, a multilayer storage film is formed overlying the substrate.

At step 2308, for example, see fig. 9-10, a memory cell structure is formed with a multilayer memory film over the memory region while leaving a remaining portion of the multilayer memory film over the boundary isolation structure and the logic region.

At step 2310, see, e.g., fig. 11, the multilayer memory film is patterned to form dummy sidewalls overlying the boundary isolation structures and facing the logic regions.

At step 2312, for example, see fig. 12 and 13, boundary sidewall spacers are formed and patterned to form boundary sidewall spacers with smooth boundary sidewalls on the dummy sidewalls.

At step 2314, for example, see fig. 14, a protective dielectric layer is formed on the top surfaces of the boundary sidewall spacers.

At step 2316, the lower pad layer and the upper pad layer in the logic area are removed simultaneously with the protective dielectric layer. For example, see fig. 15, the protective dielectric layer prevents undercutting at the junction of the boundary sidewall spacer and the boundary isolation structure.

At step 2318, a logic dielectric layer and a logic gate layer are formed over the logic region. For example, referring to fig. 16 and 17, dielectric residue is reduced or eliminated at the connection points of the boundary sidewall spacers and the boundary isolation structures.

At step 2320, for example, see fig. 18-22, a logic device is formed in the logic region.

While the flowchart 2300 of fig. 23 is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Moreover, not all illustrated acts may be required to implement one or more aspects or embodiments described herein, and one or more of the acts depicted herein may be performed in one or more separate acts and/or phases.

In view of the foregoing, some embodiments of the present application relate to Integrated Circuits (ICs). The IC includes an isolation structure disposed within a semiconductor substrate and separating a logic region and a storage region of the semiconductor substrate. The isolation structure includes a dielectric material. The IC also includes a memory cell disposed in the storage region and a dummy control gate structure disposed on the isolation structure. The dummy control gate structure defines a dummy sidewall facing the logic region and comprising a plurality of materials. The IC also includes boundary sidewall spacers disposed on the isolation structures along the dummy sidewalls of the dummy control gate structures. The boundary sidewall spacer has a smooth boundary sidewall facing the logic region. The IC also includes a logic device disposed on the logic region.

According to an aspect of the invention, there is provided a method for forming an Integrated Circuit (IC), the method comprising: providing a semiconductor substrate comprising a logic region and a storage region; forming a lower bonding pad layer and an upper bonding pad layer on the logic area; forming a dummy structure between the logic region and the storage region and defining a dummy sidewall of the dummy structure facing the logic region; forming a boundary sidewall spacer to cover the dummy structure and to at least partially define a boundary sidewall of the boundary sidewall spacer facing the logic region; forming a protective dielectric layer on the top surface of the boundary sidewall spacer; removing the lower bonding pad layer and the upper bonding pad layer in the logic area, wherein the protective medium layer is removed at the same time; and forming a logic device structure on the logic region.

In an embodiment, the protective dielectric layer is formed by heat treatment such that an uppermost portion of the boundary sidewall spacer forms the protective dielectric layer.

In an embodiment, the dummy structure is formed by forming and patterning a multi-layer film to form a memory cell structure on the memory region and to form the dummy structure on the isolation structure.

In an embodiment, the boundary sidewall spacers and upper portions of the isolation structures collectively define the boundary sidewall facing the logic region, wherein the boundary sidewall is sloped, and wherein portions of the boundary sidewall defined by the boundary sidewall spacers are continuous with portions of the boundary sidewall defined by the isolation structures.

In an embodiment, the method further comprises: a planarization process is performed to form a planar top surface of the isolation structure.

In an embodiment, forming the memory cell structure and the boundary sidewall spacer comprises: patterning the multilayer film to form the memory cell structure on the memory region; forming a dummy capping layer to cover the memory cell structure and a remaining portion of the multi-layered film; performing a first etch of the multilayer film and the dummy cap layer to remove the multilayer film and the dummy cap layer from the logic region and to define the dummy sidewalls on the isolation structures; forming the boundary sidewall spacers to cover the dummy capping layer, the isolation structure and the logic region, and further to line the dummy sidewalls; and performing a second etch of the boundary sidewall spacers to remove horizontal segments of the boundary sidewall spacers and form the boundary sidewall spacers on dummy sidewalls.

In an embodiment, the method further comprises: forming a precursor oxide layer with a top surface of the semiconductor substrate and reducing a height of the top surface of the storage region of the semiconductor substrate using the upper pad layer as a mask; and removing an upper portion of the precursor oxide layer to form a storage dielectric layer with the precursor oxide layer.

In an embodiment, forming the logic device structure comprises: forming a conformal high-k dielectric layer over the dummy cap layer, the boundary sidewall spacers, and the logic region; forming a polysilicon layer on the conformal high-k dielectric layer; and etching the common high-k dielectric layer and the polysilicon layer to form a polysilicon gate electrode and a high-k gate dielectric layer stacked on the logic region; and replacing the polysilicon gate electrode with a metal gate. Furthermore, some embodiments of the present application relate to ICs. The IC includes a semiconductor substrate including a memory region having memory cells disposed thereon and a logic region having logic devices disposed thereon. The IC also includes an isolation structure disposed within the semiconductor substrate and separating the logic region and the storage region. The isolation structure includes a dielectric material. The IC also includes a dummy control gate dielectric layer disposed on the isolation structure and a dummy control gate electrode disposed on the dummy control gate dielectric layer. The IC also includes a boundary sidewall spacer disposed on the isolation structure along the dummy control gate electrode and the dummy control gate dielectric layer. The boundary sidewall spacers and the uppermost portions of the isolation structures collectively define a boundary sidewall facing the logic region. The boundary sidewall is continuous and slopes downward toward the logic region.

In an embodiment, the dummy sidewall has an upper vertical portion and a lower vertical portion connected by a lateral portion, wherein the upper vertical portion is recessed relative to the lower vertical portion toward the storage region.

In an embodiment, the boundary sidewall extends continuously from top to bottom.

In an embodiment, the boundary sidewall has an angle relative to a lateral planar surface of the boundary sidewall spacer of less than about 60 degrees.

In an embodiment, the dummy control gate structure includes an oxide-nitride-oxide (ONO) film and a dummy gate electrode covering the oxide-nitride-oxide film.

In an embodiment, the boundary sidewall spacer directly contacts the dummy sidewall.

Further, some embodiments of the present application relate to a method of providing a semiconductor substrate including a logic region and a storage region, and forming a lower pad layer and an upper pad layer on the logic region. The method also includes forming an isolation structure in the semiconductor substrate, the isolation structure separating the logic region and the storage region. The method also includes forming and patterning the multilayer film to form a memory cell structure on the storage region, and forming a dummy structure on the isolation structure and defining a dummy structure facing a dummy sidewall of the logic region. The method also includes forming and patterning a boundary sidewall spacer covering the multilayer film to form a boundary sidewall spacer covering the dummy structure and to at least partially define a boundary sidewall of the boundary sidewall spacer facing the logic region. The method also includes forming a protective dielectric layer on top surfaces of the boundary sidewall spacers. The method also includes removing the lower pad layer and the upper pad layer in the logic area. And simultaneously removing the protective dielectric layer. The method also includes forming a logic device structure on the logic region.

In an embodiment, the dummy structure and the memory cell structure are formed simultaneously by forming and patterning a multi-layer film on the memory region.

In an embodiment, forming the boundary sidewall spacer comprises: forming a dummy capping layer to cover the memory cell structure and a remaining portion of the multi-layered film; performing a first etch of the multilayer film and the dummy cap layer to remove the multilayer film and the dummy cap layer from the logic region and to define the dummy sidewalls on the isolation structures; forming a boundary sidewall spacer to cover the dummy capping layer, the isolation structure and the logic region and further line the dummy sidewall; and performing a second etch of the boundary sidewall spacers to remove horizontal segments of the boundary sidewall spacers and form the boundary sidewall spacers on dummy sidewalls.

In an embodiment, the protective dielectric layer and the lower pad layer and the upper pad layer on the logic area are removed simultaneously;

in an embodiment, before forming the isolation structure, further comprising: forming a precursor oxide layer with a top surface of the semiconductor substrate and reducing a height of the top surface of the storage region of the semiconductor substrate using the upper pad layer as a mask; and removing an upper portion of the precursor oxide layer to form a storage dielectric layer with the precursor oxide layer.

In an embodiment, the protective dielectric layer is formed by heat treatment such that an uppermost portion of the boundary sidewall spacer forms the protective dielectric layer.

The foregoing has outlined features of various embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.