阅读说明：本技术 一种基于gpio实现i2s从机功能的方法及终端 (Method and terminal for realizing I2S slave computer function based on GPIO ) 是由 杨超 孟庆晓 吴闽华 梁栋 戴瑜 于 2019-09-19 设计创作，主要内容包括：本发明公开了一种基于GPIO实现I2S从机功能的方法及终端,所述方法包括：设置GPIO1接收I2S的SCLK信号、GPIO2接收I2S的WS信号以及GPIO3接收I2S的SD信号；主机MCU分别发送所述SCLK信号、所述WS信号和所述SD信号到从机CPU的GPIO1、GPIO2和GPIO3上；当GPIO1产生上升沿中断后,SCLK从低电平转变成了高电平,从所述SD信号读取比特数据。本发明通过利用GPIO实现了I2S从机功能的软件驱动,使得从机CPU可以支持I2S从机模式。(The invention discloses a method and a terminal for realizing the function of an I2S slave computer based on GPIO, wherein the method comprises the following steps: setting GPIO1 to receive SCLK signal of I2S, GPIO2 to receive WS signal of I2S, and GPIO3 to receive SD signal of I2S; the host MCU respectively sends the SCLK signal, the WS signal and the SD signal to GPIO1, GPIO2 and GPIO3 of the slave CPU; when the GPIO1 generates a rising edge interrupt, SCLK transitions from low to high, reading the bit data from the SD signal. The invention realizes the software drive of the function of the I2S slave machine by utilizing GPIO, so that the CPU of the slave machine can support the I2S slave machine mode.)

1. A method for realizing an I2S slave function based on GPIO is characterized in that the method for realizing the I2S slave function based on GPIO comprises the following steps:

setting GPIO1 to receive SCLK signal of I2S, GPIO2 to receive WS signal of I2S, and GPIO3 to receive SD signal of I2S;

the host MCU respectively sends the SCLK signal, the WS signal and the SD signal to GPIO1, GPIO2 and GPIO3 of the slave CPU;

when the GPIO1 generates a rising edge interrupt, SCLK transitions from low to high, reading the bit data from the SD signal.

2. The method for implementing the I2S slave function based on GPIO as claimed in claim 1, wherein when the GPIO1 generates a rising edge interrupt, the SCLK transits from low level to high level, and reads the bit data from the SD signal, and further comprising:

if WS is high, the preset size bit data is stored in the left channel buffer, and if WS is low, the preset size bit is transferred into the right channel buffer.

3. The GPIO-based method of implementing I2S slave functions of claim 2, wherein the GPIO1 supports generating interrupts to the slave CPU and edge-triggered interrupts.

4. The method of claim 3, wherein if WS is high, storing bits of a predetermined size into the left channel buffer, and if WS is low, transmitting bits of a predetermined size into the right channel buffer, specifically:

if 16 interrupts are generated continuously, 16 bits of data are read; if WS is high, 16 bits of data are stored in the left channel buffer, and if WS is low, 16 bits are transferred into the right channel buffer.

5. The GPIO-based method of enabling I2S slave functionality according to claim 1, wherein the GPIO-based method of enabling I2S slave functionality further comprises:

setting GPIO1 as an input function, setting GPIO2 as an input function, and setting GPIO3 as an input function;

setting GPIO1 rising edge interrupt;

mounting a GPIO1 interrupt processing function;

the number of received bits is 0, enabling GPIO1 interrupts.

6. The method for realizing the I2S slave function based on the GPIO as claimed in claim 5, wherein the interrupt handling function is used for processing the read request sent by the host MCU.

7. The GPIO-based method of enabling I2S slave functionality according to claim 6, wherein the GPIO-based method of enabling I2S slave functionality further comprises:

when entering the entrance of the interrupt processing function, judging whether the WS of the GPIO2 is 1;

if not, reading one bit of the SD of the GPIO3 and storing the bit into a right channel buffer, and adding 1 to the bit number;

if so, reading one bit of the SD of the GPIO3 and storing the bit into a left channel buffer, and adding 1 to the bit number;

judging whether the number of bits is 16;

if so, informing the upper layer to read data from the buffer, wherein the bit number is 0, and entering an outlet of an interrupt processing function;

and when not, directly entering the exit of the interrupt processing function.

8. A system for implementing I2S slave function based on GPIO, the system comprising: a host MCU and a slave CPU;

the GPIO1 is preset to receive SCLK signal of I2S, the GPIO2 receives WS signal of I2S and the GPIO3 receives SD signal of I2S; the master MCU respectively sends the SCLK signal, the WS signal and the SD signal to GPIO1, GPIO2 and GPIO3 of the slave CPU; when the GPIO1 generates a rising edge interrupt, SCLK transitions from low to high, reading the bit data from the SD signal.

9. A terminal, characterized in that the terminal comprises: a memory, a processor, and a program stored on the memory and executable on the processor to implement a GPIO-based I2S slave function, the program to implement a GPIO-based I2S slave function when executed by the processor implementing the steps of the method of implementing a GPIO-based I2S slave function as claimed in any one of claims 1-7.

10. A storage medium storing a program for implementing a I2S slave function based on GPIO, wherein the program for implementing a I2S slave function based on GPIO when executed by a processor implements the steps of the method for implementing a I2S slave function based on GPIO of any one of claims 1-7.

Technical Field

The invention relates to the technical field of computer application, in particular to a method, a terminal and a storage medium for realizing the function of an I2S slave computer based on GPIO.

Background

I2S (Inter-IC Sound, audio bus built in integrated circuit) is a bus standard established by philips for audio data transmission between digital audio devices, and adopts a design of transmitting a clock and a data signal along separate wires, and avoids skew induced by time difference by separating the data and clock signals. The I2S bus is simple and effective, can effectively improve the quality of output data, and has wide application in various embedded audio systems. However, in embedded audio system designs, not all CPUs support the I2S bus format, and even less CPUs support the I2S slave mode.

I2S is a three-wire bus, and 3 signals are: a serial clock SCK, a frame clock WS, and a serial data signal SD; the serial clock SCK is also called a Bit Clock (BCK), that is, each time 1 bit of digital audio data is transmitted, the SCK has 1 pulse, the frequency of the SCK is 2 × sampling frequency × sampling bit, and in the data transmission process, both the transmitter and the receiver of the I2S bus can be used as a host of the system to provide the clock frequency of the system. The frame clock WS, i.e. the command (channel) selection, is used to switch the data of the left and right channels, the frequency of WS being equal to the sampling frequency and provided by the system host, WS "1" indicating that the data of the left channel is transmitted and WS "0" indicating that the data of the right channel is transmitted. The serial data signal SD is used to transmit audio data represented by two's complement.

Regardless of the number of bits of valid data in the signal in I2S format, the Most Significant Bit (MSB) of the data bit is always transmitted first, and the number of data that can be transmitted 1 time is determined by the number of valid bits in the I2S format. As shown in fig. 1, is a typical I2S timing, when WS is high, data is sent to the left channel, and when WS is low, data is sent to the right channel, sampled at clock high.

Accordingly, the prior art is yet to be improved and developed.

Disclosure of Invention

The invention mainly aims to provide a method, a terminal and a storage medium for realizing the function of an I2S slave computer based on GPIO, and aims to solve the problem that a CPU supporting an I2S slave computer mode is lacked in the prior art.

In order to achieve the above object, the present invention provides a method for implementing an I2S slave function based on GPIO, where the method for implementing an I2S slave function based on GPIO includes the following steps:

setting GPIO1 to receive SCLK signal of I2S, GPIO2 to receive WS signal of I2S, and GPIO3 to receive SD signal of I2S;

the host MCU respectively sends the SCLK signal, the WS signal and the SD signal to GPIO1, GPIO2 and GPIO3 of the slave CPU;

when the GPIO1 generates a rising edge interrupt, SCLK transitions from low to high, reading the bit data from the SD signal.

Optionally, the method for implementing the I2S slave function based on GPIO, wherein when the GPIO1 generates a rising edge interrupt, SCLK transitions from low level to high level, and reads bit data from the SD signal, and then further includes:

if WS is high, the preset size bit data is stored in the left channel buffer, and if WS is low, the preset size bit is transferred into the right channel buffer.

Optionally, the method for implementing the I2S slave function based on GPIO is further described, wherein the GPIO1 supports generation of interrupts to the slave CPU and supports edge triggered interrupts.

Optionally, the method for implementing the I2S slave function based on GPIO includes storing bits of a preset size into a left channel buffer if WS is at a high level, and transmitting bits of a preset size into a right channel buffer if WS is at a low level, specifically:

if 16 interrupts are generated continuously, 16 bits of data are read; if WS is high, 16 bits of data are stored in the left channel buffer, and if WS is low, 16 bits are transferred into the right channel buffer.

Optionally, the method for implementing the I2S slave function based on GPIO further includes:

setting GPIO1 as an input function, setting GPIO2 as an input function, and setting GPIO3 as an input function;

setting GPIO1 rising edge interrupt;

mounting a GPIO1 interrupt processing function;

the number of received bits is 0, enabling GPIO1 interrupts.

Optionally, the method for implementing the I2S slave function based on GPIO is configured to process a read request sent by the host MCU.

Optionally, the method for implementing the I2S slave function based on GPIO further includes:

when entering the entrance of the interrupt processing function, judging whether the WS of the GPIO2 is 1;

if not, reading one bit of the SD of the GPIO3 and storing the bit into a right channel buffer, and adding 1 to the bit number;

if so, reading one bit of the SD of the GPIO3 and storing the bit into a left channel buffer, and adding 1 to the bit number;

judging whether the number of bits is 16;

if so, informing the upper layer to read data from the buffer, wherein the bit number is 0, and entering an outlet of an interrupt processing function;

and when not, directly entering the exit of the interrupt processing function.

In addition, in order to achieve the above object, the present invention further provides a system for implementing a function of an I2S slave computer based on GPIO, wherein the system includes: a host MCU and a slave CPU;

the GPIO1 is preset to receive SCLK signal of I2S, the GPIO2 receives WS signal of I2S and the GPIO3 receives SD signal of I2S; the master MCU respectively sends the SCLK signal, the WS signal and the SD signal to GPIO1, GPIO2 and GPIO3 of the slave CPU; when the GPIO1 generates a rising edge interrupt, SCLK transitions from low to high, reading the bit data from the SD signal.

In addition, to achieve the above object, the present invention further provides a terminal, wherein the terminal includes: a memory, a processor and a program stored on the memory and executable on the processor for implementing an I2S slave function based on GPIO, the program implementing an I2S slave function based on GPIO when executed by the processor implementing the steps of the method for implementing an I2S slave function based on GPIO as described above.

In addition, in order to achieve the above object, the present invention further provides a storage medium, wherein the storage medium stores a program for implementing the I2S slave function based on GPIO, and the program for implementing the I2S slave function based on GPIO implements the steps of the method for implementing the I2S slave function based on GPIO as described above when being executed by a processor.

The invention sets GPIO1 to receive SCLK signal of I2S, GPIO2 to receive WS signal of I2S, and GPIO3 to receive SD signal of I2S; the host MCU respectively sends the SCLK signal, the WS signal and the SD signal to GPIO1, GPIO2 and GPIO3 of the slave CPU; when the GPIO1 generates a rising edge interrupt, SCLK transitions from low to high, reading the bit data from the SD signal. The invention realizes the software drive of the function of the I2S slave machine by utilizing GPIO, so that the CPU of the slave machine can support the I2S slave machine mode.

Drawings

FIG. 1 is a schematic diagram of a typical I2S timing sequence;

FIG. 2 is a flowchart of a preferred embodiment of a method for implementing the function of the I2S slave based on GPIO according to the present invention;

FIG. 3 is a functional schematic diagram of a preferred embodiment of a system for implementing the function of the I2S slave based on GPIO according to the present invention;

FIG. 4 is a flow chart illustrating the generation of an interrupt in the method for implementing the I2S slave function based on GPIO according to the present invention;

FIG. 5 is a schematic diagram of a process of reading data in the method for implementing the I2S slave function based on GPIO according to the present invention;

FIG. 6 is a diagram illustrating an operating environment of a terminal according to a preferred embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer and clearer, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The MIDO time sequence is simulated through GPIO (a general input/output port is simply a controllable pin of STM32, and the GPIO pin of the STM32 chip is connected with external equipment, so that the functions of external communication, control and data acquisition are realized), and an MDIO protocol is realized through software.

As shown in fig. 2 and 3, the method for implementing the I2S slave function based on GPIO according to the preferred embodiment of the present invention includes the following steps:

step S10, setting GPIO1 to receive SCLK signal of I2S, GPIO2 to receive WS signal of I2S and GPIO3 to receive SD signal of I2S;

step S20, the host MCU sends the SCLK signal, the WS signal and the SD signal to GPIO1, GPIO2 and GPIO3 of the slave CPU respectively;

in step S30, when the GPIO1 generates a rising edge interrupt, SCLK transitions from low to high, and the bit data is read from the SD signal.

Specifically, by using the interrupt function of GPIO, when SCLK generates a high pulse, it indicates that the I2S transmission cycle is started; then, detecting the SD signal, and reading one bit from the SD to a local buffer every high level; the edge of the GPIO is used for triggering the interrupt function, the CPU is not required to poll whether the GPIO is already at a high level, the pressure of the CPU is reduced, and the real-time performance of the I2S time sequence is improved.

As shown in fig. 3, GPIO1 is connected to SCLK signal of I2S, GPIO2 is connected to WS signal of I2S, GPIO3 is connected to SD signal of I2S, and these three signals are input signals to the CPU because I2S slave devices are provided on the CPU.

Further, the selected GPIO1 supports generation of interrupts to the CPU, supporting edge triggered interrupts. When the GPIO1 generates a rising edge interrupt, which indicates that SCLK has transitioned from low to high, 1 bit of data can be read from the SD signal. If 16 interrupts are generated continuously, 16 bits of data are read; if WS is high, 16 bits of data are stored in the left channel buffer, and if WS is low, 16 bits are transferred into the right channel buffer. The upper layer task acquires the 16-bit data from the buffer and then performs other specific operations, such as playing sound or performing encoding and decoding.

Further, a process of enabling GPIO1 interrupt in the method for implementing I2S slave function based on GPIO of the present invention is as shown in fig. 4, and specifically includes:

s1: setting GPIO1 as an input function;

s2: setting GPIO2 as an input function;

s3: setting GPIO3 as an input function;

s4: setting GPIO1 rising edge interrupt;

s5: mounting a GPIO1 interrupt processing function GPIO1_ irs ();

s6: the number of received bits is 0;

s6: enabling GPIO1 interrupts.

The core part is an interrupt processing function gpio1_ irs (), which is used for processing a read request sent by the host MCU, if the host MCU is about to write to the slave CPU, the level of MDC is read in the gpio1_ irs (), one bit (bit, which is the minimum unit of information and is the information contained in one bit of binary number or the required information amount of 1 specially specified in 2 options) is read in each interrupt, and 5 bits are read as a device address according to a protocol PHY address, followed by a 5-bit register internal address.

Further, as shown in fig. 5, when entering the entry of the interrupt handling function GPIO1_ irs (), it is determined whether WS of GPIO2 is 1; if not, reading one bit of the SD of the GPIO3 and storing the bit into a right channel buffer, and adding 1 to the bit number; if so, reading one bit of the SD of the GPIO3 and storing the bit into a left channel buffer, and adding 1 to the bit number; continuously judging whether the number of the bits is 16; if so, informing the upper layer to read data from the buffer, wherein the bit number is 0, and entering an outlet of an interrupt processing function; and when not, directly entering the exit of the interrupt processing function.

Further, as shown in fig. 3, the present invention further provides a system for implementing the function of I2S slave based on GPIO, wherein the system includes: a host MCU and a slave CPU; the GPIO1 is preset to receive SCLK signal of I2S, the GPIO2 receives WS signal of I2S and the GPIO3 receives SD signal of I2S; the master MCU respectively sends the SCLK signal, the WS signal and the SD signal to GPIO1, GPIO2 and GPIO3 of the slave CPU; when the GPIO1 generates a rising edge interrupt, SCLK transitions from low to high, reading the bit data from the SD signal.

Further, as shown in fig. 6, based on the above method for implementing the function of the I2S slave computer based on GPIO, the present invention also provides a terminal, which includes a processor 10, a memory 20, and a display 30. Fig. 6 shows only some of the components of the terminal, but it is to be understood that not all of the shown components are required to be implemented, and that more or fewer components may be implemented instead.

The memory 20 may in some embodiments be an internal storage unit of the terminal, such as a hard disk or a memory of the terminal. The memory 20 may also be an external storage device of the terminal in other embodiments, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like, which are provided on the terminal. Further, the memory 20 may also include both an internal storage unit and an external storage device of the terminal. The memory 20 is used for storing application software installed in the terminal and various types of data, such as program codes of the installation terminal. The memory 20 may also be used to temporarily store data that has been output or is to be output. In an embodiment, the memory 20 stores a program 40 for implementing the I2S slave function based on GPIO, and the program 40 for implementing the I2S slave function based on GPIO is executable by the processor 10, so as to implement the method for implementing the I2S slave function based on GPIO in this application.

The processor 10 may be, in some embodiments, a Central Processing Unit (CPU), a microprocessor or other data Processing chip, and is configured to execute program codes stored in the memory 20 or process data, for example, execute the method for implementing the I2S slave function based on GPIO, and the like.

The display 30 may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, an OLED (Organic Light-Emitting Diode) touch panel, or the like in some embodiments. The display 30 is used for displaying information at the terminal and for displaying a visual user interface. The components 10-30 of the terminal communicate with each other via a system bus.

In one embodiment, when processor 10 executes program 40 in memory 20 that implements the I2S slave function based on GPIO, the following steps are implemented:

setting GPIO1 to receive SCLK signal of I2S, GPIO2 to receive WS signal of I2S, and GPIO3 to receive SD signal of I2S;

the host MCU respectively sends the SCLK signal, the WS signal and the SD signal to GPIO1, GPIO2 and GPIO3 of the slave CPU;

when the GPIO1 generates a rising edge interrupt, SCLK transitions from low to high, reading the bit data from the SD signal.

When the GPIO1 generates a rising edge interrupt, SCLK transitions from low to high, reading bit data from the SD signal, and then:

if WS is high, the preset size bit data is stored in the left channel buffer, and if WS is low, the preset size bit is transferred into the right channel buffer.

The GPIO1 supports generation of interrupts to the slave CPU and edge triggered interrupts.

If WS is high level, storing the bit data with the preset size into the left channel buffer, and if WS is low level, transmitting the bit data with the preset size into the right channel buffer, specifically:

if 16 interrupts are generated continuously, 16 bits of data are read; if WS is high, 16 bits of data are stored in the left channel buffer, and if WS is low, 16 bits are transferred into the right channel buffer.

The method for realizing the function of the I2S slave computer based on the GPIO further comprises the following steps:

setting GPIO1 as an input function, setting GPIO2 as an input function, and setting GPIO3 as an input function;

setting GPIO1 rising edge interrupt;

mounting a GPIO1 interrupt processing function;

the number of received bits is 0, enabling GPIO1 interrupts.

The interrupt processing function is used for processing the read request sent by the host MCU.

The method for realizing the function of the I2S slave computer based on the GPIO further comprises the following steps:

when entering the entrance of the interrupt processing function, judging whether the WS of the GPIO2 is 1;

if not, reading one bit of the SD of the GPIO3 and storing the bit into a right channel buffer, and adding 1 to the bit number;

if so, reading one bit of the SD of the GPIO3 and storing the bit into a left channel buffer, and adding 1 to the bit number;

judging whether the number of bits is 16;

if so, informing the upper layer to read data from the buffer, wherein the bit number is 0, and entering an outlet of an interrupt processing function;

and when not, directly entering the exit of the interrupt processing function.

Further, the present invention also provides a storage medium, wherein the storage medium stores a program for implementing the I2S slave function based on GPIO, and the program for implementing the I2S slave function based on GPIO implements the steps of the method for implementing the I2S slave function based on GPIO as described above when being executed by a processor.

In summary, the present invention provides a method and a terminal for implementing a function of an I2S slave computer based on GPIO, where the method includes: setting GPIO1 to receive SCLK signal of I2S, GPIO2 to receive WS signal of I2S, and GPIO3 to receive SD signal of I2S; the host MCU respectively sends the SCLK signal, the WS signal and the SD signal to GPIO1, GPIO2 and GPIO3 of the slave CPU; when the GPIO1 generates a rising edge interrupt, SCLK transitions from low to high, reading the bit data from the SD signal. The invention realizes the software drive of the function of the I2S slave machine by utilizing GPIO, so that the CPU of the slave machine can support the I2S slave machine mode.

Of course, it will be understood by those skilled in the art that all or part of the processes of the methods of the above embodiments may be implemented by a computer program instructing relevant hardware (such as a processor, a controller, etc.), and the program may be stored in a computer readable storage medium, and when executed, the program may include the processes of the above method embodiments. The storage medium may be a memory, a magnetic disk, an optical disk, etc.

It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.