阅读说明：本技术 一种基于fpga的扩展卡尔曼滤波器电路结构设计方法 (FPGA-based extended Kalman filter circuit structure design method ) 是由 郑智源 *** 刘胜剑 于 2019-10-22 设计创作，主要内容包括：一种基于FPGA的扩展卡尔曼滤波器电路结构设计方法,涉及扩展卡尔曼滤波器电路设计领域。为了实现无传感器时永磁同步直流电机转动时速度与位置的估计。根据PMSM当前时刻电流、电压、转子位置和角速度,通过扩展卡尔曼滤波算法预测下一时刻的PMSM转子位置和角速度；包括用于计数的Counter模块,用于按规定顺序顺序使能SIN、COS、DIV、ADD、MUL模块以用于完成EKF的计算的State_Machine模块,RAM_Controller模块,Calucate_Controller模块、SIN模块、COS模块、DIV模块、ADD模块和MUL模块；SIN模块、COS模块用于计算角度的三角正弦、余弦数值,DIV、ADD、MUL模块分别用于计算带符号定点数的除法、加法、乘法。RAM_Controller用于存储上一时刻扩展卡尔曼滤波算法产生的数据。(An FPGA-based extended Kalman filter circuit structure design method relates to the field of extended Kalman filter circuit design. The method aims to realize the estimation of the speed and the position of the permanent magnet synchronous direct current motor in rotation without a sensor. Predicting the position and the angular speed of the PMSM rotor at the next moment by an extended Kalman filtering algorithm according to the current, the voltage, the rotor position and the angular speed of the PMSM at the current moment; the EKF system comprises a Counter module for counting, a State _ Machine module, a RAM _ Controller module, a calcium _ Controller module, an SIN module, a COS module, a DIV module, an ADD module and a MUL module, wherein the State _ Machine module is used for enabling the SIN module, the COS module, the DIV module, the ADD module and the MUL module in a specified sequence order so as to complete the calculation of the EKF; the SIN module and the COS module are used for calculating triangular sine and cosine numerical values of angles, and the DIV module, the ADD module and the MUL module are respectively used for calculating division, addition and multiplication with symbolic fixed point numbers. And the RAM _ Controller is used for storing the data generated by the extended Kalman filter algorithm at the last moment.)

1. An FPGA-based extended Kalman filter circuit structure design method is used for realizing a position and speed estimator module in a traditional PMSM motor vector control system, and the output quantity of the extended Kalman filter circuit structure is estimation of angular speed (omega) and angle (theta);

the method is characterized by comprising the following steps:

EKF filtering implementation steps:

(1) set Q_d，R，P₀Initial value, Q_dAnd R initial value is set to 0, P₀Setting the unit matrix as a fourth order unit matrix;

(2) measurement of i from PMSM System_α(n)，i_β(n)，v_α(n)，v_β(n)

(3) Calculated according to the following formula:

(4) calculating P_nFirst, P is calculated_n|n-1The calculation method is as follows:

(5) calculating the Kalman gain K_n：

Wherein the content of the first and second substances,

(6) current, angle and position estimation equation at the current moment:

in the formula:

Q_dprocedural noise representing the prediction/update model;

r represents the uncertainty of an observed value in the EKF, can also be called as an observation error, belongs to sensor attributes and is not dependent on time;

P_n|n-1a predicted value (squared error) representing the uncertainty of the current data in the EKF, which is not updated with the data at the current time;

P_nan updated value representing the predicted value of the uncertainty at the current time in the EKF, using the data update at the current time, P_nIs a 4 x 4 matrix; p₀The uncertainty in the first calculation can be represented by a 4-order identity matrix;

i_α(n) represents i at the current time_αObserved values from the Clark transformation module of the current loop;

i_β(n) represents i at the current time_βObserved values from the Clark transformation module of the current loop;

v_α(n) v represents the current time_αAn observed value from a Park inverse transform module of the current loop;

ν_β(n) v represents the current time_βAn observed value from a Park inverse transform module of the current loop;

an angle estimate (i.e., rotor position) representing the current time;

i_α(n-1) represents i at the previous time_αObserving the value;

i_β(n-1) represents i at the previous time_βObserving the value;

v_α(n-1) represents v at the previous time_αObserving the value;

ν_β(n-1) is a value v representing the last time_βObserving the value;

Tc represents the period of each calculation (2.44 us);

r_srepresents the motor resistance (0.63 ohm);

ls represents the motor inductance (0.00277H);

the EKF circuit module design comprises the following processes:

designing a circuit structure according to the formula, wherein the circuit structure is a parallel circuit structure based on FPGA, repeatedly optimizing and designing the circuit structure to determine a final circuit in consideration of resource speed, realizing SIN functions and COS functions in formulas (1) and (2) by using an SIN module and a COS module, realizing addition, multiplication and division in the formulas by using an ADD module, an MUL module and a DIV module, and controlling the sequence of calling an operation module by using a State _ Machine module; because FPGA resources are limited, each step of a State Machine in design can only execute addition/multiplication operation at most once, and 0-7 steps of a State _ Machine module are used for realizing formulas (1, 2, 3 and 4) to obtain

the whole circuit comprises a Counter module, a State _ Machine module, a RAM _ Controller module, a calcium _ Controller module, an SIN module, a COS module, a DIV module, an ADD module and a MUL module;

(1) the Counter module is used for counting, and providing a reset signal for the State _ Machine module every time when 5us is counted; the realization process of the functions is as follows:

① providing a read enable RDEN RAM signal to the RAM Controller module 100ns after the start of each count period, and the read enable lasts 20 clock cycles (400 ns);

② begins executing the state machine, executing 122 clock cycles (2.44us), each step executing 20 ns;

③ RAM _ Controller gets the write enable signal, WREN _ RAM signal lasts 20 clock cycles (400 ns);

④ each cycle is left with 1.7us margin, and each cycle is seen to be 5us in modelsim simulation;

(2) the State _ Machine module is a 122-step State Machine module and is used for coordinating the work of each module, and the function realization process is as follows:

① the input data comprises a clock signal clk, a set signal rst _ n, a trigonometric function flag signal start _ sign;

② outputs are EN _ MUL, EN _ ADD, EN _ DIV, EN _ SIN, EN _ COS, the MUL module, ADD module, DIV module, SIN module, COS module are enabled according to the calculation sequence of the above formula;

③, completing the calculation of the extended Kalman filtering algorithm once each time the state machine is completed by 122 steps;

(3) the RAM _ Controller module is used for calling and controlling the RAM module, and the realization process of the function of the RAM _ Controller module is as follows:

① RAM module is designed by IP core provided by ALTERA, with RAM depth of 16 and width of 16, and is initialized with mif file storing initial data set for extended Kalman algorithm, including P11, P12, P13, P14, P22, P23, P24, P33, P34, P44, ia_n-1，ib_n-1，θ_n-1，Ω_n-1Wherein P11, P12, P13, P14, P22, P23, P24, P33, P34 and P44 represent the oblique square difference matrix in the extended Kalman filter algorithm, i_α(n)、i_β(n), ω (n), θ (n) are calculation data of the last time, and each stored data is a 16-bit signed number;

② RAM _ Controller module is used to control RAM to write or read data in sequence at specific time (see FIG. 6 for RAM _ Controller module structure diagram), the written data comes from the calcium _ Controller module, and the read data is handed to the calcium _ Controller module, SIN module and COS module for calculation;

(4) call _ Controller module

① receiving three enable signals from the state machine to enable the ADD module, MUL module, and DIV module, respectively;

② receiving the stored data in RAM, the output data of ADD, MUL, DIV, SIN, COS modules;

③ is ADD module, MUL module, DIV module for providing data R_s、L_s、i_α(n)、i_β(n)、ω(n)、θ(n)；

④ the EN _ ADD signal bit width is 7 bits, different EN _ ADD signals enable different adder inputs, the EN _ MUL signal bit width is 7 bits, different EN _ MUL signals enable different multiplier inputs, the EN _ DIV signal bit width is 2 bits, different EN _ DIV signals enable different divider inputs;

(5) the SIN module and the COS module are designed based on the LUB method, which requires a ROM module designed by an IP core provided by ALTERA corporation, 15 bits wide and 1024 bits deep, initialized by a mif file, which records sine (cosine) function values from 0 ° to 90 °; the SIN (COS) module is enabled by a state machine, input data of the module is an angle, the angle data is given by the RAM _ Controller module, and an output result is transmitted to the Call _ Controller;

(6) the ADD module, the MUL module and the DIV module are respectively used for calculating addition, multiplication and division of signed fixed point number,

① ADD modules each employ saturating adders to accommodate the possibility that addition may result in overflow,

② consider that for Q15 format numbers, MUL block multiplication requires division of the result by 2^15, i.e. right shift by 15 bits, DIV block division requires multiplication of the result by 2^15, i.e. left shift by 15 bits;

③, it adopts simplified register sequential division to operate, the division design can make the shift and subtraction operands operate in the same clock cycle, but not in different clock cycles, the division is based on that when the division operation sequence starts to operate, the content of dividend register will move to the highest bit, at the same time, it reserves the storage space for quotient bit;

design of digital format:

all numerical values are signed numbers in a Q15 format, the Q15 format is used for processing the calculation of fixed point numbers, the decimal number can be converted into a positive number, and the precision of the Q15 format number is 1/32768.

2. The design method of the circuit structure of the extended kalman filter based on the FPGA according to claim 1, wherein in implementation of the EKF filtering, a period Tc calculated each time is 2.44us, and a resistance r is calculated_sIs 0.63 ohms and the inductance Ls is 0.00277H.

3. The method of claim 1 or 2, wherein the reduced register sequential division is an efficient divider structure, which is based on the fact that at the beginning of the division operation sequence, the contents of the dividend register are moved to the highest bits, while leaving storage space for the quotient bits, and this structure is more efficient in terms of physical resource utilization because it does not use a separate register to store the quotient; the register comprises an extension bit for adjusting initial shift required by the dividend and the divisor and storing a sign bit formed by subtracting the divisor from the dividend, and the register needs to be extended by one bit on the right side to store a first bit formed by quotient calculation; the counter in the data path unit is used in the design to generate the status signal, which is transmitted to the control unit.

Technical Field

The invention relates to a design method of an extended Kalman filter circuit structure, and relates to the field of extended Kalman filter circuit design.

Background

The conventional PMSM motor adopts speed, current and position three-loop control, wherein the position loop control needs to use the current position and the angular speed as parameters of a PI regulator. Because the common sensor is easily interfered by a magnetic field, the magnetic field around the permanent magnet direct current motor is strong, the observed data has large noise and poor stability. And the sensor device is bulky and high in cost. In the industry, various rotor position and speed estimation methods (namely a sensorless method) are adopted to estimate the speed position at the current moment, and the conventional estimation method comprises direct calculation, a sliding mode observation method, a model reference adaptive algorithm, a high-frequency signal injection method, an artificial intelligence method and an extended Kalman filtering method, and the method is designed by the extended Kalman filtering method in consideration of the advantages and disadvantages of various methods and the realizability of the methods on FPGA.

In the past, most of the applications adopt DSP (digital signal processor) to realize Kalman filtering, and the method has the advantages of flexibility, simple programming and capability of directly adopting C language matrix operation, and has the defects that the flexibility is at the expense of efficiency sometimes, and when the required precision is very high, the complexity of a program is increased, so that the real-time requirement is difficult to guarantee. Aiming at the problem that the execution speed of the Kalman filtering algorithm is slow when the general processor is used for realizing the Kalman filtering algorithm, in order to seek better motor control effect, the estimation of the speed position needs to be completed more times in a short time, so the calculation speed of the algorithm is improved as much as possible. The FPGA is used for realizing the structure, mainly because the FPGA drives signals and register transmission by controlling each clock, and the FPGA is executed in parallel, compared with a general processor, the FPGA executes data flow in parallel by a slower clock frequency, and the general processor has poor parallel execution capability although the main frequency is high, and the running speed of an application program on the FPGA can be 100 times faster than that of a traditional CPU (central processing unit) for the same codes. In view of the characteristics of high parallelism and high execution speed of a Field Programmable Gate Array (FPGA), in recent years, preliminary research is being conducted on hardware implementation of a kalman filter algorithm designed in the FPGA. However, no one in the prior art proposes to realize low power consumption of the extended kalman filter algorithm on the FPGA.

Disclosure of Invention

The invention aims to provide an Extended Kalman Filter (EKF) circuit structure design method based on an FPGA (field programmable gate array), which mainly aims at the estimation of the speed and the position of a Permanent Magnet Synchronous Motor (PMSM) during rotation, namely the estimation of the speed and the position of the permanent magnet synchronous direct current motor (PMSM) during rotation without a sensor.

The technical means adopted by the invention for solving the technical problems is as follows:

an FPGA-based extended Kalman filter circuit structure design method is used for realizing a position and speed estimator module in a traditional PMSM motor vector control system, and the output quantity of the extended Kalman filter circuit structure is estimation of angular speed (omega) and angle (theta); the method comprises the following steps:

EKF filtering implementation steps:

(1) set Q_d，R，P₀Initial value, Q_dAnd R initial value is set to 0, P₀Setting the unit matrix as a fourth order unit matrix;

(2) measurement of i from PMSM System_α(n)，i_β(n)，v_α(n)，v_β(n)

(3) Calculated according to the following formula:

(4) calculating P_nFirst, P is calculated_n|n-1The calculation method is as follows:

(5) calculating the Kalman gain K_n：

Wherein the content of the first and second substances,

(6) current, angle and position estimation equation at the current moment:

in the formula:

Q_dprocedural noise representing the prediction/update model;

r represents the uncertainty of an observed value in the EKF, can also be called as an observation error, belongs to sensor attributes and is not dependent on time;

P_n|n-1a predicted value (squared error) representing the uncertainty of the current data in the EKF, which is not updated with the data at the current time;

P_nan updated value representing the predicted value of the uncertainty at the current time in the EKF, using the data update at the current time, P_nIs a 4 x 4 matrix; p₀The uncertainty in the first calculation can be represented by a 4-order identity matrix;

i_α(n) represents i at the current time_αObserved values from the Clark transformation module of the current loop;

i_β(n) represents i at the current time_βObserved values from Clark variation of the current loopChanging a module;

v_α(n) v represents the current time_αAn observed value from a Park inverse transform module of the current loop;

v_β(n) v represents the current time_βAn observed value from a Park inverse transform module of the current loop;

an angular velocity estimate representing a current time;

an angle estimate (i.e., rotor position) representing the current time;

i_α(n-1) represents i at the previous time_αObserving the value;

i_β(n-1) represents i at the previous time_βObserving the value;

v_α(n-1) represents v at the previous time_αObserving the value;

v_β(n-1) represents v at the previous time_βObserving the value;

representing an estimate of angular velocity at a previous time;

representing an angle estimate at a previous time;

the estimated value representing the current time, i.e. the final estimated value after one EKF operation

Tc represents the period of each calculation (2.44 us);

r_srepresents the motor resistance (0.63 ohm);

ls represents the motor inductance (0.00277H);

the EKF circuit module design comprises the following processes:

designing a circuit structure according to the formula, wherein the circuit structure is a parallel circuit structure based on FPGA, repeatedly optimizing and designing the circuit structure to determine a final circuit in consideration of resource speed, realizing SIN functions and COS functions in formulas (1) and (2) by using an SIN module and a COS module, realizing addition, multiplication and division in the formulas by using an ADD module, an MUL module and a DIV module, and controlling the sequence of calling an operation module by using a State _ Machine module; because FPGA resources are limited, each step of a State Machine in design can only execute addition/multiplication operation at most once, and 0-7 steps of a State _ Machine module are used for realizing formulas (1, 2, 3 and 4) to obtain

Steps 8-62 are used to realize the formula (5, 6, 7) to calculate P_n|n-1And 71-111 are used for realizing the formula (8-18) to calculate K_n、P_n112-120 for implementing the equations (19-22) to obtain

In order to store the data calculated by the formulas (19-22), the circuit uses a RAM to store the data;

the whole circuit comprises a Counter module, a State _ Machine module, a RAM _ Controller module, a calcium _ Controller module, an SIN module, a COS module, a DIV module, an ADD module and a MUL module;

(1) the Counter module is used for counting, and providing a reset signal for the State _ Machine module every time when 5us is counted; the realization process of the functions is as follows:

① providing a read enable RDEN RAM signal to the RAM Controller module 100ns after the start of each count period, and the read enable lasts 20 clock cycles (400 ns);

② begins executing the state machine, executing 122 clock cycles (2.44us), each step executing 20 ns;

③ RAM _ Controller gets the write enable signal, WREN _ RAM signal lasts 20 clock cycles (400 ns);

④ each cycle is left with 1.7us margin, and each cycle is seen to be 5us in modelsim simulation;

(2) the State _ Machine module is a 122-step State Machine module and is used for coordinating the work of each module, and the function realization process is as follows:

① the input data comprises a clock signal clk, a set signal rst _ n, a trigonometric function flag signal start _ sign;

② outputs are EN _ MUL, EN _ ADD, EN _ DIV, EN _ SIN, EN _ COS, the MUL module, ADD module, DIV module, SIN module, COS module are enabled according to the calculation sequence of the above formula;

③, completing the calculation of the extended Kalman filtering algorithm once each time the state machine is completed by 122 steps;

(3) the RAM _ Controller module is used for calling and controlling the RAM module, and the realization process of the function of the RAM _ Controller module is as follows:

① RAM module is designed by IP core provided by ALTERA, with RAM depth of 16 and width of 16, and is initialized with mif file storing initial data set for extended Kalman algorithm, including P11, P12, P13, P14, P22, P23, P24, P33, P34, P44, ia_n-1，ib_n-1，θ_n-1，Ω_n-1Wherein P11, P12, P13, P14, P22, P23, P24, P33, P34 and P44 represent the oblique square difference matrix in the extended Kalman filter algorithm, i_α(n)、i_β(n), ω (n), θ (n) are calculation data of the last time, and each stored data is a 16-bit signed number;

② RAM _ Controller module is used to control RAM to write or read data in sequence at specific time (see FIG. 6 for RAM _ Controller module structure diagram), the written data comes from the calcium _ Controller module, and the read data is handed to the calcium _ Controller module, SIN module and COS module for calculation;

(4) call _ Controller module

① receiving three enable signals from the state machine to enable the ADD module, MUL module, and DIV module, respectively;

② receiving the stored data in RAM, the output data of ADD, MUL, DIV, SIN, COS modules;

③ is ADD module, MUL module, DIV module for providing data R_s、L_s、i_α(n)、i_β(n)、ω(n)、θ(n)；

④ the EN _ ADD signal bit width is 7 bits, different EN _ ADD signals enable different adder inputs, the EN _ MUL signal bit width is 7 bits, different EN _ MUL signals enable different multiplier inputs, the EN _ DIV signal bit width is 2 bits, different EN _ DIV signals enable different divider inputs;

(5) the SIN module and the COS module are designed based on the LUB method, which requires a ROM module designed by an IP core provided by ALTERA corporation, 15 bits wide and 1024 bits deep, initialized by a mif file, which records sine (cosine) function values from 0 ° to 90 °; the SIN (COS) module is enabled by a state machine, input data of the module is an angle, the angle data is given by the RAM _ Controller module, and an output result is transmitted to the Call _ Controller;

(6) the ADD module, the MUL module and the DIV module are respectively used for calculating addition, multiplication and division of signed fixed point number,

① ADD modules each employ saturating adders to accommodate the possibility that addition may result in overflow,

② consider that for Q15 format numbers, MUL block multiplication requires division of the result by 2^15, i.e. right shift by 15 bits, DIV block division requires multiplication of the result by 2^15, i.e. left shift by 15 bits;

③, it adopts simplified register sequential division to operate, the division design can make the shift and subtraction operands operate in the same clock cycle, but not in different clock cycles, the division is based on that when the division operation sequence starts to operate, the content of dividend register will move to the highest bit, at the same time, it reserves the storage space for quotient bit;

design of digital format:

all numerical values are signed numbers in a Q15 format, the Q15 format is used for processing the calculation of fixed point numbers, the decimal number can be converted into a positive number, and the precision of the Q15 format number is 1/32768.

In EKF filtering implementation, each calculationHas a period Tc of 2.44us and a resistance r_sIs 0.63 ohms and the inductance Ls is 0.00277H.

The simplified register sequential division is an effective divider structure, which is based on that when a division operation sequence starts to execute, the content of a dividend register needs to move to the highest bit, and meanwhile, a storage space is reserved for the quotient bit, and the structure is more effective in the aspect of physical resource utilization because a separate register is not used for storing the quotient; the register comprises an extension bit for adjusting initial shift required by the dividend and the divisor and storing a sign bit formed by subtracting the divisor from the dividend, and the register needs to be extended by one bit on the right side to store a first bit formed by quotient calculation; the counter in the data path unit is used in the design to generate the status signal, which is transmitted to the control unit.

The invention has the following beneficial technical effects:

the invention is designed for estimating the position angle of the rotor when the permanent magnet synchronous motor rotates, so the invention is designed by combining the advantages of the FPGA circuit structure and the characteristic of less resource occupation of the EKF algorithm. The invention can realize the EKF algorithm on the FPGA, the calculation is carried out for about 20 ten thousand times per second, and the power consumption is lower than that of the traditional DSP for realizing the extended Kalman filtering algorithm. The design mainly aims at the estimation of the speed and the position of a permanent magnet synchronous direct current motor (PMSM) when a sensor is not arranged. The current time speed and position can be estimated without the use of sensors for the PMSM control system.

According to the current, the voltage, the rotor position and the angular speed of the PMSM at the current moment, the position and the angular speed of the PMSM rotor at the next moment are predicted through an extended Kalman filter algorithm (EKF). The design comprises a Counter module, a State _ Machine module, a RAM _ Controller module, a calcium _ Controller module, an SIN module, a COS module, a DIV module, an ADD module and a MUL module. The Counter module is used for counting, the Kalman algorithm can be expanded once according to a fixed period number, the period is set according to an ADC sampling period (5us) in a PMSM control system, the State _ machine is a core part of the whole design and is used for enabling the SIN module, the COS module, the DIV module, the ADD module and the MUL module in sequence according to a specified sequence to complete calculation of EKF, the SIN module and the COS module are used for calculating triangular sine and cosine values of angles, and the DIV module, the ADD module and the MUL module are respectively used for calculating division, addition and multiplication with symbol fixed points. And the RAM _ Controller is used for storing the data generated by the extended Kalman filter algorithm at the last moment.

The hardware implementation method of the Kalman filtering algorithm based on the FPGA is completely suitable for processing position and speed estimation of the permanent magnet synchronous motor.

Drawings

FIG. 1 is a block diagram of a vector control system for a PMSM motor of the present invention;

FIG. 2 is an overall block diagram of the system of the present invention; in the figure, the Counter represents a Counter module, which is a counting module; state _ Machine represents a State _ Machine module and a State Machine module, RAM _ Controller represents a RAM _ Controller module and is a RAM control module, COS represents a COS module and is a COS function calculation module, SIN represents an SIN module and is a SIN function calculation module, a DIV module is a division module, an ADD module is an addition module, a MUL module is a multiplication module, and calute _ Controller is a calculation module and is used for controlling the DIV module, the ADD module and the MUL module.

FIG. 3 is a timing diagram of the circuit structure of the present invention;

FIG. 4 is a modelsim simulation of the present invention;

FIG. 5 is a state machine transition diagram of the present invention;

FIG. 6 is a schematic diagram of the RAM control module circuit of the present invention, WREN is the write enable signal from the Counter module, Address is the Address signal from the RAM _ Counter module, Ian, Ibn, Omega, Theta and P matrices are the data obtained from the state machine module after one computation is completed, where P matrix is a 4 x 4 matrix, and where P matrix is a 4 x 4 matrix₁₂＝P₂₁，P₁₃＝P₃₁，P₁₄＝P₄₁，P₂₃＝P₃₂，P₂₄＝P₄₂，P₃₄＝P₄₃。

FIG. 7 is a schematic diagram of the circuit of the calcium _ Controller module of the present invention, wherein the EN _ DIV, EN _ ADD, EN _ MUL signals come from the state machine module, O _ ADD, O _ MUL, O _ DIV come from ADD, MUL, DIV module, IN1_ ADD, IN2_ ADD, IN1_ MUL, IN2_ MUL, IN1_ DIV, IN2_ DIV are used as the inputs of ADD, MUL, DIV module, respectively.

Fig. 8 is a schematic diagram of simplified register timing division in the present invention, where Load _ words is data to be loaded, Shift _ divded is used to adjust an initial state of a dividend, Shift _ divsor is used to adjust the divisor to be aligned with the dividend, Sub _ and _ Shift is used to subtract a sign bit formed by the divisor and perform a Shift operation, Flush _ divr is division alignment, Xfer _ Rem is data Shift in a register, state _ is _ shsub is a state where a current division state is Shift and subtraction, W1_ is _0 signal is word1 is 0, W2_ is _0 signal is word2 is 0, divr _ is _1 is divisor 1, MSB _ divr is used to indicate a divisor highest, sign _ bit is a sign bit, Max is used to detect when a maximum allowed Shift occurs.

Detailed Description

The implementation of the invention is illustrated below with reference to fig. 1 to 8:

1. PMSM motor vector control system framework

As shown in figure 1^【2】This is a sophisticated PMSM motor control system that implements the position and speed estimator module in the block diagram. The output quantity of the module is speed (omega) and angle (theta), and the output angle and speed are used for a PMSM control system.

2. EKF filtering implementation steps:

(1) set Q_d，R，P₀Initial value, the invention will Q_dAnd R initial value is set to 0, P₀Set as a fourth order identity matrix.

(2) Measurement of i from PMSM System_α(n)，i_β(n),v_α(n),v_β(n), values to be set for modelsim software simulation are according to the literature [2]]To obtain the compound.

(3) Calculated according to the following formula:

wherein the content of the first and second substances,

is the estimated value calculated by the EKF algorithm at the last moment. Tc is the period (2.44us) per calculation, r_sResistance (0.63 ohm), Ls inductance (0.00277H).

(4) Calculating P_nFirst, P is calculated_n|n-1The calculation method is as follows:

(5) calculating the Kalman gain K_n：

Wherein the content of the first and second substances,

(6) current, angle and position estimation equation at the current moment:

3. EKF circuit module design

The circuit structure is designed according to the theory, because the FPGA is a parallel circuit structure, after the circuit structure is repeatedly optimized and designed in consideration of factors such as resource speed, the final structure is as shown in figure 2, and the circuit comprises a Counter module, a State _ Machine module, a RAM _ Controller module, a calcium _ Controller module, an SIN module, a COS module, a DIV module, an ADD module and a MUL module.

(1) The Counter module is used to count and provide a reset signal to the State _ Machine module every 5us counted, as shown in FIG. 3.

① provides the RAM _ Controller module with a read enable RDEN _ RAM signal 100ns after the beginning of each count cycle, and the read enable lasts 20 clock cycles (400 ns).

② begins executing the state machine, executing 122 clock cycles (2.44us), each step for 20 ns.

③ RAM _ Controller gets the write enable signal, WREN _ RAM signal lasts 20 clock cycles (400 ns).

④ each cycle leaves 1.7us of margin, 5us of each cycle can be seen in modelsim simulations, as in fig. 4.

(2) The State _ Machine module is a 122-step State Machine module for coordinating the operation of the various modules.

① the input data includes a clock signal clk, a set signal rst _ n, and a trigonometric function flag signal start _ sign.

② outputs are EN _ MUL, EN _ ADD, EN _ DIV, EN _ SIN, EN _ COS, which can be enabled in the order of the state transition diagram.

③ the state machine completes the calculation of the extended kalman filter algorithm once every time 122 steps are completed, and the detailed state transition diagram is shown in fig. 5.

(3) The RAM _ Controller module is used for calling and controlling the RAM module.

① RAM Module is designed by IP core provided by ALTERA, with a depth of 16 and a width of 16, and is initialized with mif files storing initial data set for extended Kalman algorithm, including P11, P12, P13, P14, P22, P23, P24, P33, P34, P44, ia_n-1，ib_n-1，θ_n-1，_n-1Wherein P11, P12, P13, P14, P22, P23, P24, P33, P34 and P44 represent an oblique square difference matrix in the extended Kalman filter algorithm, ia_n-1，ib_n-1，θ_n-1，Ω_n-1Is the calculated data at the last moment, and each data stored is a 16-bit signed number.

② RAM _ Controller module is used to control RAM to write or read data in sequence at a specific time, the written data comes from the calcium _ Controller module, the read data is delivered to the calcium _ Controller module, the SIN module and the COS module for calculation, the structure of the RAM _ Controller module is shown in FIG. 6.

(4) Call _ Controller module

① receives three enable signals from the state machine to enable the ADD, MUL, and DIV modules, respectively.

② receive the stored data in RAM, ADD, MUL, DIV, SIN, the output data of the COS modules.

③ provide operational data for the three operational modules, as shown in FIG. 7.

The ④ EN _ ADD signal is 7 bits wide, different EN _ ADD signals enable different adder inputs, the EN _ MUL signal is also 7 bits wide, different EN _ MUL signals enable different multiplier inputs, the EN _ DIV signal is 2 bits wide, and different EN _ DIV signals enable different divider inputs.

(5) The SIN and COS modules are designed based on the LUB method, which requires a ROM module designed from an IP core provided by ALTERA corporation, 15 bits wide and 1024 bits deep, which is initialized with a mif file that records sine (cosine) function values from 0 ° to 90 °. The sin (cos) module is enabled by the state machine, the input data of the module is the angle, the angle data is given by the RAM _ Controller module, and the output result is passed to the call _ Controller, as shown in fig. 2.

(6) The ADD module, the MUL module and the DIV module are respectively used for calculating addition, multiplication and division of signed fixed point numbers.

① the ADD modules of the present invention all employ saturating adders in view of the fact that addition may cause overflow.

② consider that for Q15 format numbers, the MUL block multiplication requires the result to be divided by 2^15, i.e., right shifted by 15 bits, and the DIV block division requires the result to be multiplied by 2^15, i.e., left shifted by 15 bits.

③ the present invention adopts a simplified register timing division, as shown in FIG. 8, the design of this division can make the shift and subtraction operands in the same clock cycle, rather than in different clock cycles.

4. Digital format

Since the values of trigonometric functions, currents, voltages, etc. may be fractional or negative, all values in the present invention are signed in the Q15 format. The Q15 format is commonly used for processing the calculation of fixed point number, the decimal number can be converted into a positive number, and the precision of the Q15 format number is 1/32768, which is enough to meet the experimental requirement. Because negative numbers appear in the invention, the calculation module firstly converts the data into original codes and then processes the original codes.

The references cited in the present invention are detailed below:

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