Vertical storage device
阅读说明:本技术 竖直存储器件 (Vertical storage device ) 是由 张中 周文犀 夏志良 于 2019-08-23 设计创作,主要内容包括:本公开内容的各方面提供了一种半导体器件。该半导体器件包括沿垂直于半导体器件的衬底的方向交替地堆叠并且在衬底上方形成堆叠体的栅极层和绝缘层。该半导体器件包括形成于堆叠体的阵列区中的沟道结构的阵列。此外,该半导体器件包括:由衬底上方的连接区中的堆叠体的第一区段形成的第一阶梯,以及由衬底上方的连接区中的堆叠体的第二区段形成的第二阶梯。此外,该半导体器件包括由堆叠体的第一区段形成并且设置在连接区中的第一阶梯和第二阶梯之间的虚设阶梯。(Aspects of the present disclosure provide a semiconductor device. The semiconductor device includes gate layers and insulating layers that are alternately stacked in a direction perpendicular to a substrate of the semiconductor device and form a stacked body over the substrate. The semiconductor device includes an array of channel structures formed in an array region of a stack. Further, the semiconductor device includes: a first step formed by a first section of the stack in the connection region over the substrate, and a second step formed by a second section of the stack in the connection region over the substrate. Further, the semiconductor device includes a dummy step formed by the first section of the stack and disposed between the first step and the second step in the connection region.)
1. A semiconductor device, comprising:
alternately stacking and forming gate layers and insulating layers of a stacked body over a substrate of the semiconductor device in a direction perpendicular to the substrate;
an array of channel structures formed in an array region of the stack;
a first step formed by a first section of the stack in a connection region over the substrate;
a second step formed by a second section of the stack in the connection region over the substrate; and
a dummy step formed by the first section of the stack and disposed between the first step and the second step in the connection region.
2. The semiconductor device of claim 1, further comprising:
a first contact structure formed on the first step and connected to the gate layer in the first section of the stack; and
a second contact structure formed on the second step and connected to the gate layer in the second section of the stack.
3. The semiconductor device of claim 1, wherein the first section of the stack and the second section of the stack have the same number of gate layers.
4. The semiconductor device of claim 1, wherein the first step is formed by a first set of step steps that descend along a first direction, and the second step is formed by a second set of step steps that descend along the first direction.
5. The semiconductor device of claim 4, wherein the dummy step is formed by a set of step steps that descend in a second direction opposite the first direction.
6. The semiconductor device of claim 4, wherein a corresponding set of the first and second steps have the same height.
7. The semiconductor device of claim 4, wherein sidewalls of the dummy step to the second step have a same height as the first step.
8. The semiconductor device of claim 1, further comprising:
a third step formed by a third section of the stack corresponding to a gate top select transistor in the channel structure.
9. The semiconductor device of claim 4, wherein each step of the first and second sets of step steps is formed from a plurality of divided step steps.
10. The semiconductor device of claim 9, wherein the plurality of dividing step steps descend in a third direction perpendicular to the first direction.
11. A method for manufacturing a semiconductor device, comprising:
alternately stacking sacrificial gate layers and insulating layers in a direction perpendicular to a substrate of the semiconductor device to form a stacked body over the substrate;
shaping the sacrificial gate layer and the insulating layer in a first section of the stack in a connection region to form a first step, a second step, and a dummy step in the first section of the stack in a connection region over the substrate, the dummy step disposed between the first step and the second step; and
removing a number of the sacrificial gate layer and the insulating layer of the second step to move the second step into a second section of the stack.
12. The method of claim 11, further comprising:
forming a channel structure in the stack in the array region;
replacing the sacrificial gate layer with a gate layer; and
forming a first contact structure on the first terrace and a second contact structure on the second terrace, the first contact structure connected to the gate layer in the first section of the stack and the second contact structure connected to the gate layer in the second section of the stack.
13. The method of claim 12, wherein the first section of the stack and the second section of the stack have the same number of gate layers.
14. The method of claim 11, wherein shaping the sacrificial gate layer and the insulating layer in the connection region to form the first step, the second step, and the dummy step further comprises:
forming the sacrificial gate layer and the insulating layer in the connection region into the first step having a first set of step steps that descend in a first direction and into the second step having a second set of step steps that descend in the first direction.
15. The method of claim 14, further comprising:
shaping the sacrificial gate layer and the insulating layer in the connection region into the dummy staircase having a dummy set of staircase steps that descend in a second direction opposite the first direction.
16. The method of claim 14, wherein corresponding sets of the first and second steps have the same height.
17. The method of claim 14, wherein removing the number of the sacrificial gate layer and the insulating layer of the second step to move the second step into the second section of the stack comprises:
removing the plurality of sacrificial gate layers and the insulating layer having the same height as the first step.
18. The method of claim 12, further comprising:
the sacrificial gate layer and the insulating layer are shaped to form a step in a third section of the stack corresponding to a top select transistor of the channel structure.
19. The method of claim 14, wherein each step of the first and second sets of step steps is formed from a plurality of divided step steps.
20. The method of claim 19, wherein the plurality of dividing step steps descend in a third direction perpendicular to the first direction.
Background
Semiconductor manufacturers have developed vertical device technologies, such as three-dimensional (3D) NAND flash memory technology, to achieve higher data storage densities without requiring smaller memory cells. In some examples, a 3D NAND memory device includes an array region (also referred to as a core region) and a staircase region. The array region includes a stack of alternating gate layers and insulating layers. A stack of alternating gate and insulating layers is used to form vertically stacked memory cells in the array region. The stepped region includes a respective gate layer in the form of a step so as to form a contact to the respective gate layer. The contacts are used to connect the driver circuitry to the respective gate layer for controlling the stacked memory cells.
Disclosure of Invention
Aspects of the present disclosure provide a semiconductor device. The semiconductor device includes gate layers and insulating layers that are alternately stacked in a direction perpendicular to a substrate of the semiconductor device and form a stacked body over the substrate. The semiconductor device includes an array of channel structures formed in an array region of a stack. In addition, the semiconductor device includes a first step formed by a first section of the stack in the connection region over the substrate, and a second step formed by a second section of the stack in the connection region over the substrate. Further, the semiconductor device includes a dummy step formed by the first section of the stack and disposed between the first step and the second step in the connection region.
According to some aspects of the present disclosure, the semiconductor device includes a first contact structure formed on a first step and connected to a gate layer in a first section of a stack; and a second contact structure formed on the second step and connected to the gate layer in the second section of the stack.
In some examples, the first section of the stack and the second section of the stack have the same number of gate layers.
In some embodiments, the first step is formed by a first set of step steps that descend in a first direction, and the second step is formed by a second set of step steps that descend in the first direction.
In some examples, the dummy staircase is formed from a set of staircase steps that descend in a second direction opposite the first direction.
In some embodiments, the corresponding set of step steps in the first step and the second step have the same height.
In an example, the sidewalls of the dummy step to the second step have the same height as the first step.
According to an aspect of the disclosure, the semiconductor device further includes a third step formed by a third section of the stack corresponding to the gate top select transistor in the channel structure.
In some embodiments, each step of the first and second sets of step steps is formed by a plurality of divided step steps. In an example, the plurality of dividing step steps are lowered in a third direction perpendicular to the first direction.
Aspects of the present disclosure provide a method for manufacturing a semiconductor device. The method includes alternately stacking sacrificial gate layers and insulating layers in a direction perpendicular to a substrate of the semiconductor device to form a stack over the substrate, and shaping the sacrificial gate layers and the insulating layers in a first section of the stack in a connection region to form a first step, a second step, and a dummy step in the first section of the stack in the connection region over the substrate. The dummy ladder is disposed between the first ladder and the second ladder. In addition, the method includes removing the sacrificial gate layer and the insulating layer of the second step to move the second step into a second section of the stack.
According to some aspects of the present disclosure, the method further includes forming a channel structure in the stack in the array region, and replacing the sacrificial gate layer with the gate layer. The method then includes forming a first contact structure on the first step and forming a second contact structure on the second step. The first contact structure is connected to the gate layer in the first section of the stack and the second contact structure is connected to the gate layer in the second section of the stack.
Drawings
Aspects of the disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It is noted that, in accordance with standard practice in the art, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 illustrates a top view of a semiconductor device according to some embodiments of the present disclosure.
Fig. 2 illustrates a top view of a bulk portion in a semiconductor device, according to some embodiments of the present disclosure.
Fig. 3 illustrates a cross-sectional view of a block portion, according to some embodiments of the present disclosure.
Fig. 4 illustrates a close-up view of a portion of a block portion according to some embodiments of the present disclosure.
Fig. 5 illustrates a cross-sectional view of a portion according to some embodiments of the present disclosure.
Fig. 6 shows a flowchart outlining an example of a process for fabricating a semiconductor device according to some embodiments of the present disclosure.
Fig. 7 illustrates an example of a top view of a bulk portion of a semiconductor device during fabrication according to some embodiments of the present disclosure.
Fig. 8 illustrates an example of a top view of a bulk portion of a semiconductor device during fabrication according to some embodiments of the present disclosure.
Fig. 9 illustrates an example of a top view of a bulk portion of a semiconductor device during fabrication according to some embodiments of the present disclosure.
Fig. 10 illustrates an example of a top view of a bulk portion of a semiconductor device during fabrication according to some embodiments of the present disclosure.
Fig. 11 illustrates an example of a top view of a bulk portion of a semiconductor device during fabrication according to some embodiments of the present disclosure.
Fig. 12 illustrates an example of a cross-sectional view of a bulk portion of a semiconductor device during fabrication, according to some embodiments of the present disclosure.
Fig. 13 illustrates an example of a perspective view of a bulk portion of a semiconductor device during fabrication according to some embodiments of the present disclosure.
Fig. 14 illustrates an example of a cross-sectional view of a bulk portion of a semiconductor device during fabrication, according to some embodiments of the present disclosure.
Fig. 15 illustrates an example of a perspective view of a bulk portion of a semiconductor device during fabrication according to some embodiments of the present disclosure.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, forming a first feature over or on a second feature in the following description may include such embodiments: wherein the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Furthermore, spatially relative terms, such as "under … …," "under … …," "under," "over … …," "over," and the like, may be used herein to facilitate describing one element or feature's relationship to another element or elements or feature or features, as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
A three-dimensional (3D) semiconductor memory device may be formed on a substrate including an array region (also referred to as a core region in some examples) for forming a memory cell array and a connection region for forming a connection to a memory cell. For example, the memory cells are formed in an array region as an array of vertical memory cell strings. The vertical memory cell string is formed of gate layers and insulating layers that are alternately stacked. At the connection region, the stack of the gate layer and the insulating layer is patterned into a stepped step to provide a contact pad (pad) region for connecting the gate layer of the memory cell to a word line.
According to some examples, a trim-etch process is used to form the step. The trim-etch process repeatedly performs the trim step and the etch step based on the mask layer. During the trimming step, the mask layer is trimmed to additionally expose new step regions on the stack of alternately stacked (sacrificial) gate layers and insulating layers. During the etching step, the stack is etched based on the mask layer to generate new steps. In some examples, the trim-etch process is performed using reactive ion etching and has a relatively low throughput, such as a relatively low Wafer Per Hour (WPH), and may be a high cost process for 3D memory device fabrication. Further, when the number of step steps is relatively large, the upper step and the lower step have a relatively large height difference in order to etch the lower step. Because of the large height difference, the trim-etch process requires a thicker mask layer, such as a thicker photoresist layer, for the low step terraces, and the need for a thicker mask layer may cause difficulties in, for example, a photolithography process.
Usually, the step is formed by a bearing surface (tread) and a riser surface (riser). In an example, the bearing surface is a portion disposed horizontally between a top edge of the lower riser and a bottom edge of the upper riser, and the riser is a portion disposed vertically between an inner edge of the lower bearing surface and an outer edge of the upper bearing surface. The support surface is a contact pad that may be configured to land one or more contact structures. The riser is a sidewall of the layer stack, e.g. an alternating arrangement of (sacrificial) gate layers and insulating layers. In some examples, the step is comprised of a bearing surface and a lower riser of the bearing surface. The step is measured by the depth and width of the bearing surface and the height of the lower riser surface. The depth of the bearing surface is the distance from the outer edge to the inner edge of the bearing surface. The width of the bearing surface is the distance from one side of the bearing surface to the other. The height of the riser is the vertical distance of the side wall between the underlying bearing surface and the current bearing surface. In the present disclosure, the height of a riser may be measured in terms of a pair of levels. For example, the layer pair is the sum of the thicknesses of the (sacrificial) gate layer and the insulating layer. In some examples, when a step has a height of multiple layer pairs (e.g., four layer pairs, five layer pairs, six layer pairs), the step is referred to as a gang step; when the step has a height of one layer pair, the step is referred to as a division step.
According to some aspects of the present disclosure, a stack of alternately disposed gate layers and insulating layers may be divided into sections. Each section of the stack is further divided into groups. Each component is then divided into divisions (division). Each partition includes a pair of layers. In some embodiments, the step steps leading to different sections may be formed simultaneously (e.g., in the same trim-etch cycle), and then a skiving (chop) process is used to remove the layers and move the step steps of the different sections to the appropriate section layers. Thus, the total number of trim-etch cycles may be reduced. For example, when two segments are used, the total number of trim-etch cycles can be reduced by half, and the difference in height from the upper step to the lower step in the trim-etch process can be reduced by, for example, half. In another example, when three segments are used, the total number of trim-etch cycles can be reduced 2/3, and the height difference from an upper step to a lower step in the trim-etch process can be reduced 2/3. Since the height difference from the upper step to the lower step in the trim-etch process is reduced, the trim-etch process can be easily performed. The process efficiency is improved because the total number of trim-etch cycles is reduced.
Fig. 1 illustrates a top view of a
Further, each
It is noted that the
It is also noted that the
Fig. 2 illustrates a top view of
In the example of fig. 2 and 3, the
It is noted that the
According to some aspects of the present disclosure, the MCG connection region 269 is configured according to a multi-level ladder architecture, such as a three-level ladder architecture. As shown in the examples of fig. 2-5, each
It is noted that in some embodiments, the strings of memory cells in the array are formed in a stack of alternately disposed gate layers and insulating layers. The gate layers form the gates of the top select transistors, the memory cells (e.g., M1-M108 in the string), and the bottom select transistors. In some contexts, M1-M108 is used to refer to a gate layer for a corresponding memory cell (sometimes referred to as a victim gate layer).
Specifically, in some embodiments, the three-level ladder architecture includes a sector level, a group level, and a division level. At the section level, in the example of fig. 2-5, the three-level staircase architecture includes a
Furthermore, in the example of fig. 2-5, the MCG connection region 269 includes a
In some embodiments, the first and
According to some aspects of the present disclosure, the second stepped
It is noted that although in the examples of fig. 2-5, the three-level ladder architecture includes two ladder sections, the number of ladder sections in the three-level ladder architecture should not be limited and may be any suitable number, e.g., three, four, five, etc. It is noted that although in the examples of fig. 2-5, each stepped section includes 9 sets of stepped steps, the number of sets of stepped steps in the stepped section should not be limited and may be any suitable number, e.g., six, seven, eight, ten, etc. It is noted that although in the examples of fig. 2-5, each set of step steps includes 9 dividing step steps, the number of dividing step steps in a set of step steps should not be limited and may be any suitable number, e.g., two, three, four, five, seven, etc.
In some embodiments, a gate last fabrication technique is used, thus forming a gapped structure to help remove the sacrificial gate layer and form the actual gate. In the example of fig. 2-5,
In an example, the
In some examples, the number of slot structures in the
It is noted that in another example, the slot structures 212(B) and 213(B) are not aligned with the slot structures 212(a) and 213 (a). In another example, the number of slot structures in the
In some embodiments, at least some of the slot structures may serve as a common source contact for the array of
In the example of fig. 2-5, and as shown in fig. 4, a top select gate cut 215 may be provided in the middle of each finger section to divide the Top Select Gate (TSG) layer of the memory finger area into two sections, and thereby enable the memory finger area section to be divided into two independently programmable (read/write) pages. Although the erase operation of the 3D NAND memory may be performed at a block level, the read and write operations may be performed at a page level. In some embodiments,
Note that in some examples, top select gate cut 215 does not cut the memory cell gate layer and the bottom select gate layer.
A stepped structure is formed in the
Details of the
For example, the bearing surface dividing the step D6 in the region of the group step G9 provides a contact pad for M1. The bearing surface dividing the step D5 in the region of the gang step G9 provides a contact pad for M2. The bearing surface dividing the step D4 in the region of the gang step G9 provides a contact pad for M3. The bearing surface dividing the step D3 in the region of the gang step G9 provides a contact pad for M4. The bearing surface dividing the step D2 in the region of the gang step G9 provides a contact pad for M5. The bearing surface dividing the step D1 in the region of the gang step G9 provides a contact pad for M6.
Similarly, the bearing surface dividing the step D6 in the region of the group step G8 provides a contact pad for M7. The bearing surface dividing the step D5 in the region of the gang step G8 provides a contact pad for M8. The bearing surface dividing the step D4 in the region of the gang step G8 provides a contact pad for M9. The bearing surface dividing the step D3 in the region of the gang step G8 provides a contact pad for M10. The bearing surface dividing the step D2 in the region of the gang step G8 provides a contact pad for M11. The bearing surface dividing the step D1 in the region of the gang step G8 provides a contact pad for M12.
Similarly, the bearing surface dividing the step D6 in the region of the group step G7 provides a contact pad for M13. The bearing surface dividing the step D5 in the region of the gang step G7 provides a contact pad for M14. The bearing surface dividing the step D4 in the region of the gang step G7 provides a contact pad for M15. The bearing surface dividing the step D3 in the region of the gang step G7 provides a contact pad for M16. The bearing surface dividing the step D2 in the region of the gang step G7 provides a contact pad for M17. The bearing surface dividing the step D1 in the region of the gang step G7 provides a contact pad for M18.
Similarly, the bearing surface dividing the step D6 in the region of the group step G6 provides a contact pad for M19. The bearing surface dividing the step D5 in the region of the gang step G6 provides a contact pad for M20. The bearing surface dividing the step D4 in the region of the gang step G6 provides a contact pad for M21. The bearing surface dividing the step D3 in the region of the gang step G6 provides a contact pad for M22. The bearing surface dividing the step D2 in the region of the gang step G6 provides a contact pad for M23. The bearing surface dividing the step D1 in the region of the gang step G6 provides a contact pad for M24.
Similarly, the bearing surface dividing the step D6 in the region of the group step G5 provides a contact pad for M25. The bearing surface dividing the step D5 in the region of the gang step G5 provides a contact pad for M26. The bearing surface dividing the step D4 in the region of the gang step G5 provides a contact pad for M27. The bearing surface dividing the step D3 in the region of the gang step G5 provides a contact pad for M28. The bearing surface dividing the step D2 in the region of the gang step G5 provides a contact pad for M29. The bearing surface dividing the step D1 in the region of the gang step G5 provides a contact pad for M30.
Similarly, the bearing surface dividing the step D6 in the region of the group step G4 provides a contact pad for M31. The bearing surface dividing the step D5 in the region of the gang step G4 provides a contact pad for M32. The bearing surface dividing the step D4 in the region of the gang step G4 provides a contact pad for M33. The bearing surface dividing the step D3 in the region of the gang step G4 provides a contact pad for M34. The bearing surface dividing the step D2 in the region of the gang step G4 provides a contact pad for M35. The bearing surface dividing the step D1 in the region of the gang step G4 provides a contact pad for M36.
Similarly, the bearing surface dividing the step D6 in the region of the group step G3 provides a contact pad for M37. The bearing surface dividing the step D5 in the region of the gang step G3 provides a contact pad for M38. The bearing surface dividing the step D4 in the region of the gang step G3 provides a contact pad for M39. The bearing surface dividing the step D3 in the region of the gang step G3 provides a contact pad for M40. The bearing surface dividing the step D2 in the region of the gang step G3 provides a contact pad for M41. The bearing surface dividing the step D1 in the region of the gang step G3 provides a contact pad for M42.
Similarly, the bearing surface dividing the step D6 in the region of the group step G2 provides a contact pad for M43. The bearing surface dividing the step D5 in the region of the gang step G2 provides a contact pad for M44. The bearing surface dividing the step D4 in the region of the gang step G2 provides a contact pad for M45. The bearing surface dividing the step D3 in the region of the gang step G2 provides a contact pad for M46. The bearing surface dividing the step D2 in the region of the gang step G2 provides a contact pad for M47. The bearing surface dividing the step D1 in the region of the gang step G2 provides a contact pad for M48.
Similarly, the bearing surface dividing step D6 in the region of group step G1 provides a contact pad for M49 and a contact structure C1 (shown in fig. 5) is formed on the contact pad. The bearing surface dividing the step D5 in the region of the group step G1 provides a contact pad for M50 and a contact structure C2 (shown in fig. 5) is formed on the contact pad. The bearing surface dividing the step D4 in the region of the group step G1 provides a contact pad for M51 and a contact structure C3 (shown in fig. 5) is formed on the contact pad. The bearing surface dividing the step D3 in the region of the group step G1 provides a contact pad for M52 and a contact structure C4 (shown in fig. 5) is formed on the contact pad. The bearing surface dividing the step D2 in the region of the group step G1 provides a contact pad for M53 and a contact structure C5 (shown in fig. 5) is formed on the contact pad. The bearing surface dividing the step D1 in the region of the group step G1 provides a contact pad for M54 and a contact structure C6 (shown in fig. 5) is formed on the contact pad.
It is noted that in some examples, the slot structures, such as shown by
Fig. 6 shows a flowchart outlining an
At S610, sacrificial gate layers and insulating layers are alternately stacked on a substrate to form an initial stack. The substrate may be any suitable substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, and/or a silicon-on-insulator (SOI) substrate. The substrate may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. The group IV semiconductor may include Si, Ge, or SiGe. The substrate may be a bulk wafer or an epitaxial layer. In some examples, the insulating layer is made of an insulating material such as silicon dioxide and the sacrificial layer is made of silicon nitride.
At S620, a step to the gate of the top select transistor is formed. The step to the gate of the top select transistor may be formed by any suitable process. In an example, a step to the gate of the top select transistor may be formed by applying a repeated etch-trim process using a mask layer. Details of the repeated etch-trim process will be described with reference to S630.
Fig. 7 shows an example of a top view of the
Referring back to fig. 6, at S630, divided step steps of the step division pattern are formed in the connection region. In some examples, a mask layer is used and a trimming process is applied on the mask layer to form an etch mask for forming the dividing step.
Fig. 8 shows an example of a top view of
In some embodiments, the
In some embodiments, the etching of the stack is performed by anisotropic etching, such as Reactive Ion Etching (RIE) or other dry etching processes. In some embodiments, the insulating layer is silicon oxide. In this example, the etching of silicon oxide may include RIE using fluorine-based gases, such as carbon fluoride (CF4), hexafluoroethane (C2F6), CHF3, or C3F6, and/or any other suitable gas. In some embodiments, the silicon oxide layer may be removed by a wet chemical, for example, hydrofluoric acid or a mixture of hydrofluoric acid and ethylene glycol. In some embodiments, a timed etch method may be used. In some embodiments, the sacrificial layer is silicon nitride. In this example, the etching of the silicon nitride may include RIE using O2, N2, CF4, NF3, Cl2, HBr, BCl3, and/or combinations thereof. The method and etchant used to remove the single layer stack should not be limited by embodiments of the present disclosure.
The trimming process includes applying an appropriate etch process (e.g., isotropic dry or wet etch) on the
After trimming the
In some embodiments, the topmost level of the initial stack may be covered by an insulating layer. In some embodiments, the topmost level of the initial stack may also be covered by other dielectric materials. A process step of removing the insulating layer and/or other dielectric material may be added to the etch process of each etch-trim cycle to form the dividing step.
After forming the dividing step, the
Fig. 9 shows an example of a top view of the
Referring back to fig. 6, at S640, a set of stepped steps for a plurality of stepped sections (e.g., first stepped
Fig. 10 shows an example of a top view of the
In some embodiments, the set of step steps may be formed by applying a repeated etch-trim process using the
In some embodiments, each set of stair-step steps includes a plurality of layer pairs, e.g., 9 layer pairs in the example. The etching process then etches the appropriate layers (e.g., nine layer pairs of alternating sacrificial and insulating layers) corresponding to the height of the set of step steps.
After forming the set of step steps, the
Fig. 11 shows an example of a top view of the
Fig. 12 shows an example of a cross-sectional view of
Referring back to fig. 6, at S650, a cutting process is performed at the different stepped sections to move the stepped sections to the appropriate section layer. In an example,
In some embodiments, the etching of the pair of layers (including the insulating layer and the sacrificial gate layer) at the
Fig. 14 shows an example of a cross-sectional view of the
It is noted that when more than two sections are used, the cutting process may be repeatedly used on other sections.
Referring back to fig. 6, at S660, a channel structure is formed. In an example, a suitable planarization process is performed to obtain a relatively flat surface. Then, a pattern of channel holes and dummy channel holes is defined in the photoresist and/or hard mask layer using a photolithographic technique, and the pattern is transferred into the stack of sacrificial and insulating layers using an etching technique. Thus, channel holes are formed in the
Then, a channel structure is formed in the channel hole, and a dummy channel structure is formed in the dummy channel hole. In some embodiments, the dummy channel structure may be formed with the channel structure, and thus, the dummy channel structure is formed of the same material as the channel structure. In some embodiments, the dummy channel structure is formed differently than the channel structure.
At S670, a gate slit (also referred to as a slit structure in some examples) is formed. In some embodiments, the gate gap is etched as a trench in the stack. In some examples, the gate gaps in the connection region have the same pitch as the gate gaps in the array region.
At S680, the actual gate is removed. In some embodiments, using a gate slit, one mayThe sacrificial layer is replaced by a gate layer. In an example, an etchant is applied to the sacrificial layer via the gate slit to remove the sacrificial layer. In an example, the sacrificial layer is made of silicon nitride, and hot sulfuric acid (H) is applied via the gate slit2SO4) To remove the sacrificial layer. Further, a gate stack is formed to the transistors in the array region via the gate slits. In an example, a gate stack is formed from a high-k dielectric layer, an adhesive layer, and a metal layer. The high-k dielectric layer may comprise any suitable material that provides a large dielectric constant, such as hafnium oxide (HfO)2) Hafnium silicon oxide (HfSiO)4) Hafnium silicon oxynitride (HfSiON), aluminum oxide (Al)2O3) Lanthanum oxide (La)2O3) Tantalum oxide (Ta)2O5) Yttrium oxide (Y)2O3) Zirconium oxide (ZrO)2) Strontium titanate oxide (SrTiO)3) Zirconium oxide silicon (ZrSiO)4) Hafnium zirconium oxide (HfZrO)4) And the like. The adhesive layer may include a high melting point metal such as titanium (Ti), tantalum (Ta), and nitrides thereof, for example, TiN, TaN, W2N, TiSiN, TaSiN, and the like. The metal layer includes a metal having high conductivity, for example, tungsten (W), copper (Cu), or the like.
At S690, further processing may be performed on the semiconductor device. For example, the gate last process continues to fill the gate gap, e.g., with a spacer material (e.g., silicon oxide) and a common source material (e.g., tungsten), to form a gap structure. In addition, a contact structure may be formed, and a metal trace may be formed.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.