阅读说明：本技术 半导体元件
(Semiconductor device with a plurality of semiconductor chips
) 是由 陈敏璋
易圣涵
吕承轩 于 2019-04-18 设计创作，主要内容包括：一种半导体元件,其包括基板、第一含锆氧化物层、第一金属氧化物层及顶电极。第一含锆氧化物层位于基板上方且具有铁电性或反铁电性。第一金属氧化物层与第一含锆氧化物层接触。第一金属氧化物层的厚度小于第一含锆氧化物层的厚度。顶电极位于第一含锆氧化物层上方。(A semiconductor device includes a substrate, a first zirconium-containing oxide layer, a first metal oxide layer, and a top electrode. The first zirconium-containing oxide layer is located above the substrate and has ferroelectricity or antiferroelectricity. The first metal oxide layer is in contact with the first zirconium-containing oxide layer. The thickness of the first metal oxide layer is less than the thickness of the first zirconium-containing oxide layer. A top electrode is over the first zirconium-containing oxide layer.)
1. A semiconductor device, comprising:
a substrate;
a first zirconium-containing oxide layer over a substrate and having ferroelectricity or antiferroelectricity;
a first metal oxide layer contacting the first zirconium-containing oxide layer, a thickness of the first metal oxide layer being less than a thickness of the first zirconium-containing oxide layer; and
a top electrode over the first zirconium-containing oxide layer.
Technical Field
The present disclosure relates to semiconductor devices.
Background
The sub-threshold swing is characteristic of the current-voltage characteristic of the transistor. In the sub-threshold region, the drain current behaves like an exponentially increasing current of a forward biased diode. A log drain current versus gate voltage curve with fixed drain, source and bulk voltages will show an approximately log linear behavior in this Metal Oxide Semiconductor Field Effect Transistor (MOSFET) operating region. To improve the sub-threshold characteristics, a negative capacitance field effect transistor (NC-FET) using a ferroelectric material has been proposed.
Disclosure of Invention
In some embodiments, a semiconductor device includes a substrate, a first zirconium-containing oxide layer, a first metal oxide layer, and a top electrode. The first zirconium-containing oxide layer is located above the substrate and has ferroelectricity or antiferroelectricity. The first metal oxide layer is in contact with the first zirconium-containing oxide layer. The thickness of the first metal oxide layer is less than the thickness of the first zirconium-containing oxide layer. A top electrode is over the first zirconium-containing oxide layer.
Drawings
The various aspects of the disclosure can be understood from the following detailed description, taken in conjunction with the accompanying drawings. It is noted that the various features of the drawings are not to scale in accordance with standard practice in the industry. In fact, the dimensions of the features described may be arbitrarily increased or reduced for clarity of discussion.
FIGS. 1A and 1B respectively show schematic diagrams illustrating energy versus polarization for ferroelectricity and antiferroelectricity;
FIG. 2A is a schematic diagram showing the transient current integrated during an electric field having a triangular wave, where Ec is the coercive electric field;
FIG. 2B is a schematic diagram of the AC electric field signal, denoted as E (t), as a function of time;
FIG. 2C is a schematic diagram of an exemplary polarization-electric field (P-E) hysteresis loop for a ferroelectric material;
FIG. 3A is a schematic diagram showing the current density versus electric field for antiferroelectric;
FIG. 3B is a graph showing polarization of antiferroelectricity versus electric field;
fig. 4A and 4D are examples of semiconductor structures according to some embodiments of the present disclosure;
FIGS. 4B and 4C are schematic diagrams illustrating a polarization-electric field (P-E) hysteresis loop superimposed on a transient current-electric field (I-E) loop of the semiconductor structure of FIG. 4A;
FIG. 4E is a schematic diagram of a polarization-electric field (P-E) hysteresis loop superimposed on the transient current-electric field (I-E) loop of the semiconductor structure of FIG. 4D;
FIGS. 5A-5C illustrate schematic diagrams of fabricating the semiconductor structure of FIG. 4D in accordance with some embodiments of the present disclosure;
fig. 6A and 6C are examples of semiconductor structures according to some embodiments of the present disclosure;
FIGS. 6B and 6D are schematic diagrams of the semiconductor structures of FIGS. 6A and 6C respectively showing a polarization-electric field (P-E) hysteresis loop superimposed on the transient current-electric field (I-E) loop;
FIGS. 6E and 6F are schematic diagrams of a polarization-electric field (P-E) hysteresis loop superimposed on a transient current-electric field (I-E) loop for the semiconductor structures of FIGS. 4A and 6C, respectively;
FIGS. 7A-7C illustrate schematic diagrams of fabricating the semiconductor structure of FIG. 6A in accordance with some embodiments of the present disclosure;
FIGS. 8A-8D illustrate schematic diagrams of fabricating the semiconductor structure of FIG. 6C in accordance with some embodiments of the present disclosure;
figures 9A and 9C are examples of semiconductor structures according to some embodiments of the present disclosure;
FIGS. 9B and 9D are schematic diagrams of polarization-electric field (P-E) hysteresis loops superimposed on transient current-electric field (I-E) loops for the semiconductor structures of FIGS. 9A and 9C, respectively;
10A-10C illustrate schematic diagrams of fabricating the semiconductor structure of FIG. 9C, according to some embodiments of the present disclosure;
figures 11A and 11C are examples of semiconductor structures according to some embodiments of the present disclosure;
FIGS. 11B and 11D are schematic diagrams of polarization-electric field (P-E) hysteresis loops superimposed on transient current-electric field (I-E) loops for the semiconductor structures of FIGS. 11A and 11C, respectively;
12A, 12C, and 12E are examples of semiconductor structures according to some embodiments of the present disclosure;
12B, 12D, and 12F respectively illustrate polarization-electric field (P-E) hysteresis loops superimposed on transient current-electric field (I-E) loops for the semiconductor structures of FIGS. 12A, 12C, and 12E;
13A-13C illustrate schematic diagrams of fabricating the semiconductor structure of FIG. 12C, according to some embodiments of the present disclosure;
14A-14D illustrate schematic diagrams of fabricating the semiconductor structure of FIG. 12E, in accordance with some embodiments of the present disclosure;
figures 15A and 15C are examples of semiconductor structures according to some embodiments of the present disclosure;
15B and 15D are schematic diagrams of the polarization-electric field (P-E) hysteresis loop superimposed on the transient current-electric field (I-E) loop for the semiconductor structures of FIGS. 15A and 15C, respectively;
16A-16C illustrate schematic diagrams of fabricating the semiconductor structure of FIG. 15C, according to some embodiments of the present disclosure;
figures 17A and 17C are examples of semiconductor structures according to some embodiments of the present disclosure;
FIGS. 17B and 17D are schematic diagrams of polarization-electric field (P-E) hysteresis loops superimposed on transient current-electric field (I-E) loops for the semiconductor structures of FIGS. 17A and 17C, respectively;
FIGS. 17E and 17F are schematic diagrams of polarization-electric field (P-E) hysteresis loops superimposed on transient current-electric field (I-E) loops for the semiconductor structures of FIGS. 17A and 17C, respectively;
FIG. 18 is a flow chart of a method of fabricating a semiconductor structure according to various aspects of the present disclosure;
fig. 19-21 depict schematic cross-sectional views of semiconductor structures corresponding to the flowchart of fig. 18, in accordance with some embodiments; and
fig. 22-56 illustrate cross-sectional schematic views of semiconductor structures, according to some embodiments of the present disclosure.
Detailed Description
The spirit of the present disclosure will be described in detail with reference to the drawings and detailed description, and it will be apparent to one skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the present disclosure after understanding the embodiments of the present disclosure. For example, the description "a feature is formed over or on" a second feature, and embodiments will include the first feature and the second feature being in direct contact; and will also include the first feature and the second feature being in non-direct contact, with additional features being formed between the first and second features. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Furthermore, relative terms such as "below," "lower," "over," or "upper" or the like are used herein to facilitate describing the relationship of one element or feature to another element or feature as illustrated in the figures. Relative terms include different orientations of the device in use or operation in addition to the orientation depicted in the figures. When the device is otherwise positioned (rotated 90 degrees or at other orientations) the orientation used herein with respect to the word "relative" should be interpreted accordingly. The following embodiments disclose ferroelectric (ferroelectric) or antiferroelectric (antiferroelectric) capacitor structures that may be used for negative-capacitance fin field effect transistors (NC-FinFETs) with an elevated sub-threshold swing.
As transistor dimensions shrink, continued voltage reduction (e.g., power supply) is a goal for ultra-low power devices. However, the scaled voltage will encounter a physically limited bottleneck with a sub-threshold swing of 60mV/decade, which is accompanied by a higher off-state leakage current. Negative capacitance field effect transistors (NC-FETs) that introduce negative capacitance into the gate stack of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) would overcome this problem. The negative capacitance may result from the ferroelectricity or antiferroelectricity of the dielectric layers in the gate stack.
Refer to fig. 1A and 1B. Fig. 1A and 1B show the energy versus polarization for ferroelectricity and antiferroelectricity, respectively. As depicted in fig. 1A, a material with ferroelectricity possesses two or more stable states of different non-zero polarization and thus exhibits non-zero polarization without the application of an electric field. Thus, a material having ferroelectricity can be switched between different polarization states by an applied electric field. In contrast, as depicted in fig. 1B, a material with antiferroelectricity has a stable state of zero polarization (non-polar Antiferroelectric (AFE) phase) and two metastable states of non-zero polarization (polar Ferroelectric (FE) phase), and thus exhibits no polarization without the application of an electric field. However, the antiferroelectric material can switch to one of two original metastable states of non-zero polarization (antiferroelectric (AFE) phase- > Ferroelectric (FE) phase) when an electric field is applied. Once the applied electric field is removed, these materials switch back to a stable state of zero polarization (ferroelectric (FE) phase- > Antiferroelectric (AFE) phase).
See fig. 2A-3B. Fig. 2A shows a schematic diagram of the transient current during an electric field with a triangular wave, where Ec is the coercive electric field. FIG. 2B is a graph of the Alternating Current (AC) electric field signal, denoted E (t), as a function of time. Fig. 2C shows a diagram of an exemplary polarization-electric field (P-E) hysteresis loop for a ferroelectric material, where Pr is the residual polarization amount and Ec is the coercive electric field. Fig. 3A shows a plot of current density versus electric field for an antiferroelectric material. The notation "AFE-FE" in the graph represents the switching peak resulting from the transition from the non-polar anti-ferroelectric phase to the polar ferroelectric phase. Fig. 3B shows a plot of polarization of the antiferroelectric material versus the electric field. Ferroelectricity or antiferroelectricity can be measured using dynamic hysteresis measurement using a triangular electric field having a triangular waveform (see fig. 2B), and the amount of polarization can be obtained by integrating the current over time. When a material that is ferroelectric or antiferroelectric undergoes switching between different polarization states, this material causes a sudden change in the switching current and polarization, which corresponds to a peak in the transient current-electric field (I-E) loop (see fig. 2A and 3A) and a steep slope in the polarization-electric field (P-E) hysteresis loop (see fig. 2C and 3B), respectively. The switching process to occur presents an energy barrier to overcome, and therefore occurs when the electric field exceeds a threshold value, which results in a hysteresis behavior in the polarization-electric field (P-E) loop of the ferroelectric or antiferroelectric material.
Once a positive triangular electric field is applied to a material that is ferroelectric, a switching operation occurs if the rising field, also known as the coercive field (Ec), exceeds a threshold value, and corresponds to a steady state switching from positive to negative polarization. If a negative triangular electric field is applied, the polarization sign is reversed. The ferroelectricity shows a transient current-electric field (I-E) loop with two peaks (see fig. 2A) and a single hysteresis polarization-electric field (P-E) loop (see fig. 2C).
In contrast, in the case of materials that are antiferroelectric, two switching operations occur when a positive triangular electric field is applied. The first switching occurs when the rising field exceeds a threshold value (EF) and the material undergoes switching from its non-polar state (AFE phase) to its positively polarized state (FE phase). This switching process is referred to as "electric field induced phase inversion" of the antiferroelectric material. A second switching occurs when the falling field falls to another threshold (EA) that is less than the above-mentioned threshold (EF), and the material switches from its polar state (FE phase) to its non-polar state (AFE phase) (see fig. 3B). When a negative triangular electric field is applied, the polarization sign is reversed. Thus, the antiferroelectric material has an I-E loop (see FIG. 3A) with four peaks and a dual-hysteresis P-E loop (see FIG. 3B).
Modulation of the ferroelectricity or antiferroelectricity of the zirconium-containing oxide material will be provided and will be discussed in more detail below. The hysteresis loops are illustrated in fig. 4B, 4C, 4E, 6B, 6D to 6F, 9B, 9D, 11B, 11D, 12B, 12D, 12F, 15B, 15D, 17B, and 17D to 17F, which respectively depict a first curve 4P1, a first curve 4P2, a first curve 4P3, a first curve 6P1, a first curve 6P2, a first curve 6P3, a first curve 6P4, a first curve 9P1, a first curve 9P2, a first curve 11P1, a first curve 11P2, a first curve 12P1, a first curve 12P2, a first curve 12P3, a first curve 15P1, a first curve 15P2, a first curve 17P 6866P 6, a first curve 3517P 73727, and a first curve 3. The first curve represents polarization charge in microcoulombs per square centimeter (microcoulombs per square centimeter) versus electric field in microvolts per centimeter (microcolumns per centimeter), such as the first curve 4P1 in fig. 4B. A transient current-electric field (I-E) loop corresponding to the ferroelectric structure is also illustrated in fig. 4B, 4C, 4E, 6B, 6D to 6F, 9B, 9D, 11B, 11D, 12B, 12D, 12F, 15B, 15D, 17B, and 17D to 17F, wherein each of the second curve 4J1, 4J2, 4J3, 6J1, 6J2, 6J3, 6J4, 9J1, 9J2, 11J1, 11J2, 12J1, 12J2, 12J3, 15J1, 2, 3517J 3517, 17J 73727, 3617J 27, and 3617J 73727. The second curve represents current density in microamps per square micron versus electric field in microvolts per centimeter, such as the second curve 4J1 in fig. 4B.
Fig. 4A is an example of a semiconductor structure 1 according to some embodiments. As shown in fig. 4A, a bottom electrode 104, a zirconium dioxide layer 106 and a top electrode 108 are sequentially formed over a substrate 102. The combination of the bottom electrode 104, the zirconium dioxide layer 106 and the top electrode 108 serves as a metal-insulator-metal (MIM) capacitor, wherein the bottom electrode 104 and the top electrode 108 are metal layers of the MIM capacitor, and the zirconium dioxide layer 106 is a dielectric layer between the metal layers and has ferroelectricity or antiferroelectricity. In some embodiments, the bottom electrode 104 and/or the top electrode 108 are made of platinum (Pt) or other suitable metal. In some embodiments, substrate 102 is made of silicon or other suitable semiconductor. The substrate 102 may be a silicon substrate having, for example, a p-type dopant (e.g., boron).
Using the equation V ═ 2 α Q +4 β Q derived from the Landau model for ferroelectrics
3) T, and the voltage across the MIM capacitor formed by bottom electrode 104, zirconium dioxide layer 106, and top electrode 108 is calculated, where α and β are anisotropic constants, Q is the surface charge density and T is the ferroelectric (or antiferroelectric) layer thickness when a voltage is applied across the MIM capacitor, the voltage is amplified due to the induced negative voltage across the ferroelectric MIM capacitor, resulting in a sub-threshold swing of less than 60mV/decade when the MIM capacitor is used in a negative capacitance field effect transistor (i.e., NC-FET).
FIGS. 4B and 4C show zirconium dioxide (ZrO) with different thicknesses
2) Illustration of a polarization-electric field (P-E) hysteresis loop superimposed on a transient current-electric field (I-E) loop for a layered semiconductor structure 1Figure (a). In more detail, the graph shown in fig. 4B corresponds to the semiconductor structure 1 having the zirconia layer 106 with a thickness of about 10.3 nm, and the graph shown in fig. 4C corresponds to the semiconductor structure 1 having the zirconia layer 106 with a thickness of about 6.4 nm. Comparing the curves 4P1, 4J1 in fig. 4B with the curves 4P2, 4J2 in fig. 4C, the zirconium dioxide layer 106 having a thickness of about 6.4 nm shows weaker ferroelectricity (e.g., a smaller amount of residual polarization and a wider switching field distribution) than the zirconium dioxide layer 106 having a thickness of about 10.3 nm. Therefore, reducing the size of the zirconium dioxide layer 106 will result in reduced ferroelectricity, as shown in fig. 4B and 4C.
FIG. 4D illustrates another semiconductor structure 2 similar to the semiconductor structure 1, except for the seed layer 110 between the bottom electrode 104 and the zirconium dioxide layer 106. In more detail, the semiconductor structure 2 includes hafnium oxide (HfO)
2) A seed layer 110 formed and underlying the zirconium dioxide layer 106 having a thickness of about 6.4 nanometers. Fig. 4E is a schematic diagram illustrating a polarization-electric field (P-E) hysteresis loop of the semiconductor structure 2 superimposed on the transient current-electric field (I-E) loop. Comparing the curves 4P3, 4J3 in fig. 4E with the curves 4P2, 4J2 in fig. 4C, the ferroelectric and hysteresis behavior of the semiconductor structure 2 is enhanced (e.g., a larger amount of remnant polarization and a narrower switching field distribution) compared to the semiconductor structure 1 without a seed layer. Based on FIG. 4B, FIG. 4C and FIG. 4E, it can be seen that the thin zirconium dioxide (ZrO) is formed
2) The ferroelectricity of the layer (thickness less than 10 nm) is not satisfactory, but hafnium oxide (HfO)
2) Seed layer and direct deposition on hafnium oxide (HfO)
2) Thin zirconium dioxide (ZrO) on seed layers
2) The composite structure of the layers has enhanced ferroelectricity. In addition, the thickness of the seed layer 110 is less than the thickness of the zirconium dioxide layer 106, so that the combined structure of the layer 110 and the layer 106 can have a thickness that is thin enough to meet the requirement of size reduction. In some embodiments, the seed layer 110 has a thickness between about 1 nanometer and about 5 nanometers. For example, the seed layer 110 of the resulting schematic of fig. 4E has a thickness of about 2.3 nm.
Fig. 5A-5C illustrate a schematic diagram of fabricating the semiconductor structure 2 of fig. 4D, according to some embodiments of the present disclosure. As shown in fig. 5A, a bottom electrode 104 is formed over a substrate 102, and a seed layer 110 is formed over the bottom electrode 104. In some embodiments, the bottom electrode 104 is made of platinum (Pt) or other suitable conductive material and is formed using suitable methods such as electroplating, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), and/or combinations thereof.
Including hafnium oxide (HfO) in the seed layer 110
2) In some embodiments, the plasma-enhanced atomic layer deposition (ald; PEALD) to form hafnium oxide (HfO)
2) A seed layer 110. If the process temperature is above about 500 ℃, the seed layer 110 may be intermixed with underlying materials (e.g., the materials of the bottom electrode 104 and the substrate 102) due to the interdiffusion of atoms at high temperatures. If the process temperature is below about 270 ℃, the seed layer 110 may contain defects, such as oxygen vacancies, that would reduce the performance and reliability of the ferroelectric device. For example, the plasma enhanced atomic layer deposition process uses tetra (dimethylamino) hafnium (TDMAH) or Hf [ N (CH) respectively
3)
2]
4) And oxygen plasma as the hafnium and oxygen precursors, respectively.
As illustrated in fig. 5B, the zirconium dioxide layer 106 is formed over the as-deposited seed layer 110 using a suitable method, such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), and/or combinations thereof. In some embodiments, the zirconium dioxide layer 106 may be formed by Plasma Enhanced Atomic Layer Deposition (PEALD) using a process temperature range from about 270 ℃ to about 500 ℃. If the process temperature is above about 500 ℃, the seed layer 110 may intermix with the zirconium dioxide layer 106 due to atomic interdiffusion at the high temperature. If the process temperature is below about 270 ℃, the zirconium dioxide layer 106 may form a crystalline phase that will not have a beneficial effect on ferroelectricity. For example, a Plasma Enhanced Atomic Layer Deposition (PEALD) process uses tetrakis (dimethylamino) zirconium (TDMAH) or Zr [ N (CH), respectively
3)
2]
4) And oxygen plasma as the zirconium and oxygen precursors.
Controlling the deposition of the seed layer 110 and the deposition of the zirconium dioxide layer 106 such that the thickness of the seed layer 110 is less than the thickness of the zirconium dioxide layer 106 is advantageous for reducing the size of the semiconductor structure 2 and improving the ferroelectricity of the zirconium dioxide layer 106. For example, the seed layer 110 may be deposited on the bottom electrode 104 using Atomic Layer Deposition (ALD), and the resulting thickness of the seed layer 110 is in a range from about 1 nanometer to about 5 nanometers. In addition, the zirconium dioxide layer 106 may be deposited on the seed layer 110 using Atomic Layer Deposition (ALD), and the zirconium dioxide layer 106 has a thickness in a range from about 6.4 nanometers to about 10 nanometers.
As shown in fig. 5C, the top electrode 108 is formed over the zirconium dioxide layer 106. The top electrode 108 and the bottom electrode 104 may comprise the same material in some embodiments. For example, the top electrode 108 is made of platinum (Pt) or other suitable conductive material. The top electrode 108 is formed using a deposition process followed by a patterning process. The deposition process may include Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), and/or combinations thereof. The patterning process may comprise suitable lithography and etching techniques.
FIG. 6A illustrates another semiconductor structure 3 similar to semiconductor structure 2, except that the seed layer 112 is made of titanium dioxide (TiO)
2) Rather than hafnium oxide (HfO)
2) And (4) preparing. In more detail, the semiconductor structure 3 includes a zirconium dioxide layer 106 and a titanium dioxide seed layer 112 over the zirconium dioxide layer 106. The zirconium dioxide layer 106 has a thickness of about 6.4 nanometers and the titanium dioxide seed layer 112 has a thickness of about 4.5 nanometers. Fig. 6B shows a schematic diagram of the polarization-electric field (P-E) hysteresis loop of the semiconductor structure 3 superimposed on the transient current-electric field (I-E) loop. Curves 6P1 and 6J1 in fig. 6B show that ferroelectric to antiferroelectric phase transitions are induced in zirconia layer 106 by including titania seed layer 112. Thus, the zirconium dioxide layer 106 having the titanium dioxide seed layer 112 thereunder exhibits antiferroelectricity.
FIG. 6C illustrates another semiconductor structure 4 that is similar to semiconductor structure 3, except for the capping layer 114 between the zirconium dioxide layer 106 and the top electrode 108. In more detail, the semiconductor structure 4 comprises titanium dioxide (TiO)
2) A cover layer made and having a thickness of about 2.7 nm114. In addition, the thickness of the titanium dioxide seed layer 112 in the semiconductor structure 4 is substantially equal to that of titanium dioxide (TiO)
2) The thickness of the cover layer 114 is the same. For example, the thickness of the titanium dioxide seed layer 112 is about 2.7 nm. Fig. 6D shows a schematic diagram of the polarization-electric field (P-E) hysteresis loop of the semiconductor structure 4 superimposed on the transient current-electric field (I-E) loop. Curves 6P2 and 6J2 in FIG. 6D illustrate the inclusion of titanium dioxide (TiO) in the zirconium dioxide layer 106
2) The capping layer induces a ferroelectric to antiferroelectric phase transformation. In other words, in two TiO
2The zirconium dioxide layer 106 between layers 112 and 114 may be antiferroelectric.
Fig. 6E illustrates a diagram of a polarization-electric field (P-E) hysteresis loop superimposed on a transient current-electric field (I-E) loop for another example of the semiconductor structure 1 of fig. 4A. In more detail, the semiconductor structure 1 associated with FIG. 6E includes zirconium dioxide (ZrO) having a thickness of about 12 nanometers
2) And (3) a layer. Fig. 6F shows a schematic diagram of a polarization-electric field (P-E) hysteresis loop superimposed on a transient current-electric field (I-E) loop for another example of semiconductor structure 4. In more detail, the semiconductor structure 4 associated with FIG. 6F includes zirconium dioxide (ZrO) having a thickness of about 12 nanometers
2) A layer, a titanium dioxide seed layer 112 having a thickness of about 5.7 nanometers, and titanium dioxide (TiO) having a thickness of about 5.7 nanometers
2) And a cover layer 114. When comparing the curves 6P3 and 6J3 in FIG. 6E with the curves 6P4 and 6J4 in FIG. 6F, when using zirconium dioxide (ZrO)
2) Titanium dioxide (TiO) having a thickness of about 5.7 nanometers with a layer having a thickness of about 12 nanometers
2) A seed layer and titanium dioxide (TiO) having a thickness of about 5.7 nanometers
2) The capping layer enhances ferroelectric and hysteresis behavior.
Fig. 7A-7C illustrate schematic diagrams of fabricating the semiconductor structure 3 of fig. 6A according to some embodiments of the present disclosure. As shown in fig. 7A, a bottom electrode 104 is formed over a substrate 102, and a seed layer 112 is formed over the bottom electrode 104. In some embodiments, the bottom electrode 104 is made of platinum (Pt) or other suitable conductive material, and is formed using a suitable method, as previously discussed with respect to fig. 5A.
Including titanium dioxide (TiO) in the seed layer 112
2) In some embodiments, the titanium dioxide seed layer 112 may be formed by Plasma Enhanced Atomic Layer Deposition (PEALD) using a process temperature range from about 270 ℃ to about 500 ℃. If the process temperature is above about 500 ℃, the seed layer 112 may be intermixed with underlying materials (e.g., the materials of the bottom electrode 104 and the substrate 102) due to atomic interdiffusion at the high temperature. If the process temperature is below about 270 ℃, the seed layer 112 may contain defects, such as oxygen vacancies, that would reduce the performance and reliability of the ferroelectric device. For example, in some embodiments, a Plasma Enhanced Atomic Layer Deposition (PEALD) process uses tetrakis (dimethylamido) titanium (TDMAT) or Ti [ N (CH)
3)
2]
4) Titanium tetrachloride (TiCl)
4) Titanium methoxide (Ti (OMe)
4Where Me is methyl) as the titanium precursor, and oxygen plasma as the oxygen precursor.
As illustrated in fig. 7B, the zirconium dioxide layer 106 is formed over the as-deposited titanium dioxide seed layer 112 using a suitable method, as previously discussed with respect to fig. 5B.
Controlling the deposition of the titanium dioxide seed layer 112 and the deposition of the zirconium dioxide layer 106 such that the thickness of the titanium dioxide seed layer 112 is less than the thickness of the zirconium dioxide layer 106 is advantageous for reducing the size of the semiconductor structure 3 and improving the ferroelectricity.
As shown in fig. 7C, the top electrode 108 is formed over the zirconium dioxide layer 106. The top electrode 108 and the bottom electrode 104 may comprise the same material in some embodiments. For example, the top electrode 108 is made of platinum (Pt) or other suitable conductive material. As previously discussed with respect to fig. 5C, a deposition process is used followed by a patterning process to form the top electrode 108.
Fig. 8A-8D illustrate schematic diagrams of fabricating the semiconductor structure 4 of fig. 6C, according to some embodiments of the present disclosure. As shown in fig. 8A, a bottom electrode 104 is formed over a substrate 102, and a seed layer 112 is formed over the bottom electrode 104. In some embodiments, the bottom electrode 104 is made of platinum (Pt) or other suitable conductive material, and is formed using a suitable method, as previously discussed with respect to fig. 5A.
Including titanium dioxide (TiO) in the seed layer 112
2) In some embodiments of (a), as previously discussed with respect to figure 7A,the titanium dioxide seed layer 112 may be formed by Plasma Enhanced Atomic Layer Deposition (PEALD) using suitable precursors at suitable temperatures.
As illustrated in fig. 8B, the zirconium dioxide layer 106 is formed over the titanium dioxide seed layer 112 using a suitable method, as previously discussed with respect to fig. 5B.
As shown in fig. 8C, a capping layer 114 is then formed over the zirconium dioxide layer 106. Including titanium dioxide (TiO) in the capping layer 114
2) In some embodiments, the deposition conditions (e.g., temperature and/or precursor) of the capping layer 114 are substantially the same as the deposition conditions of the titanium dioxide seed layer 112. For example, titanium dioxide (TiO) may be formed by Plasma Enhanced Atomic Layer Deposition (PEALD) using a process temperature range from about 270 ℃ to about 500 ℃
2) And a cover layer 114. If the process temperature is above about 500 ℃, titanium dioxide (TiO) may be formed due to atomic interdiffusion at high temperatures
2) The capping layer 114 may be intermixed with the zirconium dioxide layer 106. If the process temperature is below about 270 ℃, titanium dioxide (TiO)
2) The capping layer 114 may contain defects such as oxygen vacancies that would reduce the performance and reliability of the ferroelectric element. For example, in some embodiments, a Plasma Enhanced Atomic Layer Deposition (PEALD) process uses tetrakis (dimethylamido) titanium (TDMAT) or Ti [ N (CH)
3)
2]
4) Titanium tetrachloride (TiCl)
4) Titanium methoxide (Ti (OMe)
4Where Me is methyl) as the titanium precursor, and oxygen plasma as the oxygen precursor.
As shown in FIG. 8D, the top electrode 108 is formed on titanium dioxide (TiO)
2) Over capping layer 114. The top electrode 108 and the bottom electrode 104 may comprise the same material in some embodiments. For example, the top electrode 108 is made of platinum (Pt) or other suitable conductive material. As previously discussed with respect to fig. 5C, a deposition process is used followed by a patterning process to form the top electrode 108.
Fig. 9A illustrates another semiconductor structure 5 similar to semiconductor structure 1, except that bottom electrode 105 is made of titanium nitride (TiN) instead of platinum (Pt). In more detail, the semiconductor structure 5 includes a zirconium dioxide layer 106 deposited on a titanium nitride (TiN) bottom electrode 105 and having a thickness of about 6.4 nanometers. Fig. 9B shows a schematic diagram of the polarization-electric field (P-E) hysteresis loop of the semiconductor structure 5 superimposed on the transient current-electric field (I-E) loop.
FIG. 9C illustrates another semiconductor structure 6 similar to the semiconductor structure 5, except for the capping layer 114 between the zirconium dioxide layer 106 and the top electrode 108. In more detail, the semiconductor structure 6 includes the zirconium dioxide layer 106 and the capping layer 114 over the zirconium dioxide layer 106. The zirconium dioxide layer 106 has a thickness of about 6.4 nanometers. Titanium dioxide (TiO) for the capping layer 114
2) Made and have a thickness of about 5.7 nanometers. FIG. 9D is a schematic diagram of a polarization-electric field (P-E) loop of the semiconductor structure 6. Comparing the curves 9P1, 9J1 in FIG. 9B with the curves 9P2, 9J2 in FIG. 9D, by including titanium dioxide (TiO)
2) Capping layer 114, the antiferroelectric and hysteresis behavior of semiconductor structure 6 and the absence of titanium dioxide (TiO)
2) The semiconductor structure 5 of the capping layer 114 is enhanced in comparison.
Fig. 10A-10C illustrate a schematic diagram of fabricating the semiconductor structure 6 of fig. 9C, according to some embodiments of the present disclosure. As shown in fig. 10A, a bottom electrode 105 is formed over a substrate 102, and a zirconium dioxide layer 106 is formed over the bottom electrode 104. In this embodiment, the bottom electrode 105 is made of titanium nitride (TiN) and is formed using a suitable method such as electroplating, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), and/or combinations thereof.
As shown in fig. 10A, a layer of zirconium dioxide 106 is formed over the bottom electrode 105 using a suitable method, as previously discussed with respect to fig. 5B.
As shown in fig. 10B, a capping layer 114 is formed over the zirconium dioxide layer 106. Including titanium dioxide (TiO) in the capping layer 114
2) In some embodiments, as previously discussed with respect to fig. 8C, titanium dioxide (TiO)
2) The capping layer 114 may be formed by Plasma Enhanced Atomic Layer Deposition (PEALD).
Controlling titanium dioxide (TiO)
2) The deposition of the capping layer 114 and the deposition of the zirconium dioxide layer 106 results in titanium dioxide (TiO)
2) The thickness of the capping layer 114 is less than the thickness of the zirconium dioxide layer 106, which is advantageous for reducing the size of the semiconductor structure 6 and for improving the zirconium dioxide layer106 antiferroelectric properties. For example, the capping layer 114 and the zirconium dioxide layer 106 may be deposited using Atomic Layer Deposition (ALD), the resulting capping layer 114 having a thickness between about 1 nanometer and about 6 nanometers, and the zirconium dioxide layer 106 having a thickness greater than 6 nanometers.
As shown in fig. 10C, the top electrode 108 is formed over the capping layer 114. The top electrode 108 may comprise a different material than the bottom electrode 105. For example, the top electrode 108 comprises platinum (Pt) and the bottom electrode 105 comprises titanium nitride (TiN). In other embodiments, the top electrode 108 may comprise the same material as the bottom electrode 105. For example, the top electrode 108 comprises titanium nitride (TiN) and the bottom electrode 105 also comprises titanium nitride (TiN). As previously discussed with respect to fig. 5C, a deposition process is used followed by a patterning process to form the top electrode 108.
Fig. 11A illustrates another semiconductor structure 7 similar to the semiconductor structure 1, except that the semiconductor structure 7 omits the bottom electrode 104. In more detail, the semiconductor structure 7 includes a substrate 102a having a heavily doped p-type dopant (e.g., boron) in contact with a bottom surface of the zirconium dioxide layer 106. The heavily doped substrate 102a may act as a conductor and thus a bottom electrode due to the heavy dopant concentration. In some embodiments, the zirconium dioxide layer 106 has a thickness of about 6.4 nanometers. Fig. 11B shows a diagram of the polarization-electric field (P-E) hysteresis loop of the semiconductor structure 7 superimposed on the transient current-electric field (I-E) loop. The curves 11P1 and 11J1 in fig. 11B show the paraelectric behavior of the zirconium dioxide layer 106 in contact with the heavily doped substrate 102 a.
FIG. 11C illustrates another semiconductor structure 8 similar to the semiconductor structure 7, except for the seed layer 112 between the substrate 102a and the zirconium dioxide layer 106. In some embodiments, the seed layer 112 is made of titanium dioxide (TiO)
2) Fabricated and have a thickness of about 2.7 nanometers. Fig. 11D illustrates a schematic diagram of the polarization-electric field (P-E) hysteresis loop of the semiconductor structure 8 superimposed on the transient current-electric field (I-E) loop. Curves 11P2 and 11J2 in fig. 11D illustrate the induction of a paraelectric to ferroelectric phase transformation in the zirconia layer 106 by including the titania seed layer 112. That is, the titanium dioxide seed layer 112 between the zirconium dioxide layer 106 and the heavily doped substrate 102a may cause the zirconium dioxide layer 106 ferroelectricity.
Fig. 12A depicts a semiconductor structure 9 according to some embodiments. As shown in fig. 12A, a bottom electrode 104, hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) A layer 116 and a top electrode 108 are sequentially formed over the substrate 102. In some embodiments, hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) Layer 116 has a thickness of about 11.9 nanometers. Bottom electrode 104, hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) The combination of layer 116 and top electrode 108 acts as a MIM capacitor in which hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) Layer 116 is a dielectric layer between metal layer 104 and metal layer 108 and has ferroelectric or antiferroelectric properties. Fig. 12B shows a schematic diagram of the polarization-electric field (P-E) hysteresis loop of the semiconductor structure 9 superimposed on the transient current-electric field (I-E) loop.
FIG. 12C illustrates another semiconductor structure 10 similar to the semiconductor structure 9, except that the bottom electrode 104 is similar to hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) A titanium dioxide seed layer 112 between the layers 116. More specifically, hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) Layer 116 has a thickness of about 11.9 nanometers and titania seed layer 112 has a thickness of about 2.7 nanometers. Fig. 12D is a schematic diagram of the polarization-electric field (P-E) hysteresis loop of the semiconductor structure 10 superimposed on the transient current-electric field (I-E) loop. Comparing the curves 12P1, 12J1 in fig. 12B with the curves 12P2, 12J2 in fig. 12D, the ferroelectric and hysteresis behavior of the semiconductor structure 10 with the titanium dioxide seed layer 112 is comparable to that without TiO
2The semiconductor structure 9 of the seed layer is enhanced in comparison.
FIG. 12E illustrates another semiconductor structure 11 similar to the semiconductor structure 10, except for hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) Titanium dioxide (TiO) between layer 116 and top electrode 108
2) And a cover layer 114. More specifically, hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) The layer 116 has a thickness of about 11.9 nanometers, the titanium dioxide seed layer 112 has a thickness of about 2.7 nanometers, and titanium dioxide (TiO)
2) The capping layer 114 has a thickness of about 2.7 nanometers. FIG. 12F shows a semiconductorSchematic diagram of the polarization-electric field (P-E) hysteresis loop of the bulk structure 11 superimposed on the transient current-electric field (I-E) loop. Comparing the curves 12P1, 12J1 in FIG. 12B with the curves 12P3, 12J3 in FIG. 12F, with titanium dioxide (TiO)
2) Ferroelectric and hysteresis behavior of the semiconductor structure 11 of the capping layer 114 and the titanium dioxide seed layer 112 and absence of titanium dioxide (TiO)
2) Coating and TiO
2The semiconductor structure 9 of the seed layer is enhanced in comparison.
Fig. 13A-13C illustrate a schematic diagram of fabricating the semiconductor structure 10 of fig. 12C, according to some embodiments of the present disclosure. As shown in fig. 13A, a bottom electrode 104 is formed over a substrate 102, and a seed layer 112 is formed over the bottom electrode 104. In some embodiments, the bottom electrode 104 is made of platinum (Pt) or other suitable conductive material, and is formed using a suitable method, as previously discussed with respect to fig. 5A.
Including titanium dioxide (TiO) in the seed layer 112
2) In some embodiments, as previously discussed with respect to fig. 7A, the titanium dioxide seed layer 112 may be formed by Plasma Enhanced Atomic Layer Deposition (PEALD) using suitable precursors at suitable temperatures.
As shown in fig. 13B, hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) Layer 116 is formed over the as-deposited seed layer 112 using a suitable method, such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), and/or combinations thereof. In some embodiments, hafnium zirconium oxide (Hf) may be formed by Plasma Enhanced Atomic Layer Deposition (PEALD) using a process temperature range from about 270 ℃ to about 500 ℃
0.5Zr
0.5O
2) Layer 116. Hafnium zirconium oxide (Hf) if the process temperature is higher than about 500 deg.C
0.5Zr
0.5O
2) The layer 116 may be formed into a crystalline phase that does not contribute to ferroelectricity. Hafnium zirconium oxide (Hf) if the process temperature is lower than about 270 DEG C
0.5Zr
0.5O
2) Layer 116 will not have sufficient crystallinity to exhibit ferroelectric properties. For example, in some embodiments, a Plasma Enhanced Atomic Layer Deposition (PEALD) process uses tetrakis (dimethylamino) zirconium (TDMAZ, Zr [ N (CH) ]
3)
2]
4) As zirconium precursor, tetrakis (dimethyl) is usedAmino) hafnium (TDMAH or Hf [ N (CH) ]
3)
2]
4) As a hafnium precursor, and an oxygen plasma is used as an oxygen precursor.
Controlling the deposition of the titanium dioxide seed layer 112 and hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) The deposition of layer 116 is such that the seed layer 112 has a thickness less than hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) The thickness of layer 116 is advantageous in reducing the size of semiconductor structure 10 and enhancing the ferroelectric properties. For example, the seed layer 112 and the bottom electrode 104 may be deposited using Atomic Layer Deposition (ALD), and the resulting seed layer 112 has a thickness between about 1 nanometer and about 5 nanometers, and hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) Layer 116 has a thickness of between about 5 nanometers and about 12 nanometers.
As shown in FIG. 13C, the top electrode 108 is formed on hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) Above layer 116. The top electrode 108 and the bottom electrode 104 may comprise the same material in some embodiments. For example, the top electrode 108 includes or is made of platinum (Pt) or other suitable conductive material. As previously discussed with respect to fig. 5C, a deposition process is used followed by a patterning process to form the top electrode 108.
Fig. 14A-14D illustrate a schematic diagram of fabricating the semiconductor structure 11 of fig. 12E, according to some embodiments of the present disclosure. As shown in fig. 14A, a bottom electrode 104 is formed over a substrate 102, and a seed layer 112 is formed over the bottom electrode 104. In some embodiments, the bottom electrode 104 is made of platinum (Pt) or other suitable conductive material, and is formed using a suitable method, as previously discussed with respect to fig. 5A.
Including titanium dioxide (TiO) in the seed layer 112
2) In some embodiments, as previously discussed with respect to fig. 7A, the titanium dioxide seed layer 112 may be formed by Plasma Enhanced Atomic Layer Deposition (PEALD) using suitable precursors at suitable temperatures.
As illustrated in FIG. 14B, hafnium zirconium oxide (Hf), as previously discussed with respect to FIG. 13B
0.5Zr
0.5O
2) Layer 116 is deposited using Plasma Enhanced Atomic Layer Deposition (PEALD) at a suitable temperature using a suitable precursorA seed layer 112 is formed over the just-deposited seed layer.
As shown in FIG. 14C, a cap layer 114 is formed on hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) Above layer 116. Including titanium dioxide (TiO) in the capping layer 114
2) In some embodiments, as previously discussed with respect to fig. 8C, titanium dioxide (TiO)
2) The capping layer 114 may be formed by Plasma Enhanced Atomic Layer Deposition (PEALD) using suitable precursors at suitable temperatures.
Controlling the deposition of the seed layer 112, capping layer 114, and hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) The deposition of layer 116 results in a titanium dioxide seed layer 112 and titanium dioxide (TiO)
2) The capping layer 114 has a thickness less than hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) The thickness of the layer 116 is advantageous for reducing the size of the semiconductor structure 11 and enhancing the ferroelectric properties.
As shown in FIG. 14D, the top electrode 108 is formed on titanium dioxide (TiO)
2) Over capping layer 114. The top electrode 108 and the bottom electrode 104 may comprise the same material in some embodiments. For example, the top electrode 108 is made of platinum (Pt) or other suitable conductive material. As previously discussed with respect to fig. 5C, a deposition process is used followed by a patterning process to form the top electrode 108.
Fig. 15A illustrates another semiconductor structure 12 similar to semiconductor structure 9, except that the bottom electrode 105 is made of titanium nitride (TiN) instead of platinum (Pt). Fig. 15B is a schematic diagram of the polarization-electric field (P-E) hysteresis loop of the semiconductor structure 12 superimposed on the transient current-electric field (I-E) loop.
FIG. 15C illustrates another semiconductor structure 13 similar to the semiconductor structure 12, except hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) Titanium dioxide (TiO) between layer 116 and top electrode 108
2) And a cover layer 114. In some embodiments, hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) Layer 116 has a thickness of about 11.9 nanometers and is titanium dioxide (TiO)
2) The capping layer 114 has a thickness of about 2.7 nanometers. FIG. 15D illustrates polarization-electric field (P-E) hysteresis superimposed on the transient current-electric field (I-E) loop for semiconductor structure 13Schematic of the circuit. Comparing the curves 15P1, 15J1 in FIG. 15B with the curves 15P2, 15J2 in FIG. 15D, with titanium dioxide (TiO)
2) The ferroelectricity and hysteresis behavior of the semiconductor structure 13 of the capping layer 114 and the absence of titanium dioxide (TiO)
2) The semiconductor structure 12 of the overlying layer is enhanced in comparison.
Fig. 16A-16C illustrate a schematic diagram of fabricating the semiconductor structure 13 of fig. 15C, according to some embodiments of the present disclosure. As shown in fig. 16A, a bottom electrode 105 is formed over the substrate 102. In some embodiments, the bottom electrode 105 is made of titanium nitride (TiN) and is formed using a suitable method such as electroplating, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), and/or combinations thereof.
Hafnium zirconium oxide (Hf) as previously discussed with respect to FIG. 13B
0.5Zr
0.5O
2) Layer 116 is formed over titanium nitride (TiN) bottom electrode 105 using Plasma Enhanced Atomic Layer Deposition (PEALD) using a suitable precursor at a suitable temperature.
As shown in FIG. 16B, a cap layer 114 is formed on hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) Above layer 116. Including titanium dioxide (TiO) in the capping layer 114
2) In some embodiments, as previously discussed with respect to fig. 8C, titanium dioxide (TiO)
2) The capping layer 114 may be formed by Plasma Enhanced Atomic Layer Deposition (PEALD) using suitable precursors at suitable temperatures.
Controlling titanium dioxide (TiO)
2) Deposition of capping layer 114 and hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) The deposition of layer 116 results in titanium dioxide (TiO)
2) The capping layer 114 has a thickness less than hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) The thickness of layer 116 is advantageous for reducing the size of semiconductor structure 13 and enhancing the ferroelectric properties.
As shown in FIG. 16C, the top electrode 108 is formed on titanium dioxide (TiO)
2) Over capping layer 114. The top electrode 108 and the bottom electrode 105 may comprise the same material in some embodiments. For example, the top electrode 108 is made of titanium nitride (TiN) and the bottom electrode 105 is made of titanium nitride (TiN). In other embodiments, the top electrode 108 may compriseA material different from that of the bottom electrode 105. For example, the top electrode 108 comprises platinum (Pt) and the bottom electrode 105 comprises titanium nitride (TiN). In other embodiments, the top electrode 108 may comprise other suitable conductive materials. As previously discussed with respect to fig. 5C, a deposition process is used followed by a patterning process to form the top electrode 108.
FIG. 17A illustrates another semiconductor structure 14 that is similar to the semiconductor structure 12 illustrated in FIG. 15A, except that the bottom electrode 105 is omitted from the semiconductor structure 14. In more detail, the semiconductor structure 14 includes hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) The bottom surface of layer 116 contacts substrate 102a with a heavily doped p-type dopant (e.g., boron). The heavily doped substrate 102a may act as a conductor and thus a bottom electrode due to the heavy dopant concentration. In some embodiments, hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) Layer 116 has a thickness of about 11.9 nanometers. Fig. 17B shows a schematic diagram of the polarization-electric field (P-E) hysteresis loop of the semiconductor structure 14 superimposed on the transient current-electric field (I-E) loop.
FIG. 17C illustrates another semiconductor structure 15 similar to semiconductor structure 14, except using titanium dioxide (TiO)
2) The titanium dioxide seed layer 112 and titanium dioxide (TiO) are formed
2) The cap layer 114 is located on hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) On opposite sides of layer 116. More specifically, the titanium dioxide seed layer 112 and titanium dioxide (TiO)
2) The capping layer 114 has substantially the same thickness (e.g., about 2.7 nanometers). Fig. 17D shows a schematic diagram of the polarization-electric field (P-E) hysteresis loop of the semiconductor structure 15 superimposed on the transient current-electric field (I-E) loop. Comparing the curves 17P1, 17J1 in FIG. 17B with the curves 17P2, 17J2 in FIG. 17D, there is a titanium dioxide seed layer 112 and titanium dioxide (TiO)
2) Ferroelectric and hysteresis behavior of the semiconductor structure 15 of the capping layer 114 and the absence of TiO
2Seed layer and titanium dioxide (TiO)
2) The semiconductor structure 14 of the overlying layer is enhanced in comparison.
FIG. 17E shows a schematic diagram of a polarization-electric field (P-E) hysteresis loop superimposed on a transient current-electric field (I-E) loop for another example of semiconductor structure 14. In more detail, the semiconductor structure 14 associated with FIG. 17E includes hafnium zirconium oxide (Hf) having a thickness of about 7 nanometers
0.5Zr
0.5O
2) Layer 116. Curves 17P3 and 17J3 in FIG. 17E show hafnium zirconium oxide (Hf) having a thickness of 7 nm and in contact with the heavily doped substrate 102a
0.5Zr
0.5O
2) Layer 116 exhibits paraelectric properties. Fig. 17F shows a schematic diagram of a polarization-electric field (P-E) hysteresis loop superimposed on a transient current-electric field (I-E) loop for another example of the semiconductor structure 15. In more detail, the semiconductor structure 15 associated with FIG. 17F includes hafnium zirconium oxide (Hf) having a thickness of about 7 nanometers
0.5Zr
0.5O
2) A layer 116, a titanium dioxide seed layer 112 having a thickness of about 2.7 nanometers, and titanium dioxide (TiO) having a thickness of about 2.7 nanometers
2) And a cover layer 114. Comparing the curves 17P3, 17J3 in FIG. 17E with the curves 17P4, 17J4 in FIG. 17F due to Hf
0.5Zr
0.5O
2Titanium dioxide (TiO) on opposite sides of layer 116
2) Layer 112 and titanium dioxide (TiO)
2) Layer 114 is induced in hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) A paraelectric to ferroelectric phase transformation in layer 116.
Based on the above discussion, it can be seen that a zirconium-free metal oxide layer (e.g., hafnium oxide (HfO)) can be formed by forming a zirconium-free metal oxide layer in contact with a bottom surface and/or a top surface of a zirconium-containing oxide layer
2) Layer or titanium dioxide (TiO)
2) Layer) to strengthen or condition a zirconium-containing oxide layer, e.g. zirconium dioxide (ZrO)
2) Layer or Hf
0.5Zr
0.5O
2Layer) ferroelectricity or antiferroelectricity. In addition, the thickness of the zirconium-free metal oxide layer can be smaller than that of the zirconium-containing oxide layer, which helps to reduce the size of the semiconductor structure. In addition, because ferroelectricity or antiferroelectricity can be satisfied by including a zirconium-free metal oxide layer, annealing or other heat treatments to promote ferroelectricity or antiferroelectricity of the as-deposited zirconium-containing oxide layer can be omitted. The concept of enhancing the ferroelectricity or antiferroelectricity of a zirconium-containing oxide layer by a thin zirconium-free metal oxide layer can be used in devices such as negative capacitance FinFET (NC-FET), ferroelectric random access memory (FeRAM)In a tunnel junction (FTJ) element or the like. The following embodiments are directed to negative capacitance fin field effect transistors (NC-FETs) using the above concepts.
Field Effect Transistors (FETs) and methods of forming the same are provided according to various exemplary embodiments. Intermediate stages of forming a Field Effect Transistor (FET) are illustrated. Aspects of embodiments are discussed. Like reference numerals are used to refer to like elements throughout the various views and illustrative embodiments.
Examples of negative capacitance fin field effect transistors (NCFETs) and methods of forming the same are described with reference to fig. 18-21. Specifically, fig. 18 is a flow diagram of a method 1000 of fabricating a semiconductor structure with a negative capacitance gate stack in accordance with various aspects of the present disclosure. Additional steps may be provided before, during, and after the method 1000, and some of the described steps may be substituted or eliminated to obtain other embodiments of the method 1000. Fig. 19-21 depict schematic cross-sectional views of semiconductor structures corresponding to the flowchart of fig. 18, in accordance with some embodiments.
Referring to block 1001 of fig. 18 and to fig. 19, a semiconductor structure 16 is provided. The semiconductor structure 16 includes a substrate 102 on which devices are to be formed. In various examples, the substrate 102 comprises an elemental (single element) semiconductor such as silicon or germanium in a crystalline structure; a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; such as soda lime glass, fused silica, fused quartz, and/or calcium fluoride (CaF)
2) And/or combinations thereof.
The substrate 102 may be uniform in composition or may include various layers. The layers may have similar compositions or different compositions, and in various embodiments, some substrate layers have non-uniform compositions to induce device strain and thereby tune device performance. An example of the laminated substrate includes a silicon-on-insulator (SOI) substrate 102. In some such examples, the layers of the substrate 102 may include an insulator such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, and/or other suitable insulator materials. In some embodiments, the substrate 102 may also include various p-type doped regions and/or n-type doped regions performed by processes such as ion implantation and/or ion diffusion.
The semiconductor structure 16 includes a gate dielectric layer 118 formed over the substrate 102. The gate dielectric layer 118 is made of an oxide, such as silicon oxide in some embodiments. In other embodiments, the gate dielectric layer 118 includes one or more high-k dielectric layers (e.g., having a dielectric constant greater than 3.9). For example, the one or more gate dielectric layers 118 may include one or more layers of metal oxides or silicates of hafnium (Hf), aluminum (Al), zirconium (Zr), combinations thereof, and layers thereof. Other suitable materials include metal oxides, metal alloy oxides, and combinations of the foregoing of lanthanum (La), magnesium (Mg), barium (Ba), titanium (Ti), lead (Pb), zirconium (Zr). Exemplary materials include magnesium oxide (MgO)
x) Barium titanate (BaTi)
xO
y) Barium strontium titanate (BaSr)
xTi
yO
z) Lead titanate (PbTi)
xO
y) Lead zirconate titanate (PbZr)
xTi
yO
z) Silicon carbide nitride (SiCN), silicon oxynitride (SiON), silicon nitride (SiN), aluminum oxide (Al)
2O
3) Lanthanum oxide (La)
2O
3) Tantalum oxide (Ta)
2O
3) Yttrium oxide (Y)
2O
3) Hafnium oxide (HfO)
2) Zirconium oxide (ZrO)
2) Germanium oxide (GeO)
2) Hafnium zirconium oxide (HfZrO)
2) Gallium oxide (Ga)
2O
3) Gadolinium oxide (Gd)
2O
3) Tantalum silicon oxide (TaSiO)
2) Titanium oxide (TiO)
2) Hafnium silicon oxynitride (HfSiON), yttrium germanium oxide (YGe)
xO
y) Yttrium silicon oxide (YSi)
xO
y) Lanthanum aluminum oxide (LaAlO)
3) And the like. Methods of forming the gate dielectric layer 118 include molecular-beam deposition (MBD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), and the like.
The bottom electrode 104 is disposed on the gate dielectric layer 118. In some embodiments, the bottom electrode 104 acts as an internal gate or floating gate (floating gate) to average out non-uniform charge in subsequently formed layers and non-uniform charge along the source/drain directionThe bits are distributed. The bottom electrode 104 may be a metal selected from the group consisting of tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), cobalt (Co), palladium (Pd), nickel (Ni), rhenium (Re), iridium (Ir), ruthenium (Ru), platinum (Pt), and zirconium (Zr). In some embodiments, the bottom electrode 104 comprises a metal selected from the group consisting of titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), and ruthenium (Ru). Metal alloys such as titanium-aluminum (Ti-Al), ruthenium-tantalum (Ru-Ta), ruthenium-zirconium (Ru-Zr), platinum-titanium (Pt-Ti), cobalt-nickel (Co-Ni), and nickel-tantalum (Ni-Ta) may be used, and/or metal alloys such as tungsten nitride (WN) may be used
x) Titanium nitride (TiN)
x) Molybdenum nitride (MoN)
x) Tantalum nitride (TaN)
x) And tantalum silicon nitride (TaSi)
xN
y) The metal nitride of (2).
Subsequently, as shown in fig. 19, a first seed layer 120, a first zirconium-containing oxide layer 122, and a top electrode 108 are sequentially formed over the bottom electrode 104. The first seed layer 120 may be a zirconium-free metal oxide layer capable of enhancing or altering the ferroelectricity or antiferroelectricity of the first zirconium-containing oxide layer. A suitable material for the first seed layer 120 may be hafnium oxide (HfO)
2) Titanium dioxide (TiO)
2) Or combinations of the above. Hafnium oxide (HfO)
2) Or titanium dioxide (TiO)
2) The ability to enhance or alter the ferroelectricity or antiferroelectricity of a zirconium-containing oxide is as previously discussed with respect to fig. 4B, 4C, 4E, 6B, 6D-6F, 9B, 9D, 11B, 11D, 12B, 12D, 12F, 15B, 15D, 17B, and 17D-17F.
The first seed layer 120 may be formed by any suitable technique, such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Plasma Enhanced Chemical Vapor Deposition (PECVD), or Plasma Enhanced Atomic Layer Deposition (PEALD). Including titanium dioxide (TiO) in the first seed layer 120
2) In some embodiments, titanium dioxide (TiO) may be formed by Plasma Enhanced Atomic Layer Deposition (PEALD) using a suitable precursor at a suitable temperature, as previously discussed with respect to FIG. 7A
2) A seed layer 120. Including hafnium oxide (HfO) in the first seed layer 120
2) In some embodiments, as described previously with respect to FIG. 5A As discussed, hafnium oxide (HfO) may be formed by Plasma Enhanced Atomic Layer Deposition (PEALD) using suitable precursors at suitable temperatures
2) A seed layer 120. In some embodiments, the thickness of the first seed layer 120 is less than the thickness of the first zirconium containing oxide layer 122. For example, the thickness of the first seed layer 120 is between about 1 nanometer and about 6 nanometers.
In some embodiments, the first zirconium-containing oxide layer 122 is formed from zirconium dioxide (ZrO)
2) Or hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) And (4) preparing. The first zirconium-containing oxide layer 122 may be formed by any suitable technique, such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Plasma Enhanced Chemical Vapor Deposition (PECVD), or plasma enhanced chemical vapor deposition (PEALD). The first zirconium-containing oxide layer 122 comprises zirconium dioxide (ZrO)
2) In some embodiments, zirconium dioxide (ZrO) as previously discussed with respect to FIG. 5B
2) Layer 122 may be formed by plasma enhanced chemical vapor deposition (PEALD) using suitable precursors at suitable temperatures. The first zirconium-containing oxide layer 122 comprises hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) In some embodiments, as previously discussed with respect to FIG. 13B, Hf
0.5Zr
0.5O
2Layer 122 may be formed by plasma enhanced chemical vapor deposition (PEALD) using suitable precursors at suitable temperatures. In some embodiments, the thickness of the first zirconium-containing oxide layer 122 is between about 6 nanometers and about 100 nanometers. In some embodiments, the thickness of the first zirconium-containing oxide layer 122 is between about 6 nanometers and about 20 nanometers to facilitate reducing the size of the semiconductor structure 16.
The top electrode 108 may be of the same material as the bottom electrode 104. Alternatively, the top electrode 108 may have a different material than the bottom electrode 104. The top electrode 108 may be formed by electroplating, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), combinations thereof, and/or other suitable techniques.
Referring to block 1003 of fig. 18 and fig. 20, the gate dielectric layer 118, the bottom electrode 104, the first seed layer 120, the first zirconium containing oxide layer 122, and the top electrode 108 are patterned using suitable lithography and etching techniques. Due to the ferroelectricity or antiferroelectricity of the first zirconium containing oxide layer 122, the gate dielectric layer 118, the bottom electrode 104, the first seed layer 120, the first zirconium containing oxide layer 122, and the top electrode 108 may be referred to as a negative capacitance gate stack of the semiconductor structure 16.
Referring to block 1005 of fig. 18 and 21, portion 124 of substrate 102 may be doped with an n-type dopant (e.g., phosphorus) and used as source/drain regions 124 in some embodiments. The portion of the substrate 102 between the source/drain regions 124 may be referred to as a channel region 126. Opposing source/drain regions 124 are laterally separated by a channel region 126. The flow of carriers through the channel region 126 is controlled by the voltage applied to the top electrode 108. In some embodiments, the source/drain regions 124 may be formed by epitaxial growth of different semiconductor materials for strain effects or other performance enhancements. The substrate 102 is recessed, for example, by etching, and a semiconductor material is epitaxially grown on the recessed regions with in-situ doping to form source/drain regions 124. In some embodiments, the method 1000 may form the gate stack after forming the source/drain regions 124, such as a gate last process. For example, forming a dummy gate; forming source/drain regions 124 on the sides of the dummy gate; and then forming a gate stack including layer 118, layer 104, layer 120, layer 122, and layer 108 to replace the dummy gate by a gate replacement process.
The combination of the first seed layer 120 and the first zirconium-containing oxide layer 122 provides a negative capacitance. Also, the ferroelectric phase of the first zirconium-containing oxide layer 122 may be enhanced or changed into an anti-ferroelectric phase by the first seed layer 120. Thus, semiconductor structure 16 may function as a negative capacitance field effect transistor (NC-FET).
Fig. 22 illustrates another semiconductor structure 16a similar to the semiconductor structure 16, except that the semiconductor structure 16a is supplemented with a first capping layer 128 and the first seed layer 120 is omitted. The first capping layer 128 is between the top electrode 108 and the first zirconium-containing oxide layer 122. The first capping layer 128 may be a zirconium-free metal oxide layer capable of enhancing or altering the ferroelectricity or antiferroelectricity of the first zirconium-containing oxide layer 122. A suitable material for the first capping layer 128 may be hafnium oxide (HfO)
2) Titanium dioxide (TiO)
2) Or a combination thereof.
The first capping layer 128 may be formed by any suitable technique, such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Plasma Enhanced Chemical Vapor Deposition (PECVD), or Plasma Enhanced Atomic Layer Deposition (PEALD). The first cladding layer 128 includes titanium dioxide (TiO)
2) In some embodiments, as previously discussed with respect to fig. 8C, titanium dioxide (TiO)
2) The capping layer 128 may be formed by Plasma Enhanced Chemical Vapor Deposition (PECVD) using suitable precursors at suitable temperatures. Including hafnium oxide (HfO) in the first cap layer 128
2) In some embodiments, hafnium oxide (HfO), as previously discussed with respect to fig. 5A
2) The capping layer 128 may be formed by Plasma Enhanced Chemical Vapor Deposition (PECVD) using suitable precursors at suitable temperatures. In some embodiments, the thickness of the first capping layer 128 is less than the thickness of the first zirconium-containing oxide layer 122. For example, the thickness of the first capping layer 128 is between about 1 nanometer and about 6 nanometers.
The combination of the first seed layer 120 and the first zirconium-containing oxide layer 122 provides a negative capacitance. Also, the ferroelectric phase of the first zirconium-containing oxide layer 122 may be strengthened or changed into an antiferroelectric phase by the first capping layer 128. Thus, the semiconductor structure 16a may function as a negative capacitance field effect transistor (NC-FET).
Fig. 23 illustrates another semiconductor structure 16b that is similar to the semiconductor structure 16, except for the first seed layer 120 between the first zirconium-containing oxide layer 122 and the bottom electrode 104. The combination of the first seed layer 120, the first zirconium-containing oxide layer 122, and the first capping layer 128 provides a negative capacitance. Also, the ferroelectric phase of the first zirconium-containing oxide layer 122 may be enhanced or changed into an antiferroelectric phase by the first seed layer 120 and the first capping layer 128. Thus, semiconductor structure 16b may function as a negative capacitance field effect transistor (NC-FET).
Fig. 24 illustrates another semiconductor structure 17 similar to semiconductor structure 16, except that semiconductor structure 17 omits bottom electrode 104. The first seed layer 120 is in contact with the gate dielectric layer 118 due to the omission of the bottom electrode 104. The combination of the first seed layer 120 and the first zirconium-containing oxide layer 122 provides a negative capacitance. Also, the ferroelectric phase of the first zirconium-containing oxide layer 122 may be enhanced or changed into an anti-ferroelectric phase by the first seed layer 120. Thus, semiconductor structure 17 may function as a negative capacitance field effect transistor (NC-FET).
Fig. 25 illustrates another semiconductor structure 17a similar to the semiconductor structure 16a, except that the semiconductor structure 17a omits the bottom electrode 104. The combination of the first zirconium-containing oxide layer 122 and the first capping layer 128 provides a negative capacitance. Also, the ferroelectric phase of the first zirconium-containing oxide layer 122 may be strengthened or changed into an antiferroelectric phase by the first capping layer 128. Thus, semiconductor structure 17a may function as a negative capacitance field effect transistor (NC-FET).
Fig. 26 illustrates another semiconductor structure 17b that is similar to the semiconductor structure 16b, except that the semiconductor structure 17b omits the bottom electrode 104. The combination of the first seed layer 120, the first zirconium-containing oxide layer 122, and the first capping layer 128 provides a negative capacitance. Also, the ferroelectric phase of the first zirconium-containing oxide layer 122 may be enhanced or changed into an antiferroelectric phase by the first seed layer 120 and the first capping layer 128. Thus, the semiconductor structure 17b may function as a negative capacitance field effect transistor (NC-FET).
Fig. 27 illustrates another semiconductor structure 18 that is similar to semiconductor structure 17, except that semiconductor structure 18 omits gate dielectric layer 118. The first seed layer 120 is in contact with the channel region 126 due to the omission of the gate dielectric layer 118. The combination of the first seed layer 120 and the first zirconium-containing oxide layer 122 provides a negative capacitance. Also, the ferroelectric phase of the first zirconium-containing oxide layer 122 may be enhanced or changed into an anti-ferroelectric phase by the first seed layer 120. Thus, semiconductor structure 18 may function as a negative capacitance field effect transistor (NC-FET).
Fig. 28 illustrates another semiconductor structure 18a similar to semiconductor structure 17a, except that semiconductor structure 18a omits gate dielectric layer 118. The combination of the first zirconium-containing oxide layer 122 and the first capping layer 128 provides a negative capacitance. Also, the ferroelectric phase of the first zirconium-containing oxide layer 122 may be strengthened or changed into an antiferroelectric phase by the first capping layer 128. Thus, semiconductor structure 18a may function as a negative capacitance field effect transistor (NC-FET).
Fig. 29 illustrates another semiconductor structure 18b that is similar to semiconductor structure 17b, except that semiconductor structure 18b omits bottom electrode 104. The combination of the first seed layer 120, the zirconium-containing oxide layer 122, and the first capping layer 128 provides a negative capacitance. Also, the ferroelectric phase of the first zirconium-containing oxide layer 122 may be enhanced or changed into an antiferroelectric phase by the first seed layer 120 and the first capping layer 128. Thus, semiconductor structure 18b may function as a negative capacitance field effect transistor (NC-FET).
Fig. 30 depicts another semiconductor structure 19 that is similar to semiconductor structure 16, except for an intermediate electrode 130, a second seed layer 132, and a second zirconium-containing oxide layer 134. In more detail, the intermediate electrode 130, the second seed layer 132, and the second zirconium-containing oxide layer 134 are sequentially formed over the first zirconium-containing oxide layer 122. The top electrode 108 is over the second zirconium containing oxide layer 134. The middle electrode 130 may be of the same material as the top electrode 108 and the bottom electrode 104. Alternatively, the middle electrode 130 may have a different material than the top electrode 108 and the bottom electrode 104. The intermediate electrode 130 may be formed by electroplating, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), combinations thereof, and/or other suitable techniques. The intermediate electrode 130 may be a metal selected from the group consisting of tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), cobalt (Co), palladium (Pd), nickel (Ni), rhenium (Re), iridium (Ir), ruthenium (Ru), platinum (Pt), and zirconium (Zr). In some embodiments, the bottom electrode 104 comprises a metal selected from the group consisting of titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), and ruthenium (Ru). Metal alloys such as titanium-aluminum (Ti-Al), ruthenium-tantalum (Ru-Ta), ruthenium-zirconium (Ru-Zr), platinum-titanium (Pt-Ti), cobalt-nickel (Co-Ni), and nickel-tantalum (Ni-Ta) may be used, and/or metal alloys such as tungsten nitride (WN) may be used
x) Titanium nitride (TiN)
x) Molybdenum nitride (MoN)
x) Tantalum nitride (TaN)
x) And tantalum silicon nitride (TaSi)
xN
y) The metal nitride of (2). In some embodiments, the intermediate electrode 130 acts as an internal gate or floating gate to average out non-uniform charge in subsequently formed layers and non-uniform potential distribution along the source/drain direction.
The second seed layer 132 may be a zirconium-free metal oxide capable of enhancing or modifying the ferroelectricity or antiferroelectricity of the second zirconium-containing oxide layer 134And (3) a layer. A suitable material for the second seed layer 132 may be hafnium oxide (HfO)
2) Titanium dioxide (TiO)
2) Or combinations of the above. Hafnium oxide (HfO)
2) Or titanium dioxide (TiO)
2) The ability to enhance or alter the ferroelectricity or antiferroelectricity of a zirconium-containing oxide is as previously discussed with respect to fig. 4B, 4C, 4E, 6B, 6D-6F, 9B, 9D, 11B, 11D, 12B, 12D, 12F, 15B, 15D, 17B, and 17D-17F.
The second seed layer 132 may be formed by any suitable technique, such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Plasma Enhanced Chemical Vapor Deposition (PECVD), or Plasma Enhanced Atomic Layer Deposition (PEALD). The second seed layer 132 includes titanium dioxide (TiO)
2) In some embodiments, titanium dioxide (TiO) may be formed by Plasma Enhanced Atomic Layer Deposition (PEALD) using a suitable precursor at a suitable temperature, as previously discussed with respect to FIG. 7A
2) A seed layer 132. Including hafnium oxide (HfO) in the second seed layer 132
2) In some embodiments, hafnium oxide (HfO) may be formed by Plasma Enhanced Atomic Layer Deposition (PEALD) using suitable precursors at suitable temperatures, as previously discussed with respect to fig. 5A
2) A seed layer 132. In some embodiments, the thickness of the second seed layer 132 is less than the thickness of the second zirconium containing oxide layer 134. For example, the thickness of the second seed layer 132 is between about 1 nanometer and about 6 nanometers.
In some embodiments, the second zirconium-containing oxide layer 134 is formed from zirconium dioxide (ZrO)
2) Or hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) And (4) preparing. The second zirconium containing oxide layer 134 may be formed by any suitable technique, such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Plasma Enhanced Chemical Vapor Deposition (PECVD), or Plasma Enhanced Atomic Layer Deposition (PEALD). The second zirconium-containing oxide layer 134 comprises zirconium dioxide (ZrO)
2) In some embodiments, zirconium dioxide (ZrO) as previously discussed with respect to FIG. 5B
2) Layer 134 may be formed by Plasma Enhanced Atomic Layer Deposition (PEALD) using suitable precursors at suitable temperatures. The second zirconium-containing oxide layer 134 comprises hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) In some embodiments of (1), hafnium zirconium oxide (Hf), as previously discussed with respect to FIG. 13B
0.5Zr
0.5O
2) Layer 134 may be formed by Plasma Enhanced Atomic Layer Deposition (PEALD) using suitable precursors at suitable temperatures. In some embodiments, the thickness of the second zirconium-containing oxide layer 134 is between about 6 nanometers and about 100 nanometers. In some embodiments, the thickness of the second zirconium-containing oxide layer 134 is between about 6 nanometers and about 20 nanometers to facilitate reducing the size of the semiconductor structure 16.
The combination of the second zirconium containing oxide layer 134 and the second seed layer 132 provides a negative capacitance. Also, the ferroelectric phase of the second zirconium-containing oxide layer 134 may be enhanced or changed into an anti-ferroelectric phase by the second seed layer 132. Thus, semiconductor structure 19 may function as a negative capacitance field effect transistor (NC-FET).
In some embodiments, the first zirconium containing oxide layer 122 has a ferroelectricity enhanced or altered by the first seed layer 120 and the second zirconium containing oxide layer 134 has an antiferroelectricity enhanced or altered by the second seed layer 132. In other words, in some embodiments, the first seed layer 120 and the first zirconium-containing oxide layer 122 provide a ferroelectric negative capacitance (NC-FE) and the second seed layer 132 and the second zirconium-containing oxide layer 134 provide an antiferroelectric negative capacitance (NC-AFE). In other embodiments, the first seed layer 120 and the first zirconium containing oxide layer 122 provide an antiferroelectric negative capacitance (NC-AFE) and the second seed layer 132 and the second zirconium containing oxide layer 134 provide a ferroelectric negative capacitance (NC-FE). The stack of the gate dielectric layer 118, the bottom electrode 104, the first seed layer 120, the first zirconium containing oxide layer 122, the intermediate electrode 130, the second seed layer 132, the second zirconium containing oxide layer 134, and the top electrode 108 may serve as a gate stack for a negative capacitance field effect transistor (NC-FET). Such an antiferroelectric-ferroelectric (AFE-FE) hybrid negative capacitance field effect transistor (NC-FET) may adjust the threshold of a steep slope Landau (Landau) switch and allow for achieving a steep sub-threshold to achieve a high on-current (Ion) for the negative capacitance field effect transistor (NC-FET).
In some embodiments, ferroelectricity or antiferroelectricity of the zirconium-containing oxide layer 122 and the zirconium-containing oxide layer 134 may be achieved by selecting suitable materials for the zirconium-containing oxide layer 122 and the zirconium-containing oxide layer 134 and the related seed layers 120 and 132, as previously discussed with respect to fig. 4B, 4C, 4E, 6B, 6D-6F, 9B, 9D, 11B, 11D, 12B, 12D, 12F, 15B, 15D, 17B, and 17D-17F.
Fig. 31 illustrates another semiconductor structure 19a similar to the semiconductor structure 19, except that the semiconductor structure 19a is supplemented with a second capping layer 136 and the second seed layer 132 is omitted. In more detail, the second capping layer 136 is located between the top electrode 108 and the second zirconium-containing oxide layer 134. The second capping layer 136 may be a zirconium-free metal oxide layer capable of enhancing or altering the ferroelectricity or antiferroelectricity of the second zirconium-containing oxide layer 134. A suitable material for the second capping layer 136 may be hafnium oxide (HfO)
2) Titanium dioxide (TiO)
2) Or combinations of the above.
The second capping layer 136 may be formed by any suitable technique, such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Plasma Enhanced Chemical Vapor Deposition (PECVD), or Plasma Enhanced Atomic Layer Deposition (PEALD). The second cladding layer 136 includes titanium dioxide (TiO)
2) In some embodiments, as previously discussed with respect to fig. 8C, titanium dioxide (TiO)
2) Capping layer 136 may be formed by Plasma Enhanced Atomic Layer Deposition (PEALD) using suitable precursors at suitable temperatures. Including hafnium oxide (HfO) in the second cladding layer 136
2) In some embodiments, hafnium oxide (HfO), as previously discussed with respect to fig. 5A
2) Capping layer 136 may be formed by Plasma Enhanced Atomic Layer Deposition (PEALD) using suitable precursors at suitable temperatures. In some embodiments, the thickness of the second capping layer 136 is less than the thickness of the second zirconium-containing oxide layer 134. For example, the thickness of the second capping layer 136 is between about 1 nm and about 6 nm. The combination of the second zirconium containing oxide layer 134 and the second capping layer 136 provides a negative capacitance due to the ferroelectric or antiferroelectric properties of the second zirconium containing oxide layer 134 that are altered or enhanced by the second capping layer 136. In some embodiments, the first zirconium-containing oxide layer 122 has ferroelectricity enhanced or altered by the first seed layer 120, and the second zirconium-containing oxide layer 134 has ferroelectricity enhanced or altered by the second seed layer 120The two capping layers 136 enhance or alter the antiferroelectric properties. In other embodiments, the first zirconium containing oxide layer 122 has antiferroelectricity enhanced or altered by the first seed layer 120 and the second zirconium containing oxide layer 134 has ferroelectricity enhanced or altered by the second capping layer 136.
Fig. 32 illustrates another semiconductor structure 19b similar to the semiconductor structure 19, except that a second capping layer 136 is added to the semiconductor structure 19 b. In more detail, the second capping layer 136 is located between the top electrode 108 and the second zirconium-containing oxide layer 134, and the second seed layer 132 is located between the second zirconium-containing oxide layer 134 and the intermediate electrode 130. The combination of the second seed layer 132, the second zirconium containing oxide layer 134, and the second capping layer 136 provides a negative capacitance due to the altered or enhanced ferroelectricity or antiferroelectricity of the second zirconium containing oxide layer 134 through the layer 136 and the layer 136. In some embodiments, the first zirconium containing oxide layer 122 has a ferroelectricity enhanced or altered by the first seed layer 120, and the second zirconium containing oxide layer 134 has an antiferroelectricity enhanced or altered by the second seed layer 132 and the second capping layer 136. In other embodiments, the first zirconium containing oxide layer 122 has antiferroelectricity enhanced or altered by the first seed layer 120 and the second zirconium containing oxide layer 134 has ferroelectricity enhanced or altered by the second seed layer 132 and the second capping layer 136.
Fig. 33 illustrates another semiconductor structure 19c similar to the semiconductor structure 19, except that the semiconductor structure 19c is supplemented with a first capping layer 128 and the first seed layer 120 is omitted. The first capping layer 128 is located between the intermediate electrode 130 and the first zirconium-containing oxide layer 122. The first capping layer 128 may be a zirconium-free metal oxide layer capable of enhancing or altering the ferroelectricity or antiferroelectricity of the first zirconium-containing oxide layer 122. A suitable material for the first capping layer 129 may be hafnium oxide (HfO)
2) Titanium dioxide (TiO)
2) Or combinations of the above. The combination of the first zirconium containing oxide layer 122 and the first capping layer 128 provides a negative capacitance due to the ferroelectric or antiferroelectric properties of the first zirconium containing oxide layer 122 that are altered or enhanced by the first capping layer 128. In some embodiments, the first zirconium-containing oxide layer 122 has been enhanced or altered by the first capping layer 128And the second zirconium-containing oxide layer 134 has an antiferroelectric property enhanced or changed by the second seed layer 132. In other embodiments, the first zirconium containing oxide layer 122 has antiferroelectricity enhanced or altered by the first capping layer 128 and the second zirconium containing oxide layer 134 has ferroelectricity enhanced or altered by the second seed layer 132.
Fig. 34 illustrates another semiconductor structure 19d similar to the semiconductor structure 19a, except that the semiconductor structure 19d is supplemented with the first capping layer 128 and the first seed layer 120 is omitted. The combination of the first zirconium containing oxide layer 122 and the first capping layer 128 provides a negative capacitance due to the ferroelectric or antiferroelectric properties of the first zirconium containing oxide layer 122 that are altered or enhanced by the first capping layer 128. In some embodiments, the first zirconium containing oxide layer 122 has a ferroelectricity enhanced or altered by the first capping layer 128 and the second zirconium containing oxide layer 134 has an antiferroelectricity enhanced or altered by the second capping layer 136. In other embodiments, the first zirconium containing oxide layer 122 has antiferroelectricity enhanced or altered by the first capping layer 128 and the second zirconium containing oxide layer 134 has ferroelectricity enhanced or altered by the second capping layer 136.
Fig. 35 illustrates another semiconductor structure 19e similar to the semiconductor structure 19b, except that the semiconductor structure 19e is supplemented with a first capping layer 128 and the first seed layer 120 is omitted. The combination of the first zirconium containing oxide layer 122 and the first capping layer 128 provides a negative capacitance due to the ferroelectric or antiferroelectric properties of the first zirconium containing oxide layer 122 that are altered or enhanced by the first capping layer 128. In some embodiments, the first zirconium containing oxide layer 122 has a ferroelectricity enhanced or altered by the first capping layer 128, and the second zirconium containing oxide layer 134 has an antiferroelectricity enhanced or altered by the second seed layer 132 and the second capping layer 136. In other embodiments, the first zirconium containing oxide layer 122 has antiferroelectricity enhanced or altered by the first capping layer 128 and the second zirconium containing oxide layer 134 has ferroelectricity enhanced or altered by the second seed layer 132 and the second capping layer 136.
Fig. 36 illustrates another semiconductor structure 19f similar to the semiconductor structure 19, except that the semiconductor structure 19f is added with a first capping layer 128. The combination of the first seed layer 120, the first zirconium containing oxide layer 122, and the first capping layer 128 provides a negative capacitance due to the ferroelectric or antiferroelectric properties of the first zirconium containing oxide layer 122 that are altered or enhanced by the layers 120 and 128 on opposite sides of the first zirconium containing oxide layer 122. In some embodiments, the first zirconium containing oxide layer 122 has a ferroelectricity enhanced or altered by the first seed layer 120 and the first capping layer 128, and the second zirconium containing oxide layer 134 has an antiferroelectricity enhanced or altered by the second seed layer 132. In other embodiments, the first zirconium containing oxide layer 122 has antiferroelectricity enhanced or altered by the first seed layer 120 and the first capping layer 128, and the second zirconium containing oxide layer 134 has ferroelectricity enhanced or altered by the second seed layer 132.
FIG. 37 illustrates another semiconductor structure 19g similar to the semiconductor structure 19a, except that the semiconductor structure 19g is augmented with a first capping layer 128. The combination of the first seed layer 120, the first zirconium containing oxide layer 122, and the first capping layer 128 provides a negative capacitance due to the ferroelectric or antiferroelectric properties of the first zirconium containing oxide layer 122 that are altered or enhanced by the layers 120 and 128 on opposite sides of the first zirconium containing oxide layer 122. In some embodiments, the first zirconium containing oxide layer 122 has a ferroelectricity enhanced or altered by the first seed layer 120 and the first capping layer 128, and the second zirconium containing oxide layer 134 has an antiferroelectricity enhanced or altered by the second capping layer 136. In other embodiments, the first zirconium containing oxide layer 122 has antiferroelectricity enhanced or altered by the first seed layer 120 and the first capping layer 128, and the second zirconium containing oxide layer 134 has ferroelectricity enhanced or altered by the second capping layer 136.
Fig. 38 illustrates another semiconductor structure 19h similar to the semiconductor structure 19b, except that the semiconductor structure 19h is added with a first capping layer 128. The combination of the first seed layer 120, the first zirconium containing oxide layer 122, and the first capping layer 128 provides a negative capacitance due to the ferroelectric or antiferroelectric properties of the first zirconium containing oxide layer 122 that are altered or enhanced by the layers 120 and 128 on opposite sides of the first zirconium containing oxide layer 122. In some embodiments, the first zirconium containing oxide layer 122 has ferroelectricity enhanced or altered by the first seed layer 120 and the second capping layer 136, and the second zirconium containing oxide layer 134 has antiferroelectricity enhanced or altered by the second seed layer 132 and the second capping layer 136. In other embodiments, the first zirconium containing oxide layer 122 has antiferroelectricity enhanced or altered by the first seed layer 120 and the first capping layer 128, and the second zirconium containing oxide layer 134 has ferroelectricity enhanced or altered by the second seed layer 132 and the second capping layer 136.
Fig. 39 illustrates another semiconductor structure 20 similar to the semiconductor structure 19, except that the semiconductor structure 20 omits the bottom electrode 104 and the intermediate electrode 130. In more detail, the second seed layer 132 is in contact with the top surface of the first zirconium-containing oxide layer 122. In some embodiments, the first zirconium containing oxide layer 122 has a ferroelectricity enhanced or altered by the first seed layer 120 and the second zirconium containing oxide layer 134 has an antiferroelectricity enhanced or altered by the second seed layer 132. In other embodiments, the first zirconium containing oxide layer 122 has antiferroelectricity enhanced or altered by the first seed layer 120 and the second zirconium containing oxide layer 134 has ferroelectricity enhanced or altered by the second seed layer 132.
Fig. 40 illustrates another semiconductor structure 20a similar to the semiconductor structure 20, except that the semiconductor structure 20a is supplemented with a second capping layer 136 and the second seed layer 132 is omitted. In more detail, the second zirconium containing oxide layer 134 is in contact with the top surface of the first zirconium containing oxide layer 122. In some embodiments, the first zirconium containing oxide layer 122 has a ferroelectricity enhanced or altered by the first seed layer 120 and the second zirconium containing oxide layer 134 has an antiferroelectricity enhanced or altered by the second capping layer 136. In other embodiments, the first zirconium containing oxide layer 122 has antiferroelectricity enhanced or altered by the first seed layer 120 and the second zirconium containing oxide layer 134 has ferroelectricity enhanced or altered by the second capping layer 136.
FIG. 41 illustrates another semiconductor structure 20b that is similar to the semiconductor structure 20, except that a second cap layer 136 is added to the semiconductor structure 20 b. In some embodiments, the second capping layer 136 is located between the top electrode 108 and the second zirconium-containing oxide layer 134. In some embodiments, the first zirconium containing oxide layer 122 has a ferroelectricity enhanced or altered by the first seed layer 120, and the second zirconium containing oxide layer 134 has an antiferroelectricity enhanced or altered by the second seed layer 132 and the second capping layer 136. In other embodiments, the first zirconium containing oxide layer 122 has antiferroelectricity enhanced or altered by the first seed layer 120 and the second zirconium containing oxide layer 134 has ferroelectricity enhanced or altered by the second seed layer 132 and the second capping layer 136.
Fig. 42 illustrates another semiconductor structure 20c that is similar to the semiconductor structure 20, except that the semiconductor structure 20c is supplemented with a first capping layer 128 and the first seed layer 120 is omitted. In some embodiments, the second seed layer 132 is in contact with the top surface of the first capping layer 128. In some embodiments, the first zirconium containing oxide layer 122 has a ferroelectricity enhanced or altered by the first capping layer 128 and the second zirconium containing oxide layer 134 has an antiferroelectricity enhanced or altered by the second seed layer 132. In other embodiments, the first zirconium containing oxide layer 122 has antiferroelectricity enhanced or altered by the first capping layer 128 and the second zirconium containing oxide layer 134 has ferroelectricity enhanced or altered by the second seed layer 132.
Fig. 43 illustrates another semiconductor structure 20d similar to the semiconductor structure 20a, except that the semiconductor structure 20d is supplemented with a first capping layer 128 and the first seed layer 120 is omitted. In some embodiments, the second zirconium-containing oxide layer 134 is in contact with the top surface of the first capping layer 128. In some embodiments, the first zirconium containing oxide layer 122 has a ferroelectricity enhanced or altered by the first capping layer 128 and the second zirconium containing oxide layer 134 has an antiferroelectricity enhanced or altered by the second capping layer 136. In other embodiments, the first zirconium containing oxide layer 122 has antiferroelectricity enhanced or altered by the first capping layer 128 and the second zirconium containing oxide layer 134 has ferroelectricity enhanced or altered by the second capping layer 136.
Fig. 44 illustrates another semiconductor structure 20e similar to the semiconductor structure 20e, except that the semiconductor structure 20e is supplemented with the first capping layer 128 and the first seed layer 120 is omitted. In some embodiments, the second seed layer 132 is in contact with the top surface of the first capping layer 128. In some embodiments, the first zirconium containing oxide layer 122 has a ferroelectricity enhanced or altered by the first capping layer 128, and the second zirconium containing oxide layer 134 has an antiferroelectricity enhanced or altered by the second seed layer 132 and the second capping layer 136. In other embodiments, the first zirconium containing oxide layer 122 has antiferroelectricity enhanced or altered by the first capping layer 128 and the second zirconium containing oxide layer 134 has ferroelectricity enhanced or altered by the second seed layer 132 and the second capping layer 136.
FIG. 45 illustrates another semiconductor structure 20f that is similar to the semiconductor structure 20, except that the semiconductor structure 20f is supplemented with a first capping layer 128. In some embodiments, the second seed layer 132 is in contact with the top surface of the first capping layer 128. In some embodiments, the first zirconium containing oxide layer 122 has a ferroelectricity enhanced or modified by the first seed layer 120 and the first capping layer 128, and the second zirconium containing oxide layer 134 has an antiferroelectricity enhanced or modified by the second seed layer 132. In other embodiments, the first zirconium containing oxide layer 122 has antiferroelectricity enhanced or altered by the first seed layer 120 and the first capping layer 128, and the second zirconium containing oxide layer 134 has ferroelectricity enhanced or altered by the second seed layer 132.
FIG. 46 illustrates another semiconductor structure 20g that is similar to the semiconductor structure 20a, except that the semiconductor structure 20g is augmented with a first capping layer 128. In some embodiments, the second zirconium-containing oxide layer 134 is in contact with the top surface of the first capping layer 128. In some embodiments, the first zirconium containing oxide layer 122 has a ferroelectricity enhanced or altered by the first seed layer 120 and the first capping layer 128, and the second zirconium containing oxide layer 134 has an antiferroelectricity enhanced or altered by the second capping layer 136. In other embodiments, the first zirconium containing oxide layer 122 has antiferroelectricity enhanced or altered by the first seed layer 120 and the first capping layer 128, and the second zirconium containing oxide layer 134 has ferroelectricity enhanced or altered by the second capping layer 136.
FIG. 47 illustrates another semiconductor structure 20h that is similar to the semiconductor structure 20b, except that the semiconductor structure 20h is augmented with a first capping layer 128. In some embodiments, the second seed layer 132 is in contact with the top surface of the first capping layer 128. In some embodiments, the first zirconium containing oxide layer 122 has ferroelectricity enhanced or altered by the first seed layer 120 and the first capping layer 128, and the second zirconium containing oxide layer 134 has antiferroelectricity enhanced or altered by the second seed layer 132 and the second capping layer 136. In other embodiments, the first zirconium containing oxide layer 122 has antiferroelectricity enhanced or altered by the first seed layer 120 and the first capping layer 128, and the second zirconium containing oxide layer 134 has ferroelectricity enhanced or altered by the second seed layer 132 and the second capping layer 136.
Fig. 48 illustrates another semiconductor structure 21 similar to the semiconductor structure 20, except that the semiconductor structure 21 omits the gate dielectric layer 118. In some embodiments, the first seed layer 120 is in contact with the channel region 126 of the substrate 102. In some embodiments, the first zirconium containing oxide layer 122 has a ferroelectricity enhanced or altered by the first seed layer 120 and the second zirconium containing oxide layer 134 has an antiferroelectricity enhanced or altered by the second seed layer 132. In some other embodiments, the first zirconium containing oxide layer 122 has antiferroelectricity enhanced or altered by the first seed layer 120 and the second zirconium containing oxide layer 134 has ferroelectricity enhanced or altered by the second seed layer 132.
Fig. 49 illustrates another semiconductor structure 21a similar to the semiconductor structure 21, except that the semiconductor structure 21a is added with a second capping layer 136 and the second seed layer 132 is omitted. In some embodiments, the second zirconium containing oxide layer 134 is in contact with the top surface of the first zirconium containing oxide layer 122. In some embodiments, the first zirconium containing oxide layer 122 has a ferroelectricity enhanced or altered by the first seed layer 120 and the second zirconium containing oxide layer 134 has an antiferroelectricity enhanced or altered by the second capping layer 136. In some other embodiments, the first zirconium containing oxide layer 122 has antiferroelectricity enhanced or altered by the first seed layer 120 and the second zirconium containing oxide layer 134 has ferroelectricity enhanced or altered by the second capping layer 136.
Fig. 50 illustrates another semiconductor structure 21b similar to the semiconductor structure 21, except that a second capping layer 136 is added to the semiconductor structure 21 b. In some embodiments, the first zirconium containing oxide layer 122 has a ferroelectricity enhanced or altered by the first seed layer 120, and the second zirconium containing oxide layer 134 has an antiferroelectricity enhanced or altered by the second seed layer 132 and the second capping layer 136. In some other embodiments, the first zirconium containing oxide layer 122 has antiferroelectricity enhanced or altered by the first seed layer 120 and the second zirconium containing oxide layer 134 has ferroelectricity enhanced or altered by the second seed layer 132 and the second capping layer 136.
Fig. 51 illustrates another semiconductor structure 21c similar to the semiconductor structure 21, except that the semiconductor structure 21c is supplemented with a first capping layer 128 and the first seed layer 120 is omitted. In some embodiments, the first zirconium containing oxide layer 122 has a ferroelectricity enhanced or altered by the first capping layer 128 and the second zirconium containing oxide layer 134 has an antiferroelectricity enhanced or altered by the second seed layer 132. In some other embodiments, the first zirconium containing oxide layer 122 has antiferroelectricity enhanced or altered by the first capping layer 128 and the second zirconium containing oxide layer 134 has ferroelectricity enhanced or altered by the second seed layer 132.
Fig. 52 illustrates another semiconductor structure 21d similar to the semiconductor structure 21a, except that the semiconductor structure 21d is added with the first capping layer 128 and the first seed layer 120 is omitted. In some embodiments, the first zirconium containing oxide layer 122 has a ferroelectricity enhanced or altered by the first capping layer 128 and the second zirconium containing oxide layer 134 has an antiferroelectricity enhanced or altered by the second capping layer 136. In some other embodiments, the first zirconium containing oxide layer 122 has antiferroelectricity enhanced or altered by the first capping layer 128 and the second zirconium containing oxide layer 134 has ferroelectricity enhanced or altered by the second capping layer 136.
Fig. 53 illustrates another semiconductor structure 21e similar to the semiconductor structure 21b, except that the semiconductor structure 21e is added with the first capping layer 128 and the first seed layer 120 is omitted. In some embodiments, the first zirconium containing oxide layer 122 has a ferroelectricity enhanced or altered by the first capping layer 128, and the second zirconium containing oxide layer 134 has an antiferroelectricity enhanced or altered by the second seed layer 132 and the second capping layer 136. In some other embodiments, the first zirconium containing oxide layer 122 has antiferroelectricity enhanced or altered by the first capping layer 128 and the second zirconium containing oxide layer 134 has ferroelectricity enhanced or altered by the second seed layer 132 and the second capping layer 136.
Fig. 54 illustrates another semiconductor structure 21f similar to the semiconductor structure 21, except that the semiconductor structure 21f is added with a first capping layer 128. In some embodiments, the first zirconium containing oxide layer 122 has a ferroelectricity enhanced or altered by the first seed layer 120 and the first capping layer 128, and the second zirconium containing oxide layer 134 has an antiferroelectricity enhanced or altered by the second seed layer 132. In some other embodiments, the first zirconium containing oxide layer 122 has antiferroelectricity enhanced or altered by the first seed layer 120 and the first capping layer 128, and the second zirconium containing oxide layer 134 has ferroelectricity enhanced or altered by the second seed layer 132.
Fig. 55 shows another semiconductor structure 21g similar to the semiconductor structure 21a, except that the semiconductor structure 21g is added with a first capping layer 128. In some embodiments, the first zirconium containing oxide layer 122 has a ferroelectricity enhanced or altered by the first seed layer 120 and the first capping layer 128, and the second zirconium containing oxide layer 134 has an antiferroelectricity enhanced or altered by the second capping layer 136. In some other embodiments, the first zirconium containing oxide layer 122 has antiferroelectricity enhanced or altered by the first seed layer 120 and the first capping layer 128, and the second zirconium containing oxide layer 134 has ferroelectricity enhanced or altered by the second capping layer 136.
Fig. 56 illustrates another semiconductor structure 21h similar to the semiconductor structure 21b, except that the semiconductor structure 21h is added with a first capping layer 128. In some embodiments, the first zirconium containing oxide layer 122 has ferroelectricity enhanced or altered by the first seed layer 120 and the first capping layer 128, and the second zirconium containing oxide layer 134 has antiferroelectricity enhanced or altered by the second seed layer 132 and the second capping layer 136. In some other embodiments, the first zirconium containing oxide layer 122 has antiferroelectricity enhanced or altered by the first seed layer 120 and the first capping layer 128, and the second zirconium containing oxide layer 134 has ferroelectricity enhanced or altered by the second seed layer 132 and the second capping layer 136.
Based on the above discussion, it can be seen that the present disclosure provides several advantages. It is to be understood, however, that other embodiments may provide additional advantages, and not all advantages are necessarily disclosed herein. Moreover, no particular advantage is necessary for all embodiments. One advantage is that no annealing process is required to enhance or modify the as-deposited zirconium dioxide (ZrO2) or hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) The ferroelectric or antiferroelectric properties of the layer, and thus the deposited layer of the semiconductor device has low thermal budget (thermal budget), which is beneficial to process integration. Another advantage is that the thickness of the layers in the negative capacitance gate stack can be reduced, resulting in further scaling down of the negative capacitance field effect transistor (NC-FET). Another advantage is that zirconium dioxide (ZrO) is used as ferroelectric layer
2) When made, ferroelectricity or antiferroelectricity can be achieved in the ferroelectric layer without additional dopants. Another advantage is that the ferroelectric layer can be prepared directly on the substrate without a gate dielectric layer. Another advantage is that zirconium dioxide (ZrO) is used as ferroelectric layer
2) In fabrication, a ferroelectric phase or an antiferroelectric phase may be achieved by including at least one of a seed layer and a capping layer, providing flexibility in forming Negative Capacitance Field Effect Transistors (NCFETs). Another advantage is zirconium dioxide (ZrO)
2) And hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) Are all silicon-compatible, and thus zirconium dioxide (ZrO)
2) Or hafnium zirconium oxide (Hf)
0.5Zr
0.5O
2) The layer can be deposited directly on the channel region of the silicon substrate without additional gate dielectric.
In some embodiments, a semiconductor device includes a substrate, a first zirconium-containing oxide layer, a first metal oxide layer, and a top electrode. The first zirconium-containing oxide layer is located above the substrate and has ferroelectricity or antiferroelectricity. The first metal oxide layer is in contact with the first zirconium-containing oxide layer. The thickness of the first metal oxide layer is less than the thickness of the first zirconium-containing oxide layer. A top electrode is over the first zirconium-containing oxide layer.
In some embodiments, the semiconductor element further comprises a second metal oxide layer. The first zirconium-containing oxide layer is located between the first metal oxide layer and the second metal oxide layer.
In some embodiments, the thickness of the second metal oxide layer is less than the thickness of the first zirconium-containing oxide layer.
In some embodiments, the first metal oxide layer and the second metal oxide layer are made of the same material.
In some embodiments, the semiconductor device further comprises a second zirconium-containing oxide layer and a second metal oxide layer. The second zirconium-containing oxide layer is located over the first zirconium-containing oxide layer. The second metal oxide layer contacts the second zirconium-containing oxide layer.
In some embodiments, the thickness of the second metal oxide layer is less than the thickness of the second zirconium-containing oxide layer.
In some embodiments, the semiconductor element further comprises a third metal oxide layer. The second zirconium-containing oxide layer is located between the second metal oxide layer and the third metal oxide layer.
In some embodiments, the thickness of the third metal oxide layer is less than the thickness of the second zirconium-containing oxide layer.
In some embodiments, the second metal oxide layer and the third metal oxide layer are made of the same material.
In some embodiments, the first zirconium containing oxide layer has ferroelectricity and the second zirconium containing oxide layer has antiferroelectricity.
In some embodiments, the first zirconium containing oxide layer has antiferroelectric properties and the second zirconium containing oxide layer has ferroelectric properties.
In some embodiments, a semiconductor device includes a semiconductor substrate, a first zirconium-containing oxide layer, a first metal oxide layer, and a top electrode. The semiconductor substrate has source/drain regions and a channel region between the source/drain regions. The first zirconium-containing oxide layer is located above the channel region of the semiconductor substrate and has ferroelectricity or antiferroelectricity. The first metal oxide layer contacts the first zirconium-containing oxide layer. A top electrode is over the first zirconium-containing oxide layer.
In some embodiments, the first metal oxide layer is over the first zirconium-containing oxide layer.
In some embodiments, the semiconductor device further comprises a second zirconium-containing oxide layer over the first zirconium-containing oxide layer and having ferroelectric or antiferroelectric properties.
In some embodiments, the second zirconium-containing oxide layer is located between the first metal oxide layer and the top electrode.
In some embodiments, the semiconductor element further comprises a second metal oxide layer in contact with the second zirconium-containing oxide layer.
In some embodiments, the second metal oxide layer is located between the first metal oxide layer and the second zirconium-containing oxide layer.
In some embodiments, the second metal oxide layer is located between the top electrode and the second zirconium-containing oxide layer.
In some embodiments, a method of fabricating a semiconductor device includes forming source/drain regions in a semiconductor substrate; depositing a zirconium-containing oxide layer in a semiconductor substrate over a channel region between source/drain regions; forming a metal oxide layer in contact with the zirconium-containing oxide layer; and forming a top electrode over the zirconium-containing oxide layer, wherein annealing is not performed after depositing the zirconium-containing oxide layer and before forming the top electrode.
In some embodiments, forming the metal oxide layer is performed such that the metal oxide layer is thinner than the zirconium-containing oxide layer.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
