阅读说明：本技术 高压半导体装置及其制造方法 (High voltage semiconductor device and method for manufacturing the same ) 是由 许健 韦维克 陈柏安 谢克·麦斯坦巴雪 戴许曼·普佳·瑞凡卓 巴提·莫尼卡 席德·内亚兹 于 2018-11-30 设计创作，主要内容包括：本发明提供一种高压半导体装置及其制造方法。该高压半导体装置包含半导体基底,具有第一导电类型,第一高压阱设置于半导体基底内且具有与第一导电类型相反的第二导电类型,第一埋层设置于第一高压阱上且具有第一导电类型,第二埋层和第三埋层设置于第一高压阱上且具有第二导电类型,其中第一埋层位于第二埋层与第三埋层之间,外延层设置于半导体基底上,其中第一埋层、第二埋层和第三埋层自半导体基底延伸至外延层内,以及源极区和漏极区设置于第一埋层上且具有第二导电类型。(The invention provides a high-voltage semiconductor device and a manufacturing method thereof. The high-voltage semiconductor device comprises a semiconductor substrate with a first conductivity type, a first high-voltage well arranged in the semiconductor substrate and having a second conductivity type opposite to the first conductivity type, a first buried layer arranged on the first high-voltage well and having the first conductivity type, a second buried layer and a third buried layer arranged on the first high-voltage well and having the second conductivity type, wherein the first buried layer is positioned between the second buried layer and the third buried layer, an epitaxial layer arranged on the semiconductor substrate, wherein the first buried layer, the second buried layer and the third buried layer extend into the epitaxial layer from the semiconductor substrate, and a source region and a drain region arranged on the first buried layer and having the second conductivity type.)

1. A high voltage semiconductor device, comprising:

a semiconductor substrate having a first conductivity type;

a first high voltage well disposed in the semiconductor substrate and having a second conductivity type opposite to the first conductivity type;

a first buried layer disposed on the first high voltage well and having the first conductivity type;

a second buried layer and a third buried layer disposed on the first high voltage well and having the second conductivity type, wherein the first buried layer is located between the second buried layer and the third buried layer;

an epitaxial layer disposed on the semiconductor substrate, wherein the first buried layer, the second buried layer and the third buried layer extend from the semiconductor substrate into the epitaxial layer; and

a source region and a drain region disposed on the first buried layer and having the second conductivity type.

2. The high voltage semiconductor device of claim 1, further comprising:

a second high voltage well arranged in the epitaxial layer and having the second conductive type, wherein the source region and the drain region are arranged in the second high voltage well, and wherein the first buried layer is clamped between the first high voltage well and the second high voltage well; and

and a gate structure disposed on the epitaxial layer and between the source region and the drain region.

3. The high voltage semiconductor device of claim 1, wherein said first high voltage well is adjacent to said second buried layer and said third buried layer.

4. The high voltage semiconductor device of claim 1, wherein opposite sides of the first high voltage well have a first taper and a second taper, respectively, the first taper tapering along the first high voltage well in a direction toward the second buried layer and the second taper tapering along the first high voltage well in a direction toward the third buried layer, and wherein the first taper and the second taper abut the second buried layer and the third buried layer, respectively.

5. The high voltage semiconductor device according to claim 1, wherein the first high voltage well comprises a plurality of segments, adjacent two of the plurality of segments are connected by a connection portion, and the thickness of the connection portion is smaller than the thickness of the plurality of segments.

6. A high voltage semiconductor device, comprising:

a semiconductor substrate having a first conductivity type;

a first high voltage well disposed in the semiconductor substrate and having a second conductivity type opposite to the first conductivity type;

a first buried layer disposed on the first high voltage well and having the first conductivity type;

a second high voltage well disposed on the first buried layer and having the second conductivity type;

an epitaxial layer disposed on the semiconductor substrate, wherein a portion of the first buried layer and the second high voltage well are located in the epitaxial layer; and

a source region and a first drain region disposed in the second high-voltage well and having the second conductivity type.

7. The high voltage semiconductor device of claim 6, further comprising:

a second drain region disposed in the second high-voltage well and having the second conductivity type, wherein the source region is located between the first drain region and the second drain region;

a first gate structure disposed on the semiconductor substrate and between the first drain region and the source region; and

and a second gate structure disposed on the semiconductor substrate and between the source region and the second drain region.

8. The high voltage semiconductor device of claim 6, further comprising:

a third high voltage well adjacent to the second high voltage well and having the first conductivity type, wherein the first buried layer and the first high voltage well extend to below the third high voltage well.

9. The high voltage semiconductor device of claim 8, further comprising:

a second buried layer of the second conductivity type disposed on the first high voltage well, wherein the second buried layer is adjacent to the first buried layer and the first high voltage well extends below the second buried layer; and

and a fourth high voltage well disposed on the second buried layer and having the second conductivity type, wherein the third high voltage well is located between the fourth high voltage well and the second high voltage well.

10. The high voltage semiconductor device of claim 9, further comprising:

a fifth high voltage well adjacent to the second high voltage well and having the first conductivity type, wherein the second high voltage well is located between the fifth high voltage well and the third high voltage well;

a third buried layer disposed on the first high voltage well and having the second conductivity type, wherein the first buried layer is located between the second buried layer and the third buried layer; and

and a sixth high voltage well disposed on the third buried layer and having the second conductivity type, wherein the fifth high voltage well is located between the second high voltage well and the sixth high voltage well, and the first high voltage well extends to a position below the sixth high voltage well.

11. A method for manufacturing a high-voltage semiconductor device, comprising:

forming a first high voltage well in a semiconductor substrate, wherein the semiconductor substrate has a first conductivity type, and the first high voltage well has a second conductivity type opposite to the first conductivity type;

forming a first buried layer over the first high-voltage well, wherein the first buried layer has the first conductivity type;

forming a second buried layer and a third buried layer on both sides of the first buried layer, respectively, wherein the second buried layer and the third buried layer have the second conductivity type;

forming an epitaxial layer on the semiconductor substrate, wherein the first buried layer, the second buried layer and the third buried layer extend into the epitaxial layer; and

a source region and a drain region are formed in the epitaxial layer and on the first buried layer, wherein the source region and the drain region have the second conductivity type.

12. The method of claim 11, wherein the first high voltage well extends from below the first buried layer to below the second buried layer and the third buried layer, and the first high voltage well is adjacent to the second buried layer and the third buried layer.

13. The method of claim 11, wherein a dopant concentration of the first buried layer is greater than a dopant concentration of the first high-voltage well.

14. The method of manufacturing a high voltage semiconductor device according to claim 11, further comprising:

forming a second high voltage well in the epitaxial layer and on the first buried layer, wherein the second high voltage well has the second conductivity type, the source region and the drain region are located in the second high voltage well, and the first buried layer is sandwiched between the first high voltage well and the second high voltage well.

15. The method of claim 14, wherein the first high-voltage well has a dopant concentration greater than the dopant concentration of the second buried layer, the dopant concentration of the third buried layer, and the dopant concentration of the second high-voltage well.

16. The method of manufacturing a high voltage semiconductor device according to claim 14, further comprising:

forming a third high voltage well and a fourth high voltage well in the epitaxial layer and on the first buried layer, wherein the third high voltage well has the first conductivity type and the fourth high voltage well has the second conductivity type, an

The third high voltage well is located between the second high voltage well and the fourth high voltage well, and the fourth high voltage well is adjacent to the second buried layer.

Technical Field

The present invention relates to a semiconductor device, and more particularly, to a high voltage semiconductor device and a method for manufacturing the same.

Background

High voltage semiconductor device technology is applicable to the field of high voltage and high power integrated circuits. Conventional high voltage semiconductor devices, such as Vertical Diffused Metal Oxide Semiconductor (VDMOS) transistors and horizontal diffused metal oxide semiconductor (LDMOS) transistors, are mainly used in the field of device applications of 18V or more. The high voltage device technology has advantages of cost effectiveness, and is easily compatible with other technologies, and has been widely applied in the fields of display driving IC devices, power supplies, power management, communication, automotive electronics, or industrial control.

While existing high voltage semiconductor devices have been developed to meet their intended use, they have not been completely satisfactory in every aspect. For example, if the structure and function of the device that has been used in the low voltage device are applied to the high voltage device, the device needs to be redesigned and the occupied area is increased, which cannot meet the requirement of miniaturization, high breakdown voltage and low on-resistance of the high voltage semiconductor device. Accordingly, there are still some problems to be overcome with respect to high voltage semiconductor devices and manufacturing techniques.

Disclosure of Invention

Embodiments of a high voltage semiconductor device, in particular an embodiment of a horizontal diffused metal oxide semiconductor (LDMOS) transistor, are provided. In some embodiments of the present invention, a first high voltage well is disposed within a semiconductor substrate, the semiconductor substrate having a first conductivity type, and the first high voltage well having a second conductivity type opposite the first conductivity type. And arranging a first buried layer, a second buried layer and a third buried layer on the first high-voltage well, wherein the first buried layer is positioned between the second buried layer and the third buried layer and has a first conductivity type, and the second buried layer and the third buried layer have a second conductivity type. Further, a second high voltage well having a second conductivity type is provided on the first buried layer, and a source region and a drain region having the second conductivity type are provided within the second high voltage well.

By extending the first high-voltage well below the second buried layer and the third buried layer, a semiconductor device that is completely isolated from the semiconductor substrate (fully isolated) and has a high breakdown voltage can be formed on the first high-voltage well. Furthermore, by disposing the first buried layer between the first high voltage well and the second high voltage well, the voltage required for the operation of the semiconductor device itself can be provided on the premise that the semiconductor device can withstand the high voltage by using the first high voltage well. A ldmos transistor with a high breakdown voltage can be widely applied to a level shifter (level shifter) and a High Voltage Integrated Circuit (HVIC) chip. In addition, since the source region and the drain region are both disposed in the second high voltage well, the on resistance (Ron) of the semiconductor device can be reduced, thereby increasing the on current of the ldmos transistor.

According to some embodiments, a high voltage semiconductor device is provided. The high voltage semiconductor device includes a semiconductor substrate having a first conductivity type, and a first high voltage well disposed in the semiconductor substrate and having a second conductivity type opposite to the first conductivity type. The high voltage semiconductor device also includes a first buried layer disposed on the first high voltage well and having a first conductivity type, and a second buried layer and a third buried layer disposed on the first high voltage well and having a second conductivity type, wherein the first buried layer is located between the second buried layer and the third buried layer. The high voltage semiconductor device further includes an epitaxial layer disposed on the semiconductor substrate, wherein the first, second and third buried layers extend from the semiconductor substrate into the epitaxial layer, and source and drain regions disposed on the first buried layer and having the second conductivity type.

According to some embodiments, a high voltage semiconductor device is provided. The high voltage semiconductor device includes a semiconductor substrate having a first conductivity type, and a first high voltage well disposed in the semiconductor substrate and having a second conductivity type opposite to the first conductivity type. The high voltage semiconductor device also includes a first buried layer disposed on the first high voltage well and having a first conductivity type, and a second high voltage well disposed on the first buried layer and having a second conductivity type. The high voltage semiconductor device further includes an epitaxial layer disposed on the semiconductor substrate, wherein a portion of the first buried layer and the second high voltage well are located within the epitaxial layer, and a source region and a first drain region disposed within the second high voltage well and having the second conductivity type.

According to some embodiments, a method of manufacturing a high voltage semiconductor device is provided. The method includes forming a first high voltage well within a semiconductor substrate, wherein the semiconductor substrate has a first conductivity type and the first high voltage well has a second conductivity type opposite the first conductivity type. The method also includes forming a first buried layer on the first high voltage well, wherein the first buried layer has a first conductivity type, and forming a second buried layer and a third buried layer on both sides of the first buried layer, respectively, wherein the second buried layer and the third buried layer have a second conductivity type. The method further includes forming an epitaxial layer on the semiconductor substrate, wherein the first, second and third buried layers extend into the epitaxial layer, and forming source and drain regions in the epitaxial layer and on the first buried layer, wherein the source and drain regions have the second conductivity type.

The semiconductor device of the present invention can be applied to various types of semiconductor devices, and in order to make the features and advantages of the present invention more comprehensible, embodiments thereof applied to a ldmos transistor will be described in detail below with reference to the accompanying drawings.

Drawings

The aspects of the embodiments of the present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings. It is noted that some components (features) may not be drawn to scale according to industry standard practice. In fact, the dimensions of the various elements may be increased or decreased for clarity of discussion.

FIGS. 1A-1F are schematic cross-sectional views illustrating various stages in forming the high voltage semiconductor device of FIG. 1F, in accordance with some embodiments of the present invention;

FIG. 2 is a schematic cross-sectional view of a high voltage semiconductor device, according to further embodiments of the present invention; and

fig. 3 is a schematic cross-sectional view illustrating a high voltage semiconductor device according to further embodiments of the present invention.

Reference numerals

100. 200 and 300: a high voltage semiconductor device;

101: a semiconductor substrate;

103. 203, 303: a first high voltage well;

105 a: a second buried layer;

105 b: a third buried layer;

107: a first buried layer;

109: an epitaxial layer;

111a, 111 b: a high-voltage trap;

113 a: a fourth high voltage well;

113 b: a sixth high voltage well;

115 a: a third high voltage well;

115 b: a fifth high-voltage well;

117: a second high voltage well;

121a, 121b, 123: a well;

131a, 131b, 133a, 133b, 135a, 135 b: an isolation structure;

141a, 141 b: a gate dielectric layer;

142a, 142 b: a gate structure;

143a, 143 b: a gate electrode layer;

145a, 145b, 145c, 145 d: a spacer;

151a, 151b, 153a, 153b, 155a, 155b, 157: a doped region;

203 a: a first taper portion;

203 b: a second taper portion;

303a, 303b, 303c, 303d, 303e, 303f, 303g, 303h, 303i, 303j, 303 k: a segment;

305a, 305b, 305c, 305d, 305e, 305f, 305g, 305h, 305i, 305 j: a connecting portion;

d: a distance;

d1, D2, E1, E2, E3, E4, G1, G2, S: an electrode;

t: and (4) thickness.

Detailed Description

The following disclosure provides many different embodiments or examples for implementing different components of the provided high voltage semiconductor device. Specific examples of components and arrangements thereof are described below to simplify the present embodiments. These are, of course, merely examples and are not intended to be limiting. For example, references in the description to a first element being formed on a second element may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements such that they are not in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Some variations of the embodiments are described below. Like reference numerals are used to designate like elements in the various figures and described embodiments. It will be understood that additional operations may be provided before, during, or after the method, and that some of the recited operations may be substituted or deleted for other embodiments of the method.

Fig. 1A-1F are schematic cross-sectional views illustrating various stages in forming the high voltage semiconductor device 100 of fig. 1F, according to some embodiments of the present invention.

According to some embodiments, as shown in fig. 1A, a first high voltage well 103 is formed within a semiconductor substrate 101. The semiconductor substrate 101 may be made of silicon or other semiconductor materials, or the semiconductor substrate 101 may comprise other elemental semiconductor materials, such as germanium (Ge). In some embodiments, the semiconductor substrate 101 is made of a compound semiconductor such as silicon carbide, gallium nitride, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the semiconductor substrate 101 is made of an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or indium gallium phosphide.

In addition, the semiconductor substrate 101 may include a silicon-on-insulator (SOI) substrate. In some embodiments, the semiconductor substrate 101 may be a lightly doped P-type or N-type substrate. In the present embodiment, the semiconductor substrate 101 is P-type with a P-type dopant therein, such as boron (B), and the high voltage semiconductor device 100 formed subsequently may include an N-type ldmos transistor on the semiconductor substrate 101.

In some embodiments, the first high voltage well 103 has a conductivity type opposite to that of the semiconductor substrate 101. In the present embodiment, the semiconductor substrate is P-type, and the high voltage well 103 is N-type. In addition, the method of forming the first high voltage well 103 may include performing an ion implantation process in the semiconductor substrate 101 using a mask, the ion implantation process implanting N-type dopants, such As phosphorus (P) or arsenic (As), with a dopant concentration of about 1x10 ¹⁷Atom/cubic centimeter (atoms/cm) ³) To about 5x10 ¹⁸Atom/cubic centimeter (atoms/cm) ³) Within the range of (1). Then, the implanted ions are driven (drive-in) into the semiconductor substrate 101 to form a first high voltage well 103.

In addition, in some embodiments, the thickness T of the first high voltage well 103 perpendicular to the top surface of the semiconductor substrate 101 is greater than about 8 microns.

According to some embodiments, as shown in fig. 1B, a first buried layer 107, a second buried layer 105a, and a third buried layer 105B are formed within the semiconductor substrate 101 and within the first high voltage well 103. Specifically, the first buried layer 107, the second buried layer 105a, and the third buried layer 105b are formed at upper portions of the semiconductor substrate 101 and the first high voltage well 103, near the top surface of the semiconductor substrate 101. After the first, second, and third buried layers 107, 105a, and 105b are formed, the first, second, and third buried layers 107, 105a, and 105b are located on the remaining first high voltage well 103. In the present embodiment, the first buried layer 107 is of a P-type, and the second and third buried layers 105a and 105b are of an N-type. The first buried layer 107, the second buried layer 105a, and the third buried layer 105b are formed in the same or similar manner as the first high voltage well 103, and a description thereof will not be repeated. In some embodiments, the second buried layer 105a and the third buried layer 105b may be formed in the same process, and may be formed before or after the first buried layer 107.

The second buried layer 105a and the third buried layer 105b are located on both sides of the first buried layer 107, respectively. That is, the first buried layer 107 is located between the second buried layer 105a and the third buried layer 105 b. In some embodiments, the first buried layer 107 is sandwiched between the second buried layer 105a and the third buried layer 105b, and the first high voltage well 103 extends below the second buried layer 105a and the third buried layer 105 b. Specifically, the horizontal projection of the first buried layer 107 on the top surface of the semiconductor substrate 101 is completely located within the horizontal projection of the first high voltage well 103 on the top surface of the semiconductor substrate 101, and the horizontal projection of the first high voltage well 103 on the top surface of the semiconductor substrate 101 overlaps with the horizontal projections of the second buried layer 105a and the third buried layer 105b on the top surface of the semiconductor substrate 101.

Furthermore, in some embodiments, the thickness D of the first, second, and third buried layers 107, 105a, and 105b perpendicular to the top surface of the semiconductor substrate 101 is greater than about 1 micron.

Next, as shown in fig. 1C, an epitaxial layer 109 is formed on the semiconductor substrate 101. In some embodiments, the epitaxial layer 109 may be N-type or P-type. Epitaxial layer 109 may be formed by Metal Organic Chemical Vapor Deposition (MOCVD), plasma-enhanced CVD, Molecular Beam Epitaxy (MBE), Hydride Vapor Phase Epitaxy (HVPE), Liquid Phase Epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE), other similar processes, or a combination of the foregoing.

In some embodiments, since the epitaxial layer 109 is formed under a high temperature condition, ions previously implanted into the first buried layer 107, the second buried layer 105a and the third buried layer 105b may diffuse into the epitaxial layer 109, as shown in fig. 1C, and the first buried layer 107, the second buried layer 105a and the third buried layer 105b are located near an interface between the semiconductor substrate 101 and the epitaxial layer 109 and respectively have a portion in the semiconductor substrate 101 and another portion in the epitaxial layer 109.

In some embodiments, the dopant concentration of the first buried layer 107 is about 1 × 10 ¹⁷Atom/cubic centimeter to about 1x10 ¹⁹In atomic/cubic centimeter range, and the dopant concentration of the second buried layer 105a and the third buried layer 105b is about 5x10 ¹⁶Atom/cubic centimeter to about 1x10 ¹⁹In atoms/cubic centimeter. Note that the dopant concentration of the first buried layer 107 is greater than the dopant concentration of the first high-voltage well 103. In some embodiments, the dopant concentration of the second buried layer 105a and the third buried layer 105b is greater than the dopant concentration of the first high voltage well 103. In addition, the dopant concentration of the first buried layer 107 is greater than the dopant concentration of the lightly doped semiconductor substrate 101.

Referring again to fig. 1C, a second high voltage well 117, a third high voltage well 115a, a fourth high voltage well 113a, a fifth high voltage well 115b, and a sixth high voltage well 113b are formed within the epitaxial layer 109. The second high voltage well 117, the third high voltage well 115a, and the fifth high voltage well 115b are located on the first buried layer 107 and adjoin the first buried layer 107. The fourth high voltage well 113a is located on the second buried layer 105a and adjacent to the second buried layer 105 a. The sixth high voltage well 113b is located on the third buried layer 105b and adjoins the third buried layer 105 b.

In the present embodiment, the interface between the first buried layer 107 and the second buried layer 105a is aligned with the interface between the third high voltage well 115a and the fourth high voltage well 113a, and the interface between the first buried layer 107 and the third buried layer 105b is aligned with the interface between the fifth high voltage well 115b and the sixth high voltage well 113 b. However, the foregoing positional relationship may not be limited thereto.

In some embodiments, the second high voltage well 117 has the same conductivity type as the first high voltage well 103. In the present embodiment, the second high voltage well 117, the fourth high voltage well 113a, and the sixth high voltage well 113b are N-type, and the third high voltage well 115a and the fifth high voltage well 115b are P-type. The formation method of the second high voltage well 117, the third high voltage well 115a, the fourth high voltage well 113a, the fifth high voltage well 115b, and the sixth high voltage well 113b is the same as or similar to the formation method of the first high voltage well 103, and a description thereof will not be repeated. It is noted that the first buried layer 107 is sandwiched between the first high voltage well 103 and the second high voltage well 117.

In addition, a high voltage well 111a and a high voltage well 111b may be selectively formed in the epitaxial layer 109. In some embodiments, high voltage well 111a and high voltage well 111b are P-type. The formation method of the high voltage well 111a and the high voltage well 111b is the same as or similar to the formation method of the first high voltage well 103, and a description thereof will not be repeated.

According to some embodiments, as shown in fig. 1D, a well 121a, a well 123, and a well 121b (the well 123 is also referred to as a body region) are formed within the second high-voltage well 117. The well 121a and the well 121b have the same conductivity type, and the conductivity type of the well 121a is opposite to that of the well 123. In this embodiment, well 121a and well 121b are N-type, and well 123 is P-type. The formation method of the well 121a, the well 123, and the well 121b is the same as or similar to the formation method of the first high voltage well 103, and a description thereof will not be repeated.

In some embodiments, the doping concentration of the well 121a, the well 123, and the well 121b is greater than the doping concentration of the second high voltage well 117. For example, the doping concentration of well 121a, well 123, and well 121b is about 5x10 ¹⁶Atom/cubic centimeter to about 5x10 ¹⁸In the atomic/cubic centimeter range and the dopant concentration of the second high voltage well 117 is about 1x10 ¹⁶Atom/cubic centimeter to about 1x10 ¹⁸In atoms/cubic centimeter.

After forming the well 121a, the well 123, and the well 121b in the second high voltage well 117, isolation structures 131a, 131b, 133a, 133b, 135a, and 135b are formed on the epitaxial layer 109. Specifically, a portion of the isolation structures 131a, 131b, 133a, 133b, 135a, and 135b are embedded within the epitaxial layer 109. In some embodiments, the isolation structures 131a, 131b, 133a, 133b, 135a, and 135b are made of silicon oxide and are local oxidation of silicon (LOCOS) isolation structures formed by a thermal oxidation method. In other embodiments, the isolation structures 131a, 131b, 133a, 133b, 135a, and 135b may be Shallow Trench Isolation (STI) structures formed by an etching and deposition process.

Then, as shown in fig. 1E, after the isolation structures 131a, 131b, 133a, 133b, 135a, and 135b are formed, a gate structure 142a (also referred to as a first gate structure) and a gate structure 142b (also referred to as a second gate structure) are formed on the epitaxial layer 109. Gate structure 142a includes a gate dielectric layer 141a and a gate electrode layer 143a, and gate structure 142b includes a gate dielectric layer 141b and a gate electrode layer 143 b. In addition, spacers 145a and 145b are formed on opposite sides of the gate structure 142a, and spacers 145c and 145d are formed on opposite sides of the gate structure 142 b.

In some embodiments, the gate structure 142a extends from the well 123 onto the isolation structure 135a, and the gate structure 142a covers a portion of the well 123 and a portion of the second high-voltage well 117. Gate structure 142b extends from well 123 onto isolation structure 135b, and gate structure 142b covers a portion of well 123 and a portion of second high-voltage well 117.

The method for forming the gate structures 142a and 142b may include sequentially blanket depositing a dielectric material layer and a conductive material layer on the epitaxial layer 109, and then patterning the dielectric material layer and the conductive material layer by a photolithography process and an etching process to form the gate structure 142a including the gate dielectric layer 141a and the gate electrode layer 143a and the gate structure 142b including the gate dielectric layer 141b and the gate electrode layer 143 b.

In addition, the material of the dielectric material layer (i.e., the material of the gate dielectric layers 141a and 141 b) may comprise silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant (high-k) dielectric material, a combination of the foregoing, or other suitable dielectric materials. In some embodiments, the dielectric material layer can be formed by Chemical Vapor Deposition (CVD) or spin coating (spin coating). The material of the conductive material layer (i.e., the material of the gate electrode layers 143a and 143 b) may comprise amorphous silicon, polysilicon, one or more metals, metal nitrides, conductive metal oxides, combinations of the foregoing, or other suitable conductive materials. The conductive material layer may be formed by Chemical Vapor Deposition (CVD), sputtering, resistive heating evaporation, e-beam evaporation, or other suitable deposition methods. In some embodiments, the spacers 145a, 145b, 145c, and 145d may comprise an insulating material and be formed by a deposition process.

According to some embodiments, as shown in fig. 1F, a doped region 151a is formed in the high voltage well 111a, a doped region 153a is formed in the third high voltage well 115a, a doped region 155a is formed in the well 121a, a doped region 157 is formed in the well 123, a doped region 155b is formed in the well 121b, a doped region 153b is formed in the fifth high voltage well 115b, and a doped region 151b is formed in the high voltage well 111 b. In some embodiments, after forming the gate structures 142a and 142b, the doped regions 151a, 151b, 153a, 153b, 155a, 155b, 157 are formed.

Specifically, the doped region 153a is located between the isolation structure 131a and the isolation structure 133a, the doped region 155a is located between the isolation structure 133a and the isolation structure 135a, the doped region 157 is located between the gate structure 142a and the gate structure 142b, the doped region 155b is located between the isolation structure 133b and the isolation structure 135b, and the doped region 153b is located between the isolation structure 131b and the isolation structure 133 b.

In the present embodiment, the doped regions 151a, 153b and 151b are P-type, and the doped regions 155a, 157 and 155b are N-type. The doping concentration of the doped regions 151a, 153a, 155a, 157, 155b, 153b, and 151b is higher than that of the wells 121a, 123, and 121 b. In some embodiments, doped regions 151a, 153a, 155a, 157, 155b, 153b, and 151b have a doping concentration of about 5x10 ¹⁸Atom/cubic centimeter to about 5x10 ²⁰In atoms/cubic centimeter.

It is noted that the doped region 157 may serve as a source region of the high voltage semiconductor device 100, and the doped regions 155a and 155b may serve as drain regions of the high voltage semiconductor device 100 (the doped region 155a is also referred to as a first drain region, and the doped region 155b is also referred to as a second drain region). In addition, the source region 157, the first drain region 155a, and the second drain region 155b are all located in the second high voltage well 117, and the source region 157, the first drain region 155a, the second drain region 155b, and the second high voltage well 117 have the same conductivity type.

In some embodiments, the high voltage semiconductor device 100 includes a dielectric layer (not shown) disposed on the epitaxial layer 109. The dielectric layer on the epitaxial layer 109 comprises a multi-layer structure formed by a plurality of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, or other suitable dielectric materials. In addition, the high voltage semiconductor device 100 includes an interconnect structure (not shown) disposed within the dielectric layer, and a plurality of electrodes disposed on the interconnect structure.

Specifically, the doped region 151a is connected to the electrode E via the interconnection structure ₁Electrically connected to the doped region 153a via an interconnection structure and the electrode E ₂Electrically connected to the first drain region 155a via an interconnection structure ₁(also called a first drain electrode), the source region 157 is electrically connected to the electrode S (also called a source electrode) via an interconnection structure, and the second drain region 155b is electrically connected to the electrode D via an interconnection structure ₂(also called second drain electrode) and the doped region 153b is connected to the electrode E through an interconnection structure ₃Electrically connected to the doped region 151b via the interconnection structure and the electrode E ₄(also known as the base electrode) is electrically connected.

In addition, the gate structures 142a and 142b are connected to the electrode G via an interconnection structure ₁And electrode G ₂(G ₁And G ₂Also called gate electrode) is electrically connected to form an electrode E ₁、E ₂、D ₁、D ₂、E ₃、E ₄、G ₁、G ₂And S, the high voltage semiconductor device 100 is completed.

Fig. 2 is a schematic cross-sectional view illustrating a high voltage semiconductor device 200, according to some embodiments of the present invention. The high voltage semiconductor device 200 differs from the high voltage semiconductor device 100 in that the shape of the first high voltage well 203 is different from the shape of the first high voltage well 103. The processes and materials of other components of the high voltage semiconductor device 200 are the same as or similar to those of the high voltage semiconductor device 100, and will not be described again.

As shown in fig. 2, the portions of the high voltage semiconductor device 200 where the first high voltage well 203 overlaps the second high voltage well 117 have the same thickness. It is noted that opposite sides of the first high voltage well 203 have a first taper portion 203a and a second taper portion 203b, respectively, the first taper portion 203a has a tapered thickness along the first high voltage well 203 toward the second buried layer 105a, and the second taper portion 203b has a tapered thickness along the first high voltage well 203 toward the third buried layer 105 b. Furthermore, the first taper 203a adjoins the first buried layer 107 and the second buried layer 105a, and the second taper 203b adjoins the first buried layer 107 and the third buried layer 105 b.

In some embodiments, the length of the bottom-most surface of first high voltage well 203 is the same as the length of the bottom surface of second high voltage well 117. In other words, the interface between the portion of the first high voltage well 203 having the same thickness and the first taper portion 203a is aligned with the interface between the third high voltage well 115a and the second high voltage well 117, and the interface between the portion of the first high voltage well 203 having the same thickness and the second taper portion 203b is aligned with the interface between the fifth high voltage well 115b and the second high voltage well 117, so that the process concentration range of the first buried layer 107 can be flexible, and the problem of leakage current caused by depletion is not easily caused.

Fig. 3 is a schematic cross-sectional view illustrating a high voltage semiconductor device 300, according to some embodiments of the present invention. The high voltage semiconductor device 300 differs from the high voltage semiconductor device 100 in that the shape of the high voltage well 303 is different from the shape of the first high voltage well 103. The processes and materials of other components of the high voltage semiconductor device 300 are the same as or similar to those of the high voltage semiconductor device 100, and will not be described again.

As shown in fig. 3, the first high voltage well 303 of the high voltage semiconductor device 300 includes a plurality of segments and a plurality of connections, for example, segments 303a, 303b, 303c, 303d, 303e, 303f, 303g, 303h, 303i, 303j, and 303k, and connections 305a, 305b, 305c, 305d, 305e, 305f, 305g, 305h, 305i, and 305 j. The segments 303a-303k are connected to each other by connections 305a-305 j.

In some embodiments, the method of forming the first high voltage well 303 includes performing an ion implantation process through a patterned photoresist to form a plurality of discontinuous sections (not shown) in the semiconductor substrate 101, and then performing a heat treatment process, i.e., a drive-in process, such that ions in the implanted sections are out-diffused to connect with each other. It is noted that the method of forming the first high-voltage well 303 by using a plurality of discrete sections can adjust the dopant concentration of each section, so that the characteristics of the high-voltage semiconductor device 300 can be more precisely controlled in terms of process.

Embodiments of a high voltage semiconductor device, in particular an embodiment of a horizontal diffused metal oxide semiconductor (LDMOS) transistor, are provided. In some embodiments of the present invention, a first high voltage well is disposed within a semiconductor substrate, the semiconductor substrate having a first conductivity type, and the first high voltage well having a second conductivity type opposite the first conductivity type. And arranging a first buried layer, a second buried layer and a third buried layer on the first high-voltage well, wherein the first buried layer is positioned between the second buried layer and the third buried layer and has a first conductivity type, and the second buried layer and the third buried layer have a second conductivity type. Further, a second high voltage well having a second conductivity type is provided on the first buried layer, and a source region and a drain region having the second conductivity type are provided within the second high voltage well.

By extending the first high-voltage well below the second buried layer and the third buried layer, a semiconductor device having a high breakdown voltage and completely isolated from the semiconductor substrate can be formed on the first high-voltage well. Furthermore, by arranging the first buried layer between the first high-voltage well and the second high-voltage well, the voltage required for the operation of the semiconductor device can be provided on the premise that the semiconductor device can withstand the high voltage by using the first high-voltage well, i.e. the element originally used for the low-voltage device can be applied to the high-voltage operation environment. A ldmos transistor with a high breakdown voltage can be widely used in a level shifter and a High Voltage Integrated Circuit (HVIC) chip.

In addition, in some embodiments of the present invention, since the source region and the drain region are both disposed in the second high voltage well, the on-resistance (Ron) of the semiconductor device can be reduced, thereby increasing the on-current of the ldmos transistor.

The embodiments are summarized above so that those skilled in the art to which the present invention pertains can more clearly understand the aspects of the embodiments of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present invention.