阅读说明：本技术 集成电路及其制造方法 (Integrated circuit and method of manufacturing the same ) 是由 刘铭棋 于 2019-07-26 设计创作，主要内容包括：一种集成电路包括绝缘体上半导体衬底,所述绝缘体上半导体衬底包括基底衬底、绝缘体层及半导体器件层。半导体器件层中的源极区与漏极区通过在半导体器件层中的沟道区间隔开。栅极电极设置在沟道区之上且具有在半导体器件层的顶表面下方延伸的底表面。侧壁间隔件结构沿着栅极电极的外侧壁延伸,且具有搁置在半导体器件层的顶表面上的底表面。栅极介电质将沟道区与栅极电极的底表面分隔开且接触侧壁间隔件结构的底表面。位于栅极电极的底表面之下的沟道区对应于半导体器件层,且具有小于40埃的厚度。(An integrated circuit includes a semiconductor-on-insulator substrate including a base substrate, an insulator layer, and a semiconductor device layer. A source region and a drain region in the semiconductor device layer are separated by a channel region in the semiconductor device layer. A gate electrode is disposed over the channel region and has a bottom surface extending below a top surface of the semiconductor device layer. The sidewall spacer structure extends along an outer sidewall of the gate electrode and has a bottom surface that rests on a top surface of the semiconductor device layer. The gate dielectric separates the channel region from a bottom surface of the gate electrode and contacts a bottom surface of the sidewall spacer structure. The channel region located below the bottom surface of the gate electrode corresponds to a semiconductor device layer and has a thickness of less than 40 angstroms.)

1. An integrated circuit, comprising:

a semiconductor-on-insulator substrate comprising a base substrate, an insulator layer located over the base substrate, and a semiconductor device layer located over the insulator layer;

source and drain regions disposed in the semiconductor device layer, the source and drain regions having a first conductivity type; and

a channel region disposed in the semiconductor device layer and separating the source region from the drain region, the channel region having a second conductivity type opposite the first conductivity type, the channel region including a central region having an upper surface recessed relative to upper surfaces of the first and second peripheral regions, a first peripheral region separating the source region from the central region, and a second peripheral region separating the drain region from the central region, such that the semiconductor device layer has a first thickness in the central region of the channel region and a second thickness in the first and second peripheral regions of the channel region, the first thickness being less than the second thickness.

2. The integrated circuit of claim 1, further comprising:

a sidewall spacer structure disposed over the first and second peripheral regions, wherein a bottom surface of the sidewall spacer structure has a plurality of outer regions resting on the upper surfaces of the first and second peripheral regions, and the bottom surface of the sidewall spacer structure has a plurality of overhanging regions extending inwardly beyond the upper surfaces of the first and second peripheral regions.

3. The integrated circuit of claim 2, further comprising:

a gate dielectric disposed over the channel region, the gate dielectric including a peripheral dielectric region having an upper surface contacting the plurality of overhang regions and a central dielectric region having an upper surface at a first height, the first height being less than a second height of the peripheral dielectric region.

4. The integrated circuit of claim 3, further comprising:

a gate electrode disposed over the gate dielectric and separated from the channel region by the gate dielectric, the gate electrode having a central region disposed on the upper surface of the central dielectric region and having a peripheral region disposed over the peripheral dielectric region.

5. The integrated circuit of claim 4, wherein the peripheral region of the gate electrode extends under the plurality of overhang regions of the sidewall spacer structure.

6. The integrated circuit of claim 4, wherein the peripheral region of the gate electrode is located entirely within a plurality of innermost sidewalls of the sidewall spacer structure.

7. The integrated circuit of claim 4, wherein the upper surface of the peripheral dielectric region is completely confined below an interior region of the bottom surface of the sidewall spacer structure.

8. An integrated circuit, comprising:

a semiconductor-on-insulator substrate comprising a base substrate, an insulator layer located over the base substrate, and a semiconductor device layer located over the insulator layer;

source and drain regions disposed in the semiconductor device layer and spaced apart from each other by a channel region in the semiconductor device layer;

a gate electrode disposed over the channel region, the gate electrode having a bottom surface extending below a top surface of the semiconductor device layer;

a sidewall spacer structure disposed along a plurality of outer sidewalls of the gate electrode, the sidewall spacer structure having a bottom surface that rests on the top surface of the semiconductor device layer; and

a gate dielectric disposed over the channel region and separating the channel region from the bottom surface of the gate electrode, the gate dielectric contacting the bottom surface of the sidewall spacer structure and extending to a depth below the top surface of the semiconductor device layer; and

wherein the channel region located below the bottom surface of the gate electrode corresponds to the semiconductor device layer and has a thickness of less than 40 angstroms.

9. The integrated circuit of claim 8, wherein the sidewall spacer structure has a bottom interior corner with a rounded profile.

10. A method of fabricating an integrated circuit, the method comprising:

receiving a semiconductor-on-insulator substrate comprising a base substrate, an insulator layer over the base substrate, and a semiconductor device layer over the insulator layer;

forming a sacrificial gate stack over the semiconductor device layer;

forming a sidewall spacer structure around a plurality of outer sidewalls of the sacrificial gate stack;

forming a plurality of trenches in the semiconductor device layer on a plurality of outer edges of the sidewall spacer structure;

forming source and drain regions in the plurality of trenches by epitaxy;

removing the sacrificial gate stack to form a gate recess between a plurality of inner sidewalls of the sidewall spacer structure;

extending the gate recess into the semiconductor device layer, wherein the semiconductor device layer remaining under the extended gate recess corresponds to a channel region separating the source region from the drain region;

forming a replacement gate dielectric over the channel region; and

forming a replacement metal gate electrode over the replacement gate dielectric, the replacement metal gate electrode having a bottom surface extending below a top surface of the semiconductor device layer.

Technical Field

The embodiment of the invention relates to an integrated circuit and a manufacturing method thereof.

Background

The semiconductor manufacturing industry has experienced exponential growth over the past few decades. In the course of semiconductor evolution, the minimum feature size of semiconductor devices decreases with time, contributing to an increase in the number of semiconductor devices per unit area on successive generations of Integrated Circuits (ICs). This "shrinking" of devices allows engineers to pack more devices and more corresponding functions onto newer generations of integrated circuits, and thus becomes a fundamental driver of modern digital age. Another advancement that has contributed to improving the functionality of integrated circuits in recent years has been the replacement of conventional polysilicon gates with metal gates.

Disclosure of Invention

According to some embodiments, there is provided an integrated circuit comprising: a semiconductor-on-insulator substrate comprising a base substrate, an insulator layer located over the base substrate, and a semiconductor device layer located over the insulator layer; source and drain regions disposed in the semiconductor device layer, the source and drain regions having a first conductivity type; and a channel region disposed in the semiconductor device layer and separating the source region from the drain region, the channel region having a second conductivity type opposite the first conductivity type, the channel region including a central region, a first peripheral region separating the source region from the central region, and a second peripheral region separating the drain region from the central region, the central region having an upper surface recessed relative to upper surfaces of the first and second peripheral regions, such that the semiconductor device layer has a first thickness in the central region of the channel region and a second thickness in the first and second peripheral regions of the channel region, the first thickness being less than the second thickness.

According to some embodiments, there is provided an integrated circuit comprising: a semiconductor-on-insulator substrate comprising a base substrate, an insulator layer located over the base substrate, and a semiconductor device layer located over the insulator layer; source and drain regions disposed in the semiconductor device layer and spaced apart from each other by a channel region in the semiconductor device layer; a gate electrode disposed over the channel region, the gate electrode having a bottom surface extending below a top surface of the semiconductor device layer; a sidewall spacer structure disposed along a plurality of outer sidewalls of the gate electrode, the sidewall spacer structure having a bottom surface that rests on the top surface of the semiconductor device layer; and a gate dielectric disposed over the channel region and separating the channel region from the bottom surface of the gate electrode, the gate dielectric contacting the bottom surface of the sidewall spacer structure and extending to a depth below the top surface of the semiconductor device layer; wherein the channel region located below the bottom surface of the gate electrode corresponds to the semiconductor device layer and has a thickness of less than 40 angstroms.

According to some embodiments, there is provided a method of fabricating a semiconductor construction, the method comprising: receiving a semiconductor-on-insulator substrate comprising a base substrate, an insulator layer over the base substrate, and a semiconductor device layer over the insulator layer; forming a sacrificial gate stack over the semiconductor device layer; forming a sidewall spacer structure around a plurality of outer sidewalls of the sacrificial gate stack; forming a plurality of trenches in the semiconductor device layer on a plurality of outer edges of the sidewall spacer structure; forming source and drain regions in the plurality of trenches by epitaxy; removing the sacrificial gate stack to form a gate recess between a plurality of inner sidewalls of the sidewall spacer structure; extending the gate recess into the semiconductor device layer, wherein the semiconductor device layer remaining under the extended gate recess corresponds to a channel region separating the source region from the drain region; forming a replacement gate dielectric over the channel region; and forming a replacement metal gate electrode over the replacement gate dielectric, the replacement metal gate electrode having a bottom surface extending below a top surface of the semiconductor device layer.

Drawings

Various aspects of the disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A illustrates a cross-sectional view of some embodiments of an Integrated Circuit (IC) having a recessed channel structure in a Fully Depleted Semiconductor On Insulator (FDSOI).

Fig. 1B illustrates a top view of some embodiments of an Integrated Circuit (IC) having a recessed channel structure in an FDSOI.

Fig. 2A illustrates an enlarged cross-sectional view of some embodiments of an integrated circuit having a recessed channel structure in an FDSOI.

Fig. 2B illustrates an enlarged cross-sectional view of some embodiments of an integrated circuit having a recessed channel structure in an FDSOI.

Fig. 2C illustrates an enlarged cross-sectional view of some embodiments of an integrated circuit having a recessed channel structure in an FDSOI.

Fig. 2D illustrates an enlarged cross-sectional view of some embodiments of an integrated circuit having a recessed channel structure in an FDSOI.

Fig. 3 illustrates a flow diagram of some embodiments of a method of forming an integrated circuit having a recessed channel structure in an FDSOI.

Fig. 4-13A-13B illustrate a series of cross-sectional views of some embodiments of fabricating an integrated circuit having a recessed channel structure in an FDSOI.

[ description of symbols ]

100: integrated circuit with a plurality of transistors

102: FDSOI substrate

104: base substrate

106: insulator layer

108: semiconductor device layer

108t, 214: top surface

110. 504, a step of: source region

112. 506: drain region

114: channel region

115: central channel region

116: grid electrode

116 b: bottom surface

116 p: peripheral region

117 a: a first peripheral channel region

117 b: a second peripheral channel region

118: sidewall spacer structure

118 b: bottom surface

118 o: outer zone

119: overhanging zone

120: gate dielectric

122: contact element

123: interlayer dielectric

124: metal wire

126: through hole

128: dielectric structure

129: internal connection structure

130: bonding pad

202: sharp internal lower corner

204a, 204 b: inclined side wall

206: surface of

250. 252: circular profile

300: method of producing a composite material

302. 304, 306, 308, 310, 312, 314, 316, 318, 320: movement of

400: stacking

402: dielectric layer

404: electrode layer

502: grid electrode

702: groove

704: tip end

1102: bottom gate dielectric

1104: upper gate dielectric

L: length of

t 1: a first thickness

t 2: second thickness

t _B、t _I: thickness of

t _D: maximum thickness

W: width of

Detailed Description

The present disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, formation of a first feature "over" or "on" a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms such as "below", "lower", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another (other) element or feature as illustrated in the figures for ease of description. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative terms used herein may be similarly interpreted accordingly.

A typical transistor in a CMOS (complementary metal-oxide-semiconductor) system on a chip today is formed on a bulk silicon substrate, meaning that the transistor is formed on a substrate consisting of a single monocrystalline silicon layer. Various aspects of the present disclosure are directed to the following recognition: a fully depleted semiconductor-on-insulator (FDSOI) substrate, which includes a relatively thick semiconductor base substrate, an insulator layer over the base substrate, and a relatively thin semiconductor device layer over the insulator layer, reduces substrate leakage (substructure) as compared to a bulk silicon substrate. Thus, integrated circuits formed on FDSOI substrates provide improved performance over integrated circuits formed on conventional bulk silicon substrates.

More specifically, it has heretofore been difficult to scale the thickness of the device layer of an FDSOI substrate for transistors formed thereon. As understood in the present disclosure, a transistor formed on an FDSOI substrate has a source region and a drain region spaced apart from each other by a channel region, wherein the source region, the drain region, and the channel region are each disposed in a semiconductor device layer of the FDSOI substrate. Thus, such a transistor can be said to have a length (L) which is the shortest distance between the outer edges of the gate and/or between the nearest edges of the source and drain regions, and a width (W) which is the shortest distance between the outer edges of the gate measured perpendicular to said length (L). With the development of successive technology nodes, transistor shrinking on integrated circuits typically means that the length and width of the smallest sized transistors are reduced such that the number of transistors placed in a unit area doubles every approximately 18 months. To properly scale the channel and/or gate length (L), aspects of the present disclosure understand that it is desirable to also scale the thickness of the semiconductor device layer in the channel region of the transistor as the channel/gate length is scaled. For example, in some cases, the thickness of semiconductor device layers in the channel region of transistors is scaled to less than 40 angstroms. Scaling the channel thickness in this manner may improve device performance, such as Ion/Ioff ratio (Ion/Ioff ratio), sub-threshold voltage swing (sub-threshold voltage swing), and/or other characteristics of the transistor.

Fig. 1A illustrates a cross-sectional view of an Integrated Circuit (IC)100 having transistors, and fig. 1B illustrates a top view of the integrated circuit 100, showing the width (W) and length (L) of the transistors, according to some embodiments. As can be seen in fig. 1A, the integrated circuit 100 includes an FDSOI substrate 102, the FDSOI substrate 102 including a base substrate 104, an insulator layer 106 located over the base substrate 104, and a semiconductor device layer 108 located over the insulator layer 106. In some embodiments, semiconductor device layer 108 comprises monocrystalline silicon and has a maximum thickness t in a range of 40 angstroms to 100 angstroms _D. Insulator layer 106 can comprise silicon dioxide and can have a range of 50 angstroms to several micronsThickness t of _I. The base substrate 104 may comprise monocrystalline silicon, and is typically thicker than the semiconductor device layer 108, and may have a thickness t ranging from 400 microns to 800 microns, for example _B。

A source region 110 and a drain region 112 are provided in the semiconductor device layer 108, and the source region 110 and the drain region 112 are laterally spaced apart from each other in the semiconductor device layer 108 by a channel region 114. The source region 110 and the drain region 112 have a first conductivity type (e.g., n-type), while the channel region 114 has a second conductivity type (e.g., p-type) opposite the first conductivity type. In some embodiments, the source region 110 and the drain region 112 comprise strain-induced epitaxial material (strain-induced epitaxial material). For example, in some embodiments in which the source and drain regions 110 and 112 are n-type, the source and drain regions 110 and 112 comprise silicon phosphorous (SiP) and have a thickness in a range of 10 to 1000 angstroms. In other embodiments where the source region 110 and the drain region 112 are p-type, the source region 110 and the drain region 112 comprise silicon germanium (SiGe) and have a thickness in a range of 10 to 1000 angstroms.

A gate electrode 116, such as a metal or polysilicon gate electrode, overlies the channel region 114. A gate dielectric 120 separates the channel region 114 from the gate electrode 116. Sidewall spacer structures 118 are disposed along outer sidewalls of the gate electrode 116. The plurality of contacts 122 extend through an inter-layer dielectric (ILD)123 (e.g., silicon dioxide or a low-k dielectric material), and the plurality of metal lines 124 and the plurality of vias 126 extend through a dielectric structure 128 (e.g., an inter-metal dielectric (IMD) made of silicon dioxide or a low-k dielectric material) to form an interconnect structure 129 above the FDSOI substrate 102. A redistribution layer (RDL) structure and/or a plurality of bond pads 130 are then formed over the interconnect structures 129, and the RDL structure and/or bond pads 130 are often encapsulated by a passivation layer and/or a molding layer (not shown). In some embodiments, the contacts 122 comprise nickel or tungsten; the metal lines 124 and vias 126 comprise copper or copper alloys; and the bond pads 130 comprise aluminum. Furthermore, in some embodiments, the gate electrode 116 has an upper surface that is flush with an upper surface of the sidewall spacer structure 118.

Note that at least some portion of the channel region 114 between the source region 110 and the drain region 112 is recessed (retreated). Thus, in such a recessed region, the gate dielectric 120 and the gate electrode 116 "dip" downward, and thus the semiconductor device layer 108 has a reduced thickness (e.g., the first thickness t) in the channel region ₁) So that the first thickness t ₁Less than the maximum thickness t of the semiconductor device layer 108 _D. Scaling the channel thickness in this manner may improve device performance, such as Ion/Ioff ratio, sub-threshold voltage swing, and/or other characteristics of the transistor. For example, in various embodiments, the semiconductor device layer 108 is a single crystal silicon layer having a maximum thickness of about 70 nanometers, which is thicker than some other approaches, and the channel has a thickness less than 40 angstroms (e.g., the first thickness t) ₁Has been recessed to less than a maximum thickness t _D) This improves device performance characteristics over conventional bulk substrate transistors.

Referring to fig. 2A-2D, various illustrations can be seen that can be superimposed onto corresponding sections of fig. 1A. In fig. 2A to 2D, the channel region 114 includes: a central channel region 115; a first peripheral channel region 117a separating the source region 110 from the central channel region 115; and a second peripheral channel region 117b separating the drain region 112 from the central channel region 115. The central channel region 115 has an upper surface (e.g., surface 206) that corresponds to the recessed upper surface of the semiconductor device layer 108 and is recessed relative to the top surface 108t of the peripheral channel region. Thus, the semiconductor device layer 108 has a first (reduced) thickness t in the central channel region 115 ₁And has a second thickness t in the first and second peripheral channel regions 117a, 117b ₂. A first thickness t ₁Is less than the second thickness t ₂. In some embodiments, the second thickness t ₂Equal to the maximum thickness t of the semiconductor device layer 108 _DBut a second thickness t ₂Or less than the maximum thickness t _D。

Sidewall spacer structures 118 are disposed along outer sidewalls of the gate electrode 116. The sidewall spacer structure 118 has a bottom surface 118b that rests on the top surface 108t of the first and second peripheral channel regions 117a, 117 b.Thus, the bottom surface 118b of the sidewall spacer structure 118 has a plurality of outer regions 118o that rest on the top surface 108t of the first and second peripheral channel regions 117a, 117b, and has a plurality of overhanging regions 119 that extend inwardly beyond the top surface 108t of the first and second peripheral channel regions 117a, 117 b. The sidewall spacer structure 118 may comprise silicon nitride (e.g., Si) ₃N ₄) Silicon oxynitride (e.g., Si) ₂N ₂O), silicon carbide (e.g., SiC), or silicon oxycarbonitride (silicon oxycarbonitride), and may have a thickness in a range of 10 angstroms to 500 angstroms.

Gate dielectric 120 (e.g., silicon dioxide (SiO) ₂) Or a high-k dielectric) is disposed over the channel region 114 and separates the channel region 114 from the bottom surface of the gate electrode 116. The gate dielectric 120 contacts the bottom surface 118b of the sidewall spacer structure 118 and extends to a depth below the top surface 108t of the semiconductor device layer 108 (see fig. 2A-2D). The gate dielectric 120 includes a peripheral dielectric region having an upper surface in contact with the sidewall spacer structure 118 and a central dielectric region having an upper surface at a first height that is less than a second height of the peripheral dielectric region.

A gate electrode 116 is disposed over the channel region 114. The gate electrode 116 has a bottom surface 116b (see fig. 2A-2D), the bottom surface 116b extending below the top surface 108t of the semiconductor device layer 108. The gate electrode 116 has a central region disposed on the upper surface of the central channel region 115, and has a plurality of peripheral regions 116p located above the first and second peripheral channel regions 117a, 117 b. In some embodiments, the gate electrode 116 is a metal, such as copper or a copper alloy, aluminum, tungsten, nickel, or gold, for example. The peripheral region 116p of the gate electrode 116 extends under the overhang region 119 of the sidewall spacer structure 118.

In various embodiments, the FDSOI substrate 102 is a fully depleted semiconductor-on-insulator (FDSOI) substrate, meaning that the semiconductor device layer 108 is sufficiently thin such that, during operation, the depletion region in the channel region 114 extends completely across the depth of the semiconductor device layer 108. For example, in various embodiments, the semiconductor device layer 108 is a single crystal silicon layer having a thickness of between 5nm and 40nmIn the range, and in some cases about 10nm to 12nm thick; and insulator layer 106 is a silicon dioxide or sapphire layer (sapphire layer) having a thickness in the range of 10nm to 60nm, and in some cases about 25nm thick, which may provide FDSOI functionality. In contrast, a partially depleted SOI transistor has a semiconductor device layer that is thicker than the semiconductor device layer of the FDSOI substrate, and thus the depletion region of the channel region extends only partially through the semiconductor device layer in the Partially Depleted SOI (PDSOI) substrate (e.g., through less than 100% of the thickness of the semiconductor device layer in the PDSOI substrate). By recessing the channel to a thickness less than 40 angstroms (e.g., first thickness t) ₁Has been recessed to less than a maximum thickness t _D) Device performance characteristics are improved over conventional bulk substrate transistors.

In fig. 2A, the sidewall spacer structure 118 has sharp inner lower corners (sharp inner lower corners) 202, wherein the lower surface 118b and the sidewall surface of the sidewall spacer structure 118 are flat and meet at an angle of 90 degrees. The gate dielectric 120 is relatively thin and extends conformally over the channel region 114 along the recessed surface in the semiconductor device layer 108. This recessed surface has a peripheral region with sloped sidewalls 204a, 204b and a central region with a substantially horizontal or flat bottom surface (e.g., surface 206). The sloped sidewalls meet the central region at an obtuse angle greater than 90 degrees, and the apex of the obtuse angle (the point where the central region meets the sloped sidewalls) is located under the sidewall spacer structure 118 due to undercutting in the etch used to form the recessed surface during gate replacement. Thus, in fig. 2A, the top surface 120 of the gate dielectric 120 is completely confined below the bottom surface 118b of the sidewall spacer structure 118, and the gate electrode 116 has a lower peripheral region (e.g., the peripheral region 116p) that encroaches below the sidewall spacer structure 118. In some embodiments, the height of the upper surface of the central portion of the gate dielectric 120 (which contacts the bottom surface 116b of the gate electrode 116) is lower than the height of the bottom surface 118b of the sidewall spacer structure 118 and lower than the height corresponding to the bottom extent of the source region 110 and the drain region 112.

In fig. 2B, the sidewall spacer structure 118 again has sharp interior lower corners, where the lower surface 118B and the inner sidewall surface of the sidewall spacer structure 118 are flat and meet at a 90 degree angle. However, the gate dielectric 120 in fig. 2B is relatively thick, and may be, for example, 10nm to 50nm thick, and extends conformally over the channel region 114 along the recessed surface in the semiconductor device layer 108. The sloped sidewalls 204a, 204b again meet the central region at an obtuse angle greater than 90 degrees, and the apex of the obtuse angle (the point where the central region meets the sloped sidewalls) is directly below the sidewall spacer structure 118 due to undercutting in the etch used to form the recessed surface during gate replacement. Thus, in fig. 2B, the top surface of the gate dielectric 120 extends upward along the inner sidewall surface of the sidewall spacer structure 118 (see 132). In some embodiments, the height of the upper surface of the central portion of the gate dielectric 120 (which contacts the bottom surface 116b of the gate electrode 116) is still lower than the height of the bottom surface 118b of the sidewall spacer structure 118, but is now higher than the height corresponding to the bottom extent of the source region 110 and the drain region 112.

In fig. 2C, the sidewall spacer structure 118 has a bottom corner (or inner lower corner) with a rounded profile 250 due to undercutting in the etch used to form the recessed surface during gate replacement, but otherwise fig. 2C corresponds to fig. 2A.

In fig. 2D, the sidewall spacer structure 118 has bottom interior corners with rounded contours 252 due to undercutting in the etch used to form the recessed surface during gate replacement, but otherwise fig. 2D corresponds to fig. 2B.

Fig. 3 is a flow chart illustrating a method 300 of fabricating the device described above. Fig. 4 through 13A through 13B provide cross-sectional views of the above-described device at various stages of fabrication. It is understood that other processing may be performed before, during, and after the illustrated acts of method 300 to complete the formation of the device.

The method 300 begins in act 302, where a stack 400 is disposed on a semiconductor-on-insulator (SOI) substrate 102, as shown, for example, in fig. 4. In general, the SOI structure includes a semiconductor device layer 108 located over an insulator layer 106, the semiconductor device layer 108 being, for example, silicon in a single crystal form. Alternatively, the semiconductor device layer 108 may be Ge, SiGe, a III-V material, or the like. The insulator layer 106 may be, for example, a Buried Oxide (BOX) layer or a silicon oxide layer. An insulator layer 106 is disposed on a base substrate 104 (typically a silicon substrate or a glass substrate). Other semiconductor bodies, such as multi-layered substrates or graded substrates, may also be used.

The stack 400 also includes one or more layers provided for the sacrificial gate stack. Fig. 4 provides an example of a stack 400 including a dielectric layer 402 and an electrode layer 404. In some embodiments, the dielectric layer 402 comprises silicon dioxide, silicon nitride, silicon oxynitride, or a high-k dielectric. Electrode layer 404 is formed from a sacrificial material, such as polysilicon. Thus, the dielectric layer 402 and the electrode layer 404 are sacrificial materials and may be formed using a variety of materials that vary depending on the process used.

The method 300 of fig. 3 continues with act 304 of patterning the stack 400. Fig. 5 provides an example of patterning to define the location of gate 502 and removing gate stack 400 from over source region 504 and drain region 506. The patterning generally includes: providing a photolithographic mask (e.g., a photoresist mask), performing photolithography to pattern the mask, and performing etching to transfer the pattern of the mask to the underlying layer. The photolithographic mask is then removed to yield the structure shown in fig. 5.

The method 300 continues with act 306 by forming spacer structures adjacent to the outer edges of the gates, as shown in the example of fig. 6. The sidewall spacer structure 118 can be formed by conformally depositing a dielectric layer over the structure of fig. 5, and then etching back the dielectric layer using a vertical etch. In some embodiments, the sidewall spacer structure 118 comprises a silicon nitride layer. In alternative embodiments, the sidewall spacer structure 118 includes one or more layers of suitable materials. Suitable materials may include, for example, silicon dioxide, silicon nitride, silicon oxynitride (SiON), or silicon carbide (SiC). The spacer material may be deposited using any suitable technique. Suitable techniques may include, for example, Plasma Enhanced Chemical Vapor Deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), and the like. The sidewall spacer structures 118 may be patterned by any suitable process, such as anisotropic etching.

The method 300 continues with act 308 by forming a plurality of trenches 702 in the SOI substrate 102 at desired locations of the source and drain regions, such as shown in fig. 7.

As shown on the left side of FIG. 7, in some embodiments act 308 is an anisotropic wet etch process. The anisotropic wet etching may be a selective wet etching process according to the crystal surface orientation. The etching may be performed using, for example, a tetra-methyl ammonium hydroxide (TMAH) solution having a volume concentration ranging from 1% to 10% and a temperature ranging from 15 ℃ to 50 ℃. In some embodiments, the solution is suitable for etching a single crystal semiconductor device layer. The anisotropic etch may produce a trench 702 having a tip (tip) 704. In some embodiments, the tip 704 is a distance of 6nm or less than 6nm below the top surface 214 of the semiconductor device layer 108 that will become the surface of the channel region. In some embodiments, the tip 704 is 3nm or less than 3nm below the top surface of the semiconductor device layer 108, e.g., 2nm below. In some embodiments, the trench 702 may leave a thickness of approximately 25 angstroms of the semiconductor device layer 108 in place under the bottom tip (cusp) of the trench 702. In some embodiments, tips 704 may also extend inward beyond the outermost edges of sidewall spacer structures 118 by a distance of 5 angstroms or less than 5 angstroms.

As shown on the right side of fig. 7, in other embodiments, act 308 is an anisotropic dry etch process that produces a cubic-shaped trench. In general, the shallower the trench 702, the better, and for example, the cubic trench may have a depth of 6nm or less than 6nm below the top surface 214 of the semiconductor device layer 108. In some embodiments, the cubic trench may leave a thickness of approximately 25 angstroms of the semiconductor device layer 108 in place below the bottom surface of the trench 702.

In some embodiments of method 300, a plurality of pocket/halo regions (pockets/haloregions) are implanted after act 308. The pocket region may be implanted with, for example, a charge neutral dopant that inhibits diffusion of an electrically active dopant, such as phosphorus. Examples of dopants that may be suitable for this purpose include nitrogen and fluorine. The pocket implants may be formed by any suitable ion implantation process. Alternatively, the pocket regions may be formed by implanting opposite conductivity dopants, such as p-type dopants for n-type transistors.

The method 300 of fig. 3 continues with act 310 of forming a plurality of strain-inducing source/drain regions 110, 112 in the trench 702 to form a structure such as that shown in fig. 8. The source/drain regions 110, 112 are highly doped to be conductive and apply a tensile stress to the channel region 114 of the semiconductor device layer 108. This is accomplished by forming the source/drain regions 110, 112 from a crystalline material having a lattice structure that is smaller than the lattice structure of the channel region 114. For example, where the channel region is silicon, source/drain regions comprising SiC or SiGe may provide a desired lattice structure. The addition of n-type or p-type dopants such as phosphorus or boron will provide the desired conductivity. The source/drain regions may be formed, for example, by epitaxial growth. The epitaxial growth is typically carried out at a temperature of 690 c or below 690 c. A thermal anneal may then be performed in act 312 to drive the dopants to achieve a desired doping profile and repair lattice damage, such as that which occurs due to ion implantation, and an interlayer dielectric (ILD)123 may be formed over the source/drain regions 110, 112 and over other portions of the structure. An ILD chemical-mechanical polishing (CMP) is then performed to planarize the interlayer dielectric 123 and stop when the upper surface of the sacrificial gate stack is exposed. As shown on the left side of fig. 8, in some embodiments the strained source/drain regions 110, 112 may have a diamond shape, while in other embodiments shown on the right side of fig. 8, the strained source/drain regions 110, 112 may have a cubic shape, such as a square prism or a rectangular prism.

The method 300 of fig. 3 continues with act 314 by forming a gate recess by removing the sacrificial gate stack to form a structure such as that shown in fig. 9. The sacrificial gate stack may be removed by performing a selective etch (e.g., dry etch or dry wet etch) and under-voltageStopping on the gate dielectric 402 or the semiconductor device layer 108 to form a gate recess. Cl with low power in case of poly gate stack ₂/BCl ₃For dry selective etching, and NH ₄The OH/TMAH is used for wet selective etching and stops on the gate dielectric 402. Another chemical etchant such as, for example, dilute wet HF or gaseous HF is applied to remove the gate dielectric 402 and expose the channel region of the semiconductor device layer 108.

The method 300 of fig. 3 continues with act 316 of extending the gate recess into the semiconductor device layer 108 of the SOI substrate 102, for example as shown in fig. 10. In some embodiments, extension of the gate recess may be achieved by performing an alkaline wet etch (alkali wet etch). In some embodiments, act 316 is an isotropic wet etch process (Isotropic wet process). The etching may use, for example, a tetramethylammonium hydroxide (TMAH) solution having a volume concentration in the range of 1% to 10% and a temperature in the range of 15 ℃ to 50 ℃. In some embodiments, TMAH may have a volume concentration between 2% and 3%, and thus the wet etch may have an etch rate of approximately 60 angstroms/minute at 100 ℃. In other embodiments, the alkaline wet etch may use an ammonia solution (NH) ₄OH) with an etch rate of about 40 angstroms/minute. The etch extends the gate recess down to thin the semiconductor device layer 108, for example from an initial thickness of 40 or 70 angstroms to a thinned thickness of less than 40 angstroms, or even less than 30 angstroms. Since the etch is isotropic, the etch also undercuts the bottom surface of the sidewall spacer structure 118 and provides a recessed surface having sloped sidewalls that meet the bottom surface of the recessed surface at an obtuse angle in the range of about 92 to 145 degrees in some embodiments.

The method 300 of fig. 3 continues with act 318 by forming a replacement gate dielectric 120 on the thinned semiconductor device layer 108 of the SOI substrate 102, such as shown in fig. 11A. The replacement gate dielectric 120 may be formed by a thermal oxidation process, a chemical oxidation, a CVD process, a PVD process, a PECVD process, a spin-on dielectric, or other suitable process to form the lower gate dielectric 1102. A high-k deposition process is then performed to form an upper gate dielectric 1104 made of a high-k dielectric material, the upper gate dielectric 1104 overlying the lower gate dielectric 1102 and lining the inner sidewalls of the sidewall spacer structures 118. Thus, in some embodiments, the lower gate dielectric 1102 is made of a first dielectric material (e.g., silicon dioxide) and the upper gate dielectric 1104 is made of a second dielectric material (e.g., a high-k dielectric material different from the first dielectric material).

The method 300 of fig. 3 continues with act 320 of forming a gate electrode 116 in the form of a replacement metal gate over the replacement gate dielectric 120 to fill the gate recess, for example, as shown in fig. 11A. In some embodiments, such as shown in fig. 11A, the lower gate dielectric 1102 is relatively thin such that the peripheral region of the gate electrode 116 is located below the bottom surface of the sidewall spacer structure 118. However, in other embodiments, such as that shown in FIG. 11B, the lower gate dielectric 1102 is relatively thick such that the gate dielectric 120 extends up the lower sidewalls of the sidewall spacer structures 118.

Fig. 12 illustrates an alternative embodiment in which the etch performed in act 316 has a lateral component with respect to the sidewall spacer structure 118, such that the etch of act 316 etches the sidewall spacer structure 118 to round the lower interior corners of the sidewall spacer structure 118. Again, a lower gate dielectric 1102 and an upper gate dielectric 1104 are formed on the thinned semiconductor device layer 108 of the SOI substrate 102, for example as shown in fig. 13A. The replacement gate dielectric 120 may be formed by a thermal oxidation process, a chemical oxidation process, a CVD process, a PVD process, a PECVD process, a spin-on dielectric, or other suitable process. In some embodiments, such as shown in fig. 13A, the lower gate dielectric 1102 is relatively thin such that the peripheral region of the gate electrode 116 is located below the bottom surface of the sidewall spacer structure 118. However, in other embodiments, such as that shown in FIG. 13B, the lower gate dielectric 1102 is relatively thick such that the lower gate dielectric 1102 extends up the lower sidewalls of the sidewall spacer structures 118.

Some embodiments relate to Integrated Circuits (ICs) disposed on a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a base substrate, an insulator layer located over the base substrate, and a semiconductor device layer located over the insulator layer. The source and drain regions are disposed in the semiconductor device layer. The source and drain regions have a first conductivity type. A channel region is disposed in the semiconductor device layer and separates the source region from the drain region. The channel region has a second conductivity type opposite the first conductivity type. The channel region includes: a central region; a first peripheral region separating the source region from the central region; and a second peripheral region separating the drain region from the central region. The central region has an upper surface that is recessed relative to an upper surface of the peripheral region such that the semiconductor device layer has a first thickness in the central region of the channel region and a second thickness in the peripheral region of the channel region. The first thickness is less than the second thickness.

According to some embodiments, the integrated circuit further comprises: a sidewall spacer structure disposed over the first and second peripheral regions, wherein a bottom surface of the sidewall spacer structure has a plurality of outer regions resting on the upper surfaces of the first and second peripheral regions, and the bottom surface of the sidewall spacer structure has a plurality of overhanging regions extending inwardly beyond the upper surfaces of the first and second peripheral regions. In the integrated circuit, according to some embodiments, the sidewall spacer structure has a bottom interior corner with a rounded profile. According to some embodiments, the integrated circuit further comprises: a gate dielectric disposed over the channel region, the gate dielectric including a peripheral dielectric region having an upper surface contacting the plurality of overhang regions and a central dielectric region having an upper surface at a first height, the first height being less than a second height of the peripheral dielectric region. In accordance with some embodiments, in the integrated circuit, the gate dielectric extends up a plurality of innermost sidewalls of the sidewall spacer structure. According to some embodiments, the integrated circuit further comprises: a gate electrode disposed over the gate dielectric and separated from the channel region by the gate dielectric, the gate electrode having a central region disposed on the upper surface of the central dielectric region and having a peripheral region disposed over the peripheral dielectric region. In accordance with some embodiments, in the integrated circuit, the peripheral region of the gate electrode extends under the plurality of overhang regions of the sidewall spacer structure. In accordance with some embodiments, in the integrated circuit, the peripheral region of the gate electrode is located entirely within a plurality of innermost sidewalls of the sidewall spacer structure. According to some embodiments, in the integrated circuit, the upper surface of the peripheral dielectric region is completely confined below an inner region of the bottom surface of the sidewall spacer structure. In accordance with some embodiments, in the integrated circuit, the channel region located below the bottom surface of the gate electrode corresponds to the semiconductor device layer and has a thickness of less than 40 angstroms. In the integrated circuit, according to some embodiments, the gate electrode has an upper surface that is flush with an upper surface of the sidewall spacer structure.

Other embodiments relate to an Integrated Circuit (IC). The integrated circuit includes a semiconductor-on-insulator (SOI) substrate including a base substrate, an insulator layer over the base substrate, and a semiconductor device layer over the insulator layer. The source and drain regions are disposed in the semiconductor device layer and are spaced apart from each other in the semiconductor device layer by a channel region. A gate electrode is disposed over the channel region. The gate electrode has a bottom surface extending below a top surface of the semiconductor device layer. Sidewall spacer structures are disposed along outer sidewalls of the gate electrode. The sidewall spacer structure has a bottom surface that rests on a top surface of a semiconductor device layer. A gate dielectric is disposed over the channel region and separates the channel region from a bottom surface of the gate electrode. The gate dielectric contacts a bottom surface of the sidewall spacer structure and extends to a depth below a top surface of the semiconductor device layer. The channel region located below the bottom surface of the gate electrode corresponds to a semiconductor device layer and has a thickness of less than 40 angstroms.

In the integrated circuit, according to some embodiments, the sidewall spacer structure has a bottom interior corner with a rounded profile. In the integrated circuit, according to some embodiments, the gate electrode has an upper surface that is flush with an upper surface of the sidewall spacer structure.

Other embodiments relate to a method of manufacturing an integrated circuit. In the method, a semiconductor-on-insulator (SOI) substrate is received. The SOI substrate includes a base substrate, an insulator layer located over the base substrate, and a semiconductor device layer located over the insulator layer. A sacrificial gate stack is formed over the semiconductor device layer, and a sidewall spacer structure is formed around outer sidewalls of the sacrificial gate stack. A plurality of trenches is formed in the semiconductor device layer on outer edges of the sidewall spacer structures. A source region and a drain region are epitaxially formed in the trench. The sacrificial gate stack is removed to form a gate recess between inner sidewalls of the sidewall spacer structure. Extending the gate recess into the semiconductor device layer, wherein the semiconductor device layer remaining under the extended gate recess corresponds to a channel region separating the source region from the drain region. A replacement gate dielectric is formed over the channel region and a replacement metal gate electrode is formed over the replacement gate dielectric. The replacement metal gate electrode has a bottom surface that extends below a top surface of the semiconductor device layer.

In accordance with some embodiments, in the method, extending the gate recess laterally removes portions of the semiconductor device layer underlying the plurality of inner sidewalls of the sidewall spacer structure. In accordance with some embodiments, in the method, the replacement metal gate electrode extends below the plurality of inner sidewalls of the sidewall spacer structure. According to some embodiments, in the method, the gate dielectric contacts a bottom surface of the sidewall spacer structure and extends to a depth below the top surface of the semiconductor device layer. In accordance with some embodiments, in the method, an upper surface of the gate dielectric is disposed at a first height that is less than a second height corresponding to the top surface of the semiconductor device layer. According to some embodiments, in the method, the channel region has a thickness of less than 40 angstroms.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.