Semiconductor device and method of forming a semiconductor device
阅读说明:本技术 半导体器件以及形成半导体器件的方法 (Semiconductor device and method of forming a semiconductor device ) 是由 吴家扬 张简旭珂 王廷君 游咏晞 于 2019-07-30 设计创作,主要内容包括:根据本申请的实施例,提供了一种半导体器件。该半导体器件包括具有源极/漏极和栅极的晶体管。半导体器件也包括用于晶体管的导电接触件。导电接触件提供至晶体管的源极/漏极或栅极的电连接。导电接触件包括多个阻挡层。阻挡层具有彼此不同的深度。根据本申请的实施例,还提供了另一种半导体器件以及一种形成半导体器件的方法。(According to an embodiment of the present application, there is provided a semiconductor device. The semiconductor device includes a transistor having source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contacts provide electrical connections to the source/drain or gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from each other. According to embodiments of the present application, there is also provided another semiconductor device and a method of forming a semiconductor device.)
1. A semiconductor device, comprising:
a transistor having a source/drain and a gate; and
a conductive contact for the transistor, the conductive contact providing an electrical connection to the source/drain or the gate of the transistor;
wherein:
the conductive contact comprises a plurality of barrier layers; and
the barrier layers have different depths from each other.
2. The semiconductor device of claim 1, wherein the plurality of barrier layers have a stepped profile in cross-section.
3. The semiconductor device of claim 1, wherein the barrier layers have different material compositions from each other.
4. The semiconductor device of claim 1, wherein:
the conductive contact includes a metal portion surrounded by the barrier layer;
the barrier layer comprises a first barrier layer, a second barrier layer and a third barrier layer;
the first barrier layer is in direct physical contact with a portion of the second barrier layer;
the second barrier layer is in direct physical contact with a portion of the third barrier layer; and
the third barrier layer is in direct physical contact with a metal portion of the conductive contact.
5. The semiconductor device of claim 4, wherein:
the first barrier layer has a first length extending down into the dielectric layer;
the second barrier layer has a second length extending downward into the dielectric layer, the second length being greater than the first length; and
the third barrier layer has a third length extending downward into the dielectric layer, the third length being greater than the second length.
6. The semiconductor device of claim 4, wherein:
the first barrier layer comprises TaN;
the second barrier layer comprises at least one of TaN, Ta, Ti, and TiN; and
the third barrier layer comprises at least one of Co, Ni, Ti, and TiN.
7. The semiconductor device according to claim 1, wherein an upper portion of the conductive contact is surrounded by (n +1) barrier layers, a central portion is surrounded by n barrier layers, and a bottom portion is surrounded by (n-1) barrier layers, where n is a natural number equal to or greater than 2.
8. A semiconductor device, comprising:
a transistor having a source/drain component and a gate component; and
a conductive contact formed over the source/drain component or over the gate component of the transistor;
wherein:
the conductive contact includes a metal portion surrounded by a plurality of barrier layers; and
the length of each of the barrier layers is related to the distance of the barrier layer from the metal portion.
9. The semiconductor device of claim 8, wherein a depth decreases with increasing distance from the metal portion.
10. A method of forming a semiconductor device, comprising:
providing a transistor having a source/drain and a gate, wherein a dielectric material is formed over the transistor;
performing a plurality of etch and deposition cycles to form a plurality of barrier layers of conductive contacts of the transistor, wherein each cycle comprises an etch process to etch openings in the dielectric material and a deposition process to deposit a respective barrier layer in the etched openings, wherein the barrier layers are formed to have different depths from one another; and
the final opening etched by the last cycle is filled with a conductive material, thereby forming a conductive contact of the transistor.
Technical Field
Embodiments of the present application relate to the field of semiconductors, and more particularly, to semiconductor devices and methods of forming semiconductor devices.
Background
The semiconductor Integrated Circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have resulted in generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are required in order to achieve these advances. In the course of IC evolution, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometry (i.e., the smallest component that can be produced using a fabrication process) has decreased.
However, conventional semiconductor devices may still have certain drawbacks. For example, conductive contacts may be formed to provide electrical connections for active devices such as transistors or passive devices such as resistors, capacitors, inductors, and the like. To form such a conductive contact, a contact opening may be formed and then filled with a conductive material. However, the contact opening of the conventional semiconductor device is generally formed to have a vase or oval-like shape. Such shapes may result in difficulty filling the openings, which may reduce device performance or yield.
Thus, while existing semiconductor devices and their manufacture are generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.
Disclosure of Invention
According to an embodiment of the present application, there is provided a semiconductor device including: a transistor having a source/drain and a gate; and a conductive contact for the transistor, the conductive contact providing an electrical connection to the source/drain or the gate of the transistor; wherein: the conductive contact comprises a plurality of barrier layers; and the barrier layers have different depths from each other.
According to an embodiment of the present application, there is also provided a semiconductor device including: a transistor having a source/drain component and a gate component; and a conductive contact formed over the source/drain component or over the gate component of the transistor; wherein: the conductive contact includes a metal portion surrounded by a plurality of barrier layers; and a length of each of the barrier layers is related to a distance of the barrier layer from the metal portion.
There is also provided, in accordance with an embodiment of the present application, a method of forming a semiconductor device, including: providing a transistor having a source/drain and a gate, wherein a dielectric material is formed over the transistor; performing a plurality of etch and deposition cycles to form a plurality of barrier layers of conductive contacts of the transistor, wherein each cycle comprises an etch process to etch openings in the dielectric material and a deposition process to deposit a respective barrier layer in the etched openings, wherein the barrier layers are formed to have different depths from one another; and filling the final opening etched by the last cycle with a conductive material, thereby forming a conductive contact of the transistor.
Drawings
Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion. It is also to be emphasized that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other embodiments as well.
Fig. 1 is a perspective view of an exemplary FinFET transistor.
Fig. 2 illustrates a top view of a semiconductor device including a plurality of FinFET transistors, according to an embodiment of the present disclosure.
Fig. 3-14 and 15A-15B illustrate cross-sectional side views of a FinFET transistor at various stages of fabrication, according to embodiments of the present disclosure.
Fig. 16 is a flow chart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present invention may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element (or other) component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Further, as will be understood by those of skill in the art, when a value or range of values is described with "about," "about," etc., the term is intended to encompass values within a reasonable range including the recited value, such as +/-10% of the recited value or other values. For example, the term "about 5 nm" encompasses the size range of 4.5nm to 5.5 nm.
In the pursuit of higher device density, higher performance and lower cost, the semiconductor industry has entered the nanotechnology process node. However, conventional semiconductor fabrication methods may still have drawbacks. For example, to provide electrical connections for semiconductor devices, conductive contacts may be formed over active devices such as transistors or passive devices such as resistors or capacitors. The formation of the conductive contacts may include etching contact openings in the dielectric structure and subsequently filling the openings with a conductive material, such as a metal. However, the contact openings formed in conventional semiconductor devices may have oval or vase-like cross-sectional side profiles, e.g. wider in the middle but narrower at the top and/or bottom. Such a profile may result in difficulty in filling the contact openings with conductive material. Incomplete filling of the contact holes may reduce device performance or yield.
To improve device performance, the present disclosure forms conductive contacts with multiple barrier layers. Multiple barrier layers are formed by multiple etch-deposition cycles, wherein contact openings are etched (or extended downward) in each cycle, followed by deposition of a different barrier layer. In some of these etch-deposition cycles, a sputtering process is also performed to remove the bottom section of the deposited barrier layer to facilitate subsequent etching of the contact opening. Due to this unique manufacturing process flow, the plurality of barrier layers are formed to have a stepped profile in a cross-sectional view. The resulting contact opening does not have a vase-like shape but a shape that is wider at the top and narrower at the bottom, making it easier to fill. The individual barrier layers can also have different material compositions, which makes them possible to function differently.
Various aspects of the disclosure are discussed in more detail below with reference to fig. 1-14 and 15A-15B. As non-limiting examples illustrating various aspects of the present disclosure, fin field effect transistor (FinFET) devices are discussed with reference to fig. 1-14 and 15A-15B. However, it should be understood that aspects of the present disclosure are not limited to any particular type of device unless explicitly stated otherwise.
The use of FinFET devices is becoming increasingly popular in the semiconductor industry. Referring to fig. 1, a perspective view of an
L
GIndicating the length (or width, depending on the perspective view) of the
Fig. 2 is a simplified top view of a
The different cross-sectional views of the
Referring to fig. 3, a
The
An isolation structure such as a Shallow Trench Isolation (STI) is formed over the semiconductor layer, but since the location of the X cut is employed here, the isolation structure may not be directly visible in fig. 3. The isolation structure may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. The isolation structures provide electrical isolation between the various microelectronic components of the
Portions of the
The
In some embodiments, the
The ILD1 layer may be formed after the formation of
Similarly, another etch process similar to
Referring now to fig. 4, a
It should be understood that
Referring now to fig. 5, a
In some embodiments, the
Referring now to fig. 6, an etch process 500 is performed on the
Referring now to fig. 7, a
As shown in fig. 7,
Similar to the
Referring now to fig. 8, a re-sputtering process 600 is performed on the
Referring now to fig. 9, an
Referring now to fig. 10, a deposition process 750 is performed to form a
As shown in fig. 10,
As shown in fig. 10, the
Similar to the deposition processes 350 and 550, the deposition process 750 may also include a sputtering process, and the deposition process 750 may be performed via the same manufacturing tool that performed the deposition processes 350 and 550. Unlike barrier layers 360 and 560, no resputtering process need be performed on
Referring now to fig. 12,
Based on the above discussion, it can be seen that the present disclosure utilizes a unique method to form the
The plurality of barrier layers 360/560/760 formed herein also have a unique profile, such as a stepped (or trapezoidal) profile in cross-sectional side view. For example, the depth (in the Z-direction) of
It should be understood that although three
Furthermore, the source/drain contacts and the gate contact may have different numbers of barrier layers in some embodiments, or the same number of barrier layers in other embodiments.
Fig. 15A to 15B show partial sectional side views of a part of a
In fig. 15A through 15B, the
Fig. 16 is a flow chart illustrating a
The
The
In some embodiments, at least some of the cycles further include a re-sputtering process performed between the etching process and the deposition process. And removing the bottom section of the deposited barrier layer by a sputtering process. In some embodiments, the deposition process and the re-sputtering process are performed using the same semiconductor manufacturing tool.
In some embodiments, the plurality of etch and deposition cycles are performed as follows: a first etch process is performed to etch openings in the dielectric material. The opening is over a source/drain or over a gate of the FinFET transistor. Thereafter, a first barrier layer is deposited in the opening. The first barrier layer includes sidewall segments connected by a bottom segment. The bottom section of the first barrier layer is then removed. After removing the bottom section of the first barrier layer, a second etching process is performed to extend the opening downward. After performing the second etching process, a second barrier layer is deposited in the opening. The second barrier layer includes sidewall segments connected by a bottom segment. Portions of the sidewall sections of the second barrier layer are formed on the sidewall sections of the first barrier layer. Thereafter, the bottom section of the second barrier layer is removed. After removing the bottom section of the second barrier layer, a third etching process is performed to extend the opening further down. After the third etch process, a third barrier layer is deposited in the opening. The third barrier layer includes sidewall segments connected by a bottom segment. Portions of the sidewall sections of the third barrier layer are formed on the sidewall sections of the second barrier layer. The openings are then filled with a conductive material to form conductive contacts. In some embodiments, an annealing process is performed after depositing the third barrier layer but before filling the opening with the conductive material. The annealing process promotes a reaction between the third barrier layer and portions of the underlying source/drain, forming a contact silicide layer. In some embodiments, the first barrier layer, the second barrier layer, and the third barrier layer are formed to have different material compositions from each other. For example, in an embodiment, the first barrier layer is formed to contain TaN, the second barrier layer is formed to contain TaN, Ta, Ti, or TiN, and the third barrier layer is formed to contain Co, Ni, Ti, or TiN.
In some embodiments, the opening is filled with a tungsten-containing material. The tungsten-containing material may be formed in direct physical contact with the sidewall segments and the bottom segment of the third barrier layer.
In some embodiments, the upper portion of the conductive contact is surrounded by (n +1) barrier layers, the central portion is surrounded by n barrier layers, and the bottom portion is surrounded by (n-1) barrier layers, where n is a natural number equal to or greater than 2.
It should be understood that additional processes may be performed before, during, or after
Based on the above discussion, it can be seen that the present disclosure provides advantages over conventional FinFET devices. However, it is to be understood that other embodiments may provide additional advantages, and that not all advantages need be disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that the present invention forms contact openings with profiles that are easily filled. This is achieved by multiple cycles of the etching and deposition processes discussed above. Another advantage is that different barrier layers can be used for different purposes, since they can have different material compositions and be in different locations. Yet another advantage is that the present disclosure improves silicide formation for contacts. For example, the later-formed barrier layer may react with the underlying layers to form a contact silicide layer, which may have a larger volume than a conventional silicide layer. Yet another advantage is that the process of the present disclosure is easy to implement, e.g., barrier deposition and re-sputtering can be implemented in the same manufacturing tool. Other advantages include compatibility with existing FinFET fabrication, so the present disclosure does not require additional processes, and is therefore easy and inexpensive to implement.
One aspect of the present disclosure relates to a semiconductor device. The semiconductor device has a transistor having source/drain and a gate. The semiconductor device has a conductive contact for a transistor. The conductive contacts provide electrical connections to the source/drain or gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from each other.
Another aspect of the present disclosure relates to a semiconductor device. The semiconductor device has a transistor having source/drain components and a gate component. The semiconductor device has a conductive contact formed over a source/drain component or over a gate component of the transistor. The conductive contact includes a metal portion surrounded by a plurality of barrier layers. The length of each barrier layer is related to the distance of the barrier layer from the metal portion.
Another aspect of the present disclosure relates to a method. The method comprises the step of providing a transistor having a source/drain and a gate. A dielectric material is formed over the FinFET transistor. The method includes the step of performing a plurality of etch and deposition cycles to form a plurality of barrier layers for conductive contacts of the transistor. Each cycle includes an etching process to etch an opening in the dielectric material and a deposition process to deposit a corresponding barrier layer in the etched opening. The barrier layers are formed to have different depths from each other. The method comprises the step of filling the final opening etched by the last cycle with a conductive material, thereby forming a conductive contact of the transistor.
According to an embodiment of the present application, there is provided a semiconductor device including: a transistor having a source/drain and a gate; and a conductive contact for the transistor, the conductive contact providing an electrical connection to the source/drain or the gate of the transistor; wherein: the conductive contact comprises a plurality of barrier layers; and the barrier layers have different depths from each other.
According to an embodiment of the application, the plurality of barrier layers has a stepped profile in a cross-sectional view.
According to an embodiment of the application, the barrier layers have different material compositions from each other.
According to an embodiment of the application, wherein: the conductive contact includes a metal portion surrounded by the barrier layer; the barrier layer comprises a first barrier layer, a second barrier layer and a third barrier layer; the first barrier layer is in direct physical contact with a portion of the second barrier layer; the second barrier layer is in direct physical contact with a portion of the third barrier layer; and the third barrier layer is in direct physical contact with the metal portion of the conductive contact.
According to an embodiment of the application, wherein: the first barrier layer has a first length extending down into the dielectric layer; the second barrier layer has a second length extending downward into the dielectric layer, the second length being greater than the first length; and the third barrier layer has a third length extending downward into the dielectric layer, the third length being greater than the second length.
According to an embodiment of the application, wherein: the first barrier layer comprises TaN; the second barrier layer comprises at least one of TaN, Ta, Ti, and TiN; and the third barrier layer comprises at least one of Co, Ni, Ti, and TiN.
According to an embodiment of the present application, an upper portion of the conductive contact is surrounded by (n +1) barrier layers, a central portion is surrounded by n barrier layers, and a bottom portion is surrounded by (n-1) barrier layers, where n is a natural number equal to or greater than 2.
According to an embodiment of the present application, there is also provided a semiconductor device including: a transistor having a source/drain component and a gate component; and a conductive contact formed over the source/drain component or over the gate component of the transistor; wherein: the conductive contact includes a metal portion surrounded by a plurality of barrier layers; and a length of each of the barrier layers is related to a distance of the barrier layer from the metal portion.
According to an embodiment of the application, the depth decreases with increasing distance from the metal portion.
According to an embodiment of the application, wherein: the barrier layer comprises a first barrier layer, a second barrier layer and a third barrier layer; the first barrier layer is located furthest away from the metal portion and includes a sidewall section having a first depth; the third barrier layer is located closest to the metal portion and includes a sidewall section having a third depth; the second barrier layer is located between the first barrier layer and the third barrier layer and includes a sidewall section having a second depth; the first depth is less than the second depth; and the second depth is less than the third depth.
According to an embodiment of the application, wherein: the third barrier layer is in direct physical contact with the metal portion of the conductive contact; the entire second barrier layer is in direct physical contact with a portion of the third barrier layer; and the entire first barrier layer is in direct physical contact with a portion of the second barrier layer.
According to an embodiment of the application, wherein: the metal portion comprises at least one of W and Co; the first barrier layer comprises TaN; the second barrier layer comprises at least one of TaN, Ta, Ti, and TiN; and the third barrier layer comprises at least one of Co, Ni, Ti, and TiN.
There is also provided, in accordance with an embodiment of the present application, a method of forming a semiconductor device, including: providing a transistor having a source/drain and a gate, wherein a dielectric material is formed over the transistor; performing a plurality of etch and deposition cycles to form a plurality of barrier layers of conductive contacts of the transistor, wherein each cycle comprises an etch process to etch openings in the dielectric material and a deposition process to deposit a respective barrier layer in the etched openings, wherein the barrier layers are formed to have different depths from one another; and filling the final opening etched by the last cycle with a conductive material, thereby forming a conductive contact of the transistor.
According to an embodiment of the application, at least some of the cycles further comprise a re-sputtering process performed between the etching process and the deposition process, and wherein the re-sputtering process removes a bottom section of the deposited barrier layer.
According to embodiments of the present application, the deposition process and the re-sputtering process are performed using the same semiconductor manufacturing tool.
According to an embodiment of the application, performing the plurality of etch and deposition cycles comprises: performing a first etch process to etch an opening in the dielectric material, wherein the opening is located over the source/drain or over the gate of the transistor; depositing a first barrier layer in the opening, the first barrier layer comprising sidewall segments connected by a bottom segment; removing a bottom section of the first barrier layer; after the bottom section of the first barrier layer is removed, performing a second etching process to extend the opening downward; depositing a second barrier layer in the opening after the second etching process, the second barrier layer comprising sidewall segments connected by a bottom segment, wherein portions of the sidewall segments of the second barrier layer are formed on the sidewall segments of the first barrier layer; removing a bottom section of the second barrier layer; after the bottom section of the second barrier layer is removed, performing a third etching process to further extend the opening downward; depositing a third barrier layer in the opening after the third etch process, the third barrier layer comprising sidewall segments connected by a bottom segment, wherein portions of the sidewall segments of the third barrier layer are formed on the sidewall segments of the second barrier layer; and filling the opening with a conductive material.
According to the embodiment of the application, the method further comprises the following steps: an annealing process is performed after depositing the third barrier layer but before filling the opening with the conductive material.
According to an embodiment of the present application, the first barrier layer, the second barrier layer, and the third barrier layer are formed to have different material compositions from each other.
According to an embodiment of the application, wherein: the first barrier layer is formed to contain TaN; the second barrier layer is formed to contain at least one of TaN, Ta, Ti, and TiN; and the third barrier layer is formed to include at least one of Co, Ni, Ti, and TiN.
According to an embodiment of the application, filling the opening comprises filling the opening with a tungsten-containing material, and wherein the tungsten-containing material is formed in direct physical contact with a sidewall segment and a bottom segment of the third barrier layer.
The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. For example, by implementing different thicknesses for the bit line conductors and the word line conductors, different resistances of the conductors can be implemented. However, other techniques for changing the resistance of the metal conductor may also be utilized.