阅读说明：本技术 一种半导体器件的制造方法 (Method for manufacturing semiconductor device ) 是由 张超然 李赟 周俊 于 2019-11-08 设计创作，主要内容包括：本发明提供一种半导体器件的制造方法,提供衬底,所述衬底上形成有浮栅以及其上的堆叠层,所述堆叠层包括依次层叠的隔离层、控制栅和保护层,所述堆叠层的侧壁上形成有侧墙,所述堆叠层一侧为擦除栅区、另一侧为字线区,所述擦除栅区一侧的浮栅延伸至所述堆叠层以及所述侧墙之外,所述擦除栅区一侧形成有擦除栅,所述字线区一侧形成有字线；选择性去除所述保护层；在所述擦除栅、字线以及控制栅上形成接触塞。该方法无需额外的掩膜和光刻工艺,简化了制造半导体器件的工艺流程,降低了器件的制造成本。(The invention provides a manufacturing method of a semiconductor device, which comprises the steps of providing a substrate, wherein a floating gate and a stack layer on the floating gate are formed on the substrate, the stack layer comprises an isolation layer, a control gate and a protective layer which are sequentially stacked, a side wall is formed on the side wall of the stack layer, one side of the stack layer is an erasing gate region, the other side of the stack layer is a word line region, the floating gate on one side of the erasing gate region extends out of the stack layer and the side wall, an erasing gate is formed on one side of the erasing gate region, and a word line is formed on one side of the word line region; selectively removing the protective layer; and forming contact plugs on the erasing gate, the word line and the control gate. The method does not need extra mask and photoetching process, simplifies the process flow of manufacturing the semiconductor device and reduces the manufacturing cost of the device.)

1. A method of manufacturing a semiconductor device, comprising:

providing a substrate, wherein a floating gate and a stack layer on the floating gate are formed on the substrate, the stack layer comprises an isolation layer, a control gate and a protective layer which are sequentially stacked, a side wall is formed on the side wall of the stack layer, one side of the stack layer is an erasing gate region, the other side of the stack layer is a word line region, the floating gate on one side of the erasing gate region extends out of the stack layer and the side wall, an erasing gate is formed on one side of the erasing gate region, and a word line is formed on one side of the word line region;

selectively removing the protective layer;

and forming contact plugs on the erasing gate, the word line and the control gate.

2. The method of manufacturing according to claim 1, wherein the protective layer is selectively removed using wet etching.

3. The method of claim 2, wherein the erase gate, the word line, and the control gate are polysilicon, the protective layer is silicon nitride, and the wet etching uses phosphoric acid as a solution.

4. The method as claimed in claim 2, wherein the protective layer has a thickness in the range of 100-200 angstroms before selectively removing the protective layer by wet etching.

5. The manufacturing method according to any one of claims 1 to 4, wherein the floating gate and the stacked layer are formed by a method comprising:

depositing a floating gate layer, an isolation layer, a control gate and a protection layer on the substrate in sequence;

patterning the isolation layer, the control gate and the protection layer to form a stacked layer;

forming a side wall on the side wall of the stacked layer;

forming a sacrificial layer on the side wall of the side wall on one side of the stacked layer;

patterning the floating gate layer by taking the stacked layer and the sacrificial layer as masks to form a floating gate, wherein one side of the sacrificial layer is an erasing gate region, and the other side of the sacrificial layer is a word line region;

and removing the sacrificial layer.

6. The manufacturing method according to claim 5, wherein the sidewall spacer comprises a silicon oxide layer and a silicon nitride layer stacked in this order from the sidewall of the stacked layer.

7. The method as claimed in claim 5, wherein the thickness of the passivation layer deposited on the substrate is in the range of 600-700 angstroms; before selectively removing the protective layer by wet etching, the thickness of the protective layer is in the range of 100-200 angstroms.

8. The manufacturing method according to claim 5, wherein the sacrificial layer is a silicon oxide layer.

9. The method as claimed in claim 8, wherein the thickness of the sacrificial layer is in the range of 300-350 angstroms.

10. The method of manufacturing according to claim 1, wherein the step of forming the contact plug on the erase gate, the word line, and the control gate comprises:

forming a dielectric layer on the erasing gate, the word line and the control gate;

forming a contact hole in the dielectric layer;

and filling the contact hole to form the contact plug.

Technical Field

The present invention relates to semiconductor devices and manufacturing methods thereof, and more particularly, to a method for manufacturing a semiconductor device.

Background

With the continuous development of semiconductor technology, semiconductor devices including floating gate type flash memories are widely used. The floating gate type flash memory is a nonvolatile memory and has the advantages of high integration level, high storage speed, easy erasing and rewriting and the like. However, as the feature size of integrated circuits is continuously reduced, the fabrication process of semiconductor devices is complicated and the manufacturing cost is high.

Disclosure of Invention

In view of the above, an object of the present invention is to provide a method for manufacturing a semiconductor device, which simplifies the manufacturing process of the semiconductor device and reduces the manufacturing cost.

In order to achieve the purpose, the invention has the following technical scheme:

a method of manufacturing a semiconductor device, comprising:

providing a substrate, wherein a floating gate and a stack layer on the floating gate are formed on the substrate, the stack layer comprises an isolation layer, a control gate and a protective layer which are sequentially stacked, a side wall is formed on the side wall of the stack layer, one side of the stack layer is an erasing gate region, the other side of the stack layer is a word line region, the floating gate on one side of the erasing gate region extends out of the stack layer and the side wall, an erasing gate is formed on one side of the erasing gate region, and a word line is formed on one side of the word line region;

selectively removing the protective layer;

and forming contact plugs on the erasing gate, the word line and the control gate.

Optionally, the protective layer is selectively removed by wet etching.

Optionally, the erase gate, the word line and the control gate are polysilicon, the protective layer is silicon nitride, and the solution adopted in the wet etching is phosphoric acid.

Optionally, before selectively removing the protection layer by wet etching, the thickness of the protection layer ranges from 100 to 200 angstroms.

Optionally, the method for forming the floating gate and the stacked layer includes:

depositing a floating gate layer, an isolation layer, a control gate and a protection layer on the substrate in sequence;

patterning the isolation layer, the control gate and the protection layer to form a stacked layer;

forming a side wall on the side wall of the stacked layer;

forming a sacrificial layer on the side wall of the side wall on one side of the stacked layer;

patterning the floating gate layer by taking the stacked layer and the sacrificial layer as masks to form a floating gate, wherein one side of the sacrificial layer is an erasing gate region, and the other side of the sacrificial layer is a word line region;

and removing the sacrificial layer.

Optionally, the sidewall spacer includes a silicon oxide layer and a silicon nitride layer stacked in sequence from a sidewall of the stacked layer.

Optionally, the thickness of the protective layer deposited on the substrate is in the range of 600-700 angstroms; before selectively removing the protective layer by wet etching, the thickness of the protective layer is in the range of 100-200 angstroms.

Optionally, the sacrificial layer is a silicon oxide layer.

Optionally, the thickness of the sacrificial layer ranges from 300 to 350 angstroms.

Optionally, the step of forming the contact plugs on the erase gate, the word line, and the control gate includes:

forming a dielectric layer on the erasing gate, the word line and the control gate;

forming a contact hole in the dielectric layer;

and filling the contact hole to form the contact plug.

The method for manufacturing the semiconductor device provided by the embodiment of the invention comprises the steps of forming a floating gate and a stacked layer on a substrate, wherein the stacked layer comprises an isolation layer, a control gate and a protective layer which are sequentially stacked, a side wall is formed on the side wall of the stacked layer, one side of the stacked layer is an erasing gate region, the other side of the stacked layer is a word line region, the floating gate on one side of the erasing gate region extends out of the stacked layer and the side wall, an erasing gate is formed on one side of the erasing gate region, a word line is formed on one side of the word line region, then, the protective layer is selectively removed without photoetching, masking and other processes, the protective layer is selectively removed, and then contact plugs are formed on the. The method simplifies the process flow of manufacturing the semiconductor device and reduces the manufacturing cost of the device.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 shows a schematic flow diagram of a method of manufacturing a semiconductor device according to an embodiment of the invention;

fig. 2-17 are schematic diagrams illustrating cross-sectional structures of semiconductor devices formed by a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.

Next, the present invention will be described in detail with reference to the drawings, wherein the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration when describing the embodiments of the present invention, and the drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize the applicability of other processes and/or the use of other materials. In addition, the structure of a first feature described below as "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

As described in the background, as the feature size of integrated circuits is continuously reduced, the fabrication process of semiconductor devices including floating gate type flash memories is complicated and the fabrication cost is high.

Therefore, the application provides a manufacturing method of a semiconductor device, a floating gate and a stack layer are formed on a substrate, the stack layer comprises an isolation layer, a control gate and a protective layer which are sequentially stacked, a side wall is formed on the side wall of the stack layer, one side of the stack layer is an erasing gate region, the other side of the stack layer is a word line region, the floating gate on one side of the erasing gate region extends out of the stack layer and the side wall, an erasing gate is formed on one side of the erasing gate region, a word line is formed on one side of the word line region, the protective layer in the stack layer is selectively removed after the erasing gate and the word line are formed so as to lead out the control gate, the protective layer is selectively removed without processes of photoetching, masking and the like in the process of removing the protective layer, and then contact plugs. The method simplifies the process flow of manufacturing the semiconductor device and reduces the manufacturing cost of the device.

In order to better understand the technical solution and technical effects of the present application, the following detailed description of specific embodiments will be made with reference to the flowchart 1 and the accompanying fig. 2-17.

Referring to fig. 1, in step S01, a semiconductor substrate 100 is provided, a floating gate 102 'and a stacked layer 110 thereon are formed on the substrate 100, the stacked layer 110 includes an isolation layer 103, a control gate 104 and a protection layer 105 which are sequentially stacked, sidewalls 111 and 112 are formed on sidewalls of the stacked layer 110, an erase gate region 1102 is formed on one side of the stacked layer 110, a word line region 1101 is formed on the other side of the stacked layer 110, the floating gate 102' on one side of the erase gate region 1102 extends to the outside of the stacked layer 110 and the sidewalls 111 and 112, an erase gate 116 is formed on one side of the erase gate region 1102, and a word line 117 is formed on one side of the word line region 1101, as shown in fig. 14.

In the embodiment of the present application, the semiconductor substrate 100 may be a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or GOI (Germanium On Insulator) or the like. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, SiC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also be other epitaxial structures, such as SGOI (silicon germanium on insulator) or the like. The semiconductor substrate 100 may have been formed with isolation regions (not shown) that may comprise silicon dioxide or other materials that may separate the active regions of the devices. In the present embodiment, the substrate 100 is a silicon substrate.

In this embodiment, the floating gate 102' and the stack layer 110 thereon can be formed by the following method, specifically, in step S101, the floating gate layer 102, the isolation layer 103, the control gate 104 and the protection layer 105 are sequentially deposited on the substrate 100, as shown in fig. 2.

In this embodiment, a floating gate layer 102, an isolation layer 103, a control gate 104, and a protection layer 105 are sequentially deposited on a substrate 100, where the floating gate layer 102 may be, for example, a polysilicon layer, a gate dielectric layer 101 is usually formed between the floating gate layer 102 and the substrate, the gate dielectric layer 101 may be, for example, silicon oxide, the isolation layer 103 isolates the floating gate layer 102 from the control gate 104, the isolation layer 103 may be an insulating dielectric material, for example, a stack of ono (oxide nitride oxide), that is, a stack of oxide, nitride, and oxide, the control gate 104 may be, for example, polysilicon, the protection layer 105 is used to protect the control gate 104 from being damaged in a subsequent process, and the protection layer 105 may be a single layer or a stack structure of a dielectric material, for example, a silicon nitride. In one embodiment, the thickness of the passivation layer 105 may be 600-700 angstroms.

In step S102, the isolation layer 103, the control gate 104 and the protection layer 105 are patterned to form a stack layer 110, which is shown in fig. 2-4.

In this embodiment, a first mask layer 106 may be formed on the protection layer 105 by using a photolithography technique, a pattern of the stack layer 110 is formed in the first mask layer 106, as shown in fig. 2, the protection layer 105, the control gate 104 and the isolation layer 103 are sequentially etched under the shielding of the first mask layer 106, for example, a Reactive Ion Etching (RIE) method may be adopted, so that the stack layer 110 is formed, as shown in fig. 3, and then the first mask layer 106 is removed, as shown in fig. 4.

In step S103, sidewalls 111 and 112 are formed on the sidewalls of the stacked layer 110, as shown in fig. 5.

In the embodiment of the present invention, the sidewalls 111 and 112 are formed on the sidewalls of the stacked layer 110, and the sidewalls 111 and 112 protect and isolate the stacked layer 110, in the embodiment of the present invention, the sidewalls 111 and 112 may have a stacked structure, and the materials of the stacked structure may be the same or different, for example, the stacked structure may be a silicon oxide layer, a silicon nitride layer, or a stack thereof, specifically, the silicon oxide layer and the silicon nitride layer may be sequentially deposited, and then, the silicon oxide layer and the silicon nitride layer are etched by anisotropic etching, so that the sidewalls 111 and 112 in which the silicon oxide layer and the silicon nitride layer are stacked are formed on the sidewalls of the stacked layer 110.

In this embodiment, the spacers 111 and 112 formed by stacking the silicon oxide layer and the silicon nitride layer are formed on the sidewalls of the stacked layers 111 and 112, and specifically, the silicon oxide layer may be deposited first, the silicon oxide layer is subjected to a sidewall process to form a silicon oxide layer sidewall 111, for example, the silicon oxide layer may be subjected to anisotropic etching to form a silicon oxide layer on the sidewall of the stack layer 110, and then a silicon nitride layer is deposited, the silicon nitride layer is subjected to a sidewall process to form silicon nitride layer sidewalls 112, e.g., the silicon nitride layer may be anisotropically etched, therefore, a silicon oxide layer and a silicon nitride layer which are sequentially stacked are formed on the side wall of the stack layer 110, the silicon oxide layer and the silicon nitride layer have high etching selectivity, and the silicon oxide layer can protect the stack layer 110 in the process of etching and removing the silicon nitride on the top of the stack layer and the floating gate layer 102 to form the silicon nitride layer side wall 112.

In this embodiment, for convenience of description, the sidewalls on the sidewalls of the stacked layer 110 are referred to as a first sidewall 111 and a second sidewall 112, the first sidewall 111 is a sidewall next to the stacked layer 110, the second sidewall 112 is a sidewall next to the first sidewall 111, and the material of the second sidewall 112 formed on the sidewalls of the stacked layer 110 may be the same as the material of the protection layer 105, for example, the second sidewall 112 and the protection layer 105 are both silicon nitride, the first sidewall 111 may be silicon oxide, when the second sidewall 112 is formed on the first sidewall 111, during the process of removing the second sidewall 112 on the top of the gate stacked layer 110 and the first sidewall 111 by etching, a part of the silicon nitride protection layer 105 in the stacked layer 110 may be simultaneously removed by etching, so as to consume a part of the thickness of the protection layer 105, and the thickness of the consumed protection layer 105 is related to the deposition thickness of the second sidewall 112, as shown in fig. 6.

In step S104, a sacrificial layer 113 is formed on the sidewalls of the sidewalls 111 and 112 on one side of the stacked layer 110, as shown in fig. 7.

In this embodiment, the sacrificial layer 113 is deposited on the sidewalls of the sidewalls 111 and 112 of the stacked layer 110, and then anisotropic etching is used to perform a sidewall process on the sacrificial layer 113 and remove the stacked layer 110, the floating gate layer 102 and the sacrificial layer 113 on the top of the sidewalls 111 and 112, so that the sacrificial layer 113 is formed only on the sidewall 112 of one side of the stacked layer 110, and the sacrificial layer 113 may be silicon oxide. In a specific embodiment, the thickness of the sacrificial layer 113 may be 300-350 angstroms.

In step S105, the stacked layer 110 and the sacrificial layer 113 are used as a mask to perform patterning of the floating gate layer 102 to form a floating gate 102', where one side of the sacrificial layer 113 is an erase gate region 1102 and the other side is a word line region 1101, as shown in fig. 8.

In the embodiment of the present application, the stacked layer 110 and the sacrificial layer 113 are used as a mask, and no additional mask and lithography process is needed, and the floating gate layer 102 is patterned in a self-aligned manner, for example, an RIE etching method may be used to form the floating gate 102 ', where one side of the sacrificial layer 113 is the erase gate region 1102 and the other side is the word line region 1101, the floating gate 102 ' of the word line region 1101 is substantially flush with the sidewall of the word line region, the floating gate 102 ' of the erase gate region 1102 is substantially flush with the sidewall of the erase gate region 1102, and during the process of etching the floating gate layer 102, the gate dielectric layer 101 may be partially or completely etched.

In step S106, the sacrifice layer 113 is removed, as shown with reference to fig. 9.

After the floating gate 102 'is formed, the sacrificial layer 113 on one side of the erase gate region 1102 is removed, so that the floating gate 102' on one side of the erase gate region 1102 extends to the outside of the stacked layer 110 and the sidewalls 111 and 112, and the sacrificial layer 113 may be removed in various ways.

In this embodiment, a tunnel oxide layer 114 may be formed on the exposed surface of the floating gate 102', and then an erase gate 116 in contact with the tunnel oxide layer 114 is formed on the erase gate 1102, and a word line 117 in contact with the tunnel oxide layer 114 is formed in the word line region 1101, as shown in fig. 13.

In this embodiment, the tunnel oxide material on the surface of the substrate 100 in the word line region 1101 may be removed after depositing the tunnel oxide material. Specifically, a tunneling oxide material may be deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD) or Low Pressure Chemical Vapor Deposition (LPCVD), as shown in fig. 10, and then a mask layer 115 is covered on the tunneling oxide layer 114 of the erase gate region 1102, where the mask layer 115 may be a photoresist, as shown in fig. 11, after the mask layer 115 is formed, the tunneling oxide material on the substrate 100 of the word line region 1101 is removed by shielding the mask layer 115, and at this time, the tunneling oxide layer 114 covers the exposed surface of the floating gate 102 ' on the erase gate region 1102 side, that is, the upper surface and the sidewalls of the portion of the floating gate 102 ' protruding from the stacked layer 110 and the substrate 100 of the erase gate region 1102, and also covers the sidewalls of the stacked layer 110 and the sidewalls of the floating gate 102 ' on the word line region 1101 side, as shown in fig. 12. In a specific embodiment, the tunnel oxide layer 114 may be silicon oxide, and a hydrofluoric acid etching may be used to remove the tunnel oxide material on the surface of the substrate 100 in the word line region 1101.

Then, referring to fig. 13, an erase gate 116 is formed in an erase gate region 1102, and a word line 117 is formed in a word line region 1101. The erase gate 116 of the erase gate region 1102 and the word line 117 of the word line region 1101 may be formed simultaneously by depositing polysilicon, followed by planarization and etching back, and then the tunnel oxide layer 114 on top of the stack layer 110 may be removed by dry etching to expose the protection layer 105 in the stack layer 110, as shown in fig. 14.

In step S02, the protective layer 105 is selectively removed.

Thus, the device structure is formed, in the whole forming process, the protective layer 105 is consumed and thinned, and the consumption includes consumption caused by removing the structure made of the same material as the protective layer 105 at the same time, for example, when the second sidewall 112 is formed, a sidewall process is performed on the deposited second sidewall material, in the sidewall process, in the process of removing the second sidewall 112 deposited on the top of the stack layer 110 by etching, part of the protective layer 105 in the stack layer 110 is simultaneously removed by etching, and also loss of the protective layer 105 is caused when structures made of different materials are removed, so that when the protective layer 105 is removed, only the remaining protective layer 105 needs to be removed by etching, thereby saving time and reducing process complexity.

In a specific application, the initial thickness of the protection layer 105 is reasonably set by estimating the consumption thickness of the protection layer, so that the thickness of the protection layer 105 is kept at about 100-200 angstroms before the protection layer 105 is removed, and the subsequent rapid removal of the remaining protection layer 105 is facilitated. When the protective layer 105 is removed, no additional mask or photoetching process is needed, and the complexity and cost of the process are reduced. In the present embodiment, the thickness of the passivation layer 105 deposited on the substrate may be in the range of 600-700 angstroms, and after the formation process, the thickness of the passivation layer 105 may be in the range of 100-200 angstroms.

In the embodiment of the present application, the wet etching may be used to remove the protection layer 105, the wet etching selectively removes the protection layer 105 in the stack layer 110 to expose the control gate 104, so as to facilitate the subsequent process of leading out the control gate, in the process of selectively removing the protection layer 105 by wet etching, only the protection layer 105 is selectively etched to remove, and no loss is caused to the stack layer 110, for example, an acidic solution that only reacts with the protection layer 105 may be selected, and the acidic solution only reacts with the material of the protection layer 105, so that the control gate 104 is protected from corrosion loss while the protection layer 105 is removed, the protection layer 105 is removed by wet etching, no additional mask or lithography process is needed, and the complexity and cost of the process are reduced.

In this embodiment, the erase gate 116, the word line 117 and the control gate 104 may be polysilicon, the protection layer 105 may be silicon nitride, the first sidewall 111 of the stack layer 110 may be silicon oxide, when the silicon nitride protection layer 105 is removed by wet etching, a solution adopted by the wet etching may be phosphoric acid, the phosphoric acid reacts with the silicon nitride, thereby selectively etching away the protective layer 105, leaking out of the control gate 104, and not etching the erase gate 116, the word line 117, and the control gate 104, as shown in figure 15, after the protective layer 105 is selectively removed by wet etching, the first sidewall 111 and the tunnel oxide layer 114 are not removed during the wet etching, thereby extending above the control gate 104 in the stack 110, removing the first sidewall 111 and the portion of the tunnel oxide layer 114 extending above the control gate 104 in the stack 110 by chemical mechanical polishing, so that the first sidewall spacers 111 and the tunnel oxide layer 114 are substantially flush with the control gate 104.

In another embodiment, a dry etching process may also be used to selectively remove the protection layer 105 in the stack layer 110 to expose the control gate 104, so as to facilitate a subsequent extraction process of the control gate 104. In the process of dry etching to selectively remove the protective layer 105, an appropriate process gas is selected to etch only the protective layer 105 without loss of other structures.

In step S03, contact plugs 120 are formed on the erase gates 116, the word lines 117, and the control gates 104, as shown in fig. 17.

In the embodiment of the present invention, a dielectric layer 118 is formed on the erase gate 116, the word line 117 and the control gate 104, the dielectric layer 118 may be a single layer or a multi-layer structure, and may be made of the same material or different materials, for example, the dielectric layer 118 may be a silicon oxide layer, and a chemical vapor deposition process or a plasma enhanced chemical vapor deposition process may be used.

In this embodiment, a dielectric layer 118 is deposited, a photoresist is then coated on the dielectric layer 118, a patterned photoresist layer is formed through exposure, development and other steps, the patterned photoresist layer is used as a mask to etch the dielectric layer 118, for example, reactive ion etching may be adopted, and at this time, the dielectric layer 118 does not penetrate through the control gate layer 104, and then the dielectric layer 118 is continuously etched until the dielectric layer penetrates through the control gate layer 104, the erase gate 116 and the word line 117, so that a contact hole 120' is formed in the dielectric layer 118, and then the patterned photoresist layer is removed, as shown in fig. 16.

The filling of the contact hole 120' is performed to form the contact plug 120. The filling may be performed with a metal material such as copper, and after the filling, a planarization process may be performed to remove the filling material on top of the dielectric layer 118 until the dielectric layer 118 is exposed, thereby forming a contact plug 120 in the contact hole 120', as shown in fig. 17.

The foregoing is only a preferred embodiment of the present invention, and although the present invention has been disclosed in the preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.