阅读说明：本技术 一种动态阈值隧穿场效应双栅器件 (Dynamic threshold tunneling field effect double-gate device ) 是由 何进 任源 李春来 胡国庆 刘京京 潘俊 王小萌 何箫梦 于胜 于 2019-10-28 设计创作，主要内容包括：本发明公开了一种动态阈值隧穿场效应双栅器件。由控制栅电极、独立偏置栅电极、源区、漏区、沟道区和控制栅介质层组成；其中,所述独立偏置栅电极位于所述阈值隧穿场效应双栅器件底部的独立偏置栅介质层下,由独立偏置栅介质层与沟道区隔离；所述源区和漏区分别位于所述沟道区的两侧,并被控制栅介质将其与控制栅隔离。本发明涉及的器件可独立工作在栅控条件下,为低功耗电路设计提供一种选择方案,而且对阈值电压的调节灵敏度大于传统T-FinFET器件和SOI隧穿器件。此外,其电学性能优于常规T-FinFET器件和SOI隧穿器件。通过独立偏置栅的单独电压调制,可以将栅长缩小到20纳米及以下,并保持比较理想的器件性能。(The invention discloses a dynamic threshold tunneling field effect double-gate device. The gate structure comprises a control gate electrode, an independent bias gate electrode, a source region, a drain region, a channel region and a control gate dielectric layer; the independent bias gate electrode is positioned below an independent bias gate dielectric layer at the bottom of the threshold tunneling field effect double-gate device and is isolated from a channel region by the independent bias gate dielectric layer; the source region and the drain region are respectively positioned at two sides of the channel region and are isolated from the control gate by a control gate medium. The device can independently work under a grid control condition, provides a selection scheme for low-power consumption circuit design, and has higher adjustment sensitivity on threshold voltage than a traditional T-FinFET device and an SOI tunneling device. In addition, the electrical performance of the device is superior to that of a conventional T-FinFET device and an SOI tunneling device. By independent voltage modulation of the independently biased gates, the gate length can be scaled down to 20nm and below, and relatively ideal device performance can be maintained.)

1. A dynamic threshold tunneling field effect double-gate device comprises a control gate electrode, an independent bias gate electrode, a source region, a drain region, a channel region, a control gate dielectric layer and an independent bias gate dielectric layer;

the independent bias gate electrode is positioned below an independent bias gate dielectric layer at the bottom of the threshold tunneling field effect double-gate device, and is isolated from a channel region by a metal substrate and the independent bias gate dielectric layer;

the control gate electrode is isolated from the channel region through a control gate dielectric layer, and the control gate dielectric layer surrounds the channel region from three sides;

the source region and the drain region are respectively positioned at two ends of the channel region and are isolated from the control gate by the control gate dielectric layer.

2. The dynamic threshold tunneling field effect double gate device of claim 1, wherein: the material for forming the channel region is undoped or lightly doped semiconductor material;

the material for forming the source region and the drain region has a doping concentration of 5 × 10¹⁸cm-3～2×10²¹cm-3 semiconductor material, the doping types of which are different, the former is P doping, and the latter is N doping, or vice versa.

3. The dynamic threshold tunneling field effect double gate device of claim 2, wherein: the material for forming the channel region is boron doped with the concentration of 1 multiplied by 10¹⁷cm-3 of silicon material;

the material forming the source region isPhosphorus doping concentration of 1 × 10²⁰cm-3 silicon material, and drain region material with boron doping concentration of 5 × 10¹⁸cm-3 silicon material.

4. The dynamic threshold tunneling field-effect double-gate device according to any one of claims 1-3, wherein:

the thickness of the independent bias gate electrode is 5-20 nanometers;

the thickness of the independent bias gate dielectric layer is 1.2-20 nanometers;

the thickness of the control gate electrode is 5-20 nanometers;

the thickness of the control gate dielectric layer is 1.2-2 nanometers;

the width of the channel region is 3-10 nanometers, and the height of the channel region is 3-50 nanometers.

Technical Field

The invention relates to the field of semiconductor integrated circuit devices, in particular to a dynamic threshold tunneling field effect double-gate device.

Background

With the continuous reduction of the size of an integrated circuit device according to moore's law, the metal oxide semiconductor field effect device under the traditional planar bulk silicon process suffers from development bottlenecks such as short channel effect and gate leakage current, and the like, and new structure devices such as a tunneling device, a collision ionization device, a negative capacitance device and the like continuously emerge at a 10 nanometer technology node, wherein the conventional tunneling field effect double-gate device is also called as: T-FinFETs, which are of great interest because of their excellent sub-threshold characteristics and very low leakage current that break the sub-threshold limit of conventional FinFETs, are considered to have potential applications in 10-5 nanometer integrated circuits.

The threshold voltage of the device can be changed by substrate bias of a bulk silicon device and back gate bias of a double-gate device, and the independent gate bias operation can control the threshold voltage by applying a bias signal, so that the method has important application in the field of power consumption management such as a low-power-consumption memory circuit. In the T-FinFET, an independent bias electrode is introduced to adjust the independent volume potential, so that parameters such as the threshold voltage of the T-FinFET can be adjusted, various electrical characteristics of the device are improved, and various choices and optimizations are provided for application, namely a Dynamic threshold tunneling field effect double-gate device (DT T-FinFET). The scheme is suitable for SOI type T-FinFET, and a bias electrode can be formed under the bottom oxide layer substrate.

Disclosure of Invention

The invention aims to provide a dynamic threshold tunneling field effect double-gate device which consists of a control gate electrode, an independent bias gate electrode, a source region, a drain region, a channel region, a control gate dielectric layer and an independent bias gate dielectric layer; the independent bias gate electrode is positioned below an independent bias gate dielectric layer at the bottom of the threshold tunneling field effect double-gate device, and is isolated from a channel region by a metal substrate and the independent bias gate dielectric layer; the control gate electrode is isolated from the channel region through a control gate dielectric layer, and the control gate dielectric layer surrounds the channel region from three sides; the source region and the drain region are respectively positioned at two ends of the channel region and are isolated from the control gate by the control gate dielectric layer.

Preferably, the material constituting the channel region is an undoped or lightly doped semiconductor material;

the material for forming the source region and the drain region has a doping concentration of 5 × 10¹⁸cm-3～2×10²¹cm-3 semiconductor material, the doping types of which are different, the former is P doping, and the latter is N doping, or vice versa.

Preferably, the material for forming the channel region is boron doped with a concentration of 1 × 10¹⁷cm-3 of silicon material; the material for forming the source region is phosphorus with the doping concentration of 1 multiplied by 10²⁰cm-3 silicon material, and drain region material with boron doping concentration of 5 × 10¹⁸cm-3 silicon material.

Preferably, the thickness of the independently biased gate electrode is 5-20 nm; the thickness of the independent bias gate dielectric layer is 1.2-20 nanometers; the thickness of the control gate electrode is 5-20 nanometers; the thickness of the control gate dielectric layer is 1.2-2 nanometers; the width of the channel region is 3-10 nanometers, and the height of the channel region is 3-50 nanometers.

The channel region of the dynamic threshold tunneling field effect double-gate device is made of undoped or lightly doped semiconductor material, for example, boron doping concentration is 1 × 10¹⁷cm^-3Silicon material of (2). The source and drain regions being of heavily doped semiconductor material, e.g. boron doped and phosphorus doped respectively at a concentration of 1 x 10²⁰cm^-3And 5X 10¹⁸cm^-3Silicon material of (2). Materials for control gate electrodes and adjustable work function, or using high-dielectric constant materialsAnd metal gate material, the thickness is also adjustable, generally controlled to be more than 1-2 nanometers. The dielectric material and thickness of the bias dielectric layer can be adjusted, for example, a silicon oxide material is adopted, and the thickness can be kept to be 1 to 20 nanometers. The height and width of the semiconductor material in the channel region can be adjusted according to the length and width of the channel of the device.

Has the advantages that: the invention provides a dynamic threshold tunneling field effect double-gate device, which is provided with two electrically independent gate electrodes: the gate electrode and the control gate electrode are independently biased. Compared with a conventional tunneling field effect double-gate device (T-FinFET), the structural device allows different working voltages to be applied to the independent bias gate electrode and the control gate electrode, so that the device can work under independent bias gate conditions, and convenience is brought to circuit application and power consumption control of the device. When the dynamic threshold tunneling field effect double-gate device (DT T-FinFET) works under the independent bias gate control condition, the doping and size parameters of the device are not changed, and the current-voltage characteristics of the device are changed by changing the bias voltage of the independent bias gate electrode. For example, reducing the bias voltage of the independently biased gate electrode will increase the threshold voltage of the control gate and reduce the drive current of the entire device. This result provides an alternative to low power circuit designs such as memory cell circuit designs. When the independently biased gate-controlled nano dynamic threshold tunneling field effect double-gate device works under the common-gate condition, compared with a conventional tunneling double-gate device (T-FinFET) with the same structure, the on-state current can be effectively improved under the condition of keeping the off-state current similar, so that the current on-off ratio of the device is improved, and the driving capability of the device is enhanced. The invention provides an alternative for nano DT T-FinFET performance optimization, circuit applications, etc., that allows control of the biased gate electrode.

Drawings

Fig. 1 is a schematic cross-sectional view of a dynamic threshold tunneling field effect double gate device according to the present invention.

FIG. 2 shows the influence of a bias gate electrode on the drain current characteristics of a dynamic threshold tunneling field effect dual gate device according to the present invention.

FIG. 3 is a diagram showing the relationship between the threshold voltage and the sub-threshold slope of a dual gate device with a biased gate electrode according to the present invention.

FIG. 4 shows the on-state current, off-state current, and current-to-switch ratio of the dual gate device with dynamic threshold tunneling field effect.

FIG. 5 is a diagram showing the relationship between the maximum transconductance and the drain induced barrier lowering effect of the dynamic threshold tunneling field effect double-gate device under the bias of the electrode.

Fig. 6 is a comparison of drain-to-drain current characteristics of a dynamic threshold tunneling field effect dual gate device of the present invention under common gate operation with a corresponding conventional dual gate tunneling device.

FIG. 7 shows the drift relationship between the threshold voltage and the sub-threshold slope with the channel length under the common-gate operation of the dynamic-threshold tunneling field effect dual-gate device of the present invention.

Fig. 8 shows the on-state current, the off-state current and the current-to-switching ratio of the dynamic threshold tunneling field effect double-gate device according to the present invention under the common-gate operation.

FIG. 9 is a graph showing the relationship between the maximum transconductance and the drain induced barrier lowering effect of a dynamic threshold tunneling field effect dual-gate device of the present invention with the variation of the channel length under the common-gate operation.

In the figure: 1-control gate electrode, 2-source electrode, 3-drain electrode, 4-independent bias gate dielectric layer, 5-control gate dielectric layer and 6-bias gate electrode.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings:

referring to fig. 1, in this embodiment, the bias-gate controlled nano dynamic threshold tunneling field effect dual-gate device is composed of an independent bias gate electrode 6, a control gate electrode 1, a bias gate dielectric layer 4, a control gate dielectric layer 5, a channel region surrounded by the control gate dielectric layer 5, a source electrode 2, and a drain electrode 3. The source electrode area is called a source area, the drain electrode area is called a drain area, the control grid electrode completely surrounds a channel area of the device, and the independent bias grid electrode is led out through the substrate metal part.

In a first embodiment, the two ends of the channel region are a source region and a drain region made of different materials; the channel region is low doped.

In a second embodiment, the two ends of the channel region are a source region and a drain region of the same material; wherein: the source region is a P-type heavily doped silicon material, the drain region is an N-type doped silicon material, and the channel is an N-type lightly doped silicon material.

The device is prepared according to the prior method, and the preparation process comprises the following steps:

a) isolating on the silicon wafer by using a silicon nitride hard mask LOCOS;

b) depositing Si3N4/Poly-Si as a hard mask of the silicon Fin;

c) photoetching and defining silicon Fin strips and etching;

d) forming SiO2 side walls with the thickness of 70nm,

e) implanting arsenic into the source region and the drain region;

f) after removing the side wall, defining the width of the groove by photoetching, namely the gate length of the device;

g) etching the Si3N4 and SiO2 which are formed initially, and then etching silicon to form a silicon Fin body and a groove;

h) after the Si3N4 side wall is formed, continuing etching the silicon to expose the silicon at the bottom of the Fin channel, wherein the purpose of the operation is to facilitate subsequent oxidation;

i) then the bottom of the Fin channel is completely oxidized, so that a bias disposal gate dielectric layer structure is formed;

j) after Si3N4 is removed, 20nm sacrificial oxidation is carried out to improve the damage of an etched interface;

k) then growing 4nm gate oxide, and photoetching to form a polysilicon gate;

l) completing the preparation of a contact hole and a metal electrode by a standard CMOS process;

m) making the nano tunneling field effect double-gate device controlled by the bias gate.

The present invention will be further illustrated with reference to the following specific examples, but the present invention is not limited to the following examples.