阅读说明：本技术 一种基于fpga的跨时钟域深度自行配置fifo系统 (Cross-clock-domain depth self-configuration FIFO system based on FPGA ) 是由 张润曦 周洲 石春琦 刘元 李延中 翁冰 于 2019-09-16 设计创作，主要内容包括：本发明公开了一种基于FPGA的跨时钟域深度自行配置FIFO系统,提供了一种基于FPGA的能够综合的异步FIFO,FIFO的深度位宽能够自行配置,不需要通过增加一位的方式来判别FIFO的空满状态,也不需要再将已经转换好的格雷码地址再回复到之前的二进制地址码,直接通过二进制地址转换成的格雷码地址进行比较,相比传统异步FIFO而言,有效减少了芯片面积,提高了数据传输速率。(The invention discloses a cross-clock domain depth self-configuration FIFO system based on an FPGA, and provides an asynchronous FIFO which is based on the FPGA and can be synthesized, wherein the depth bit width of the FIFO can be self-configured, the empty and full state of the FIFO is not required to be judged by adding one bit, the converted Gray code address is not required to be returned to the previous binary address code, and the Gray code address converted by the binary address is directly compared.)

1. A cross-clock domain depth self-configuration FIFO system based on FPGA is characterized in that the system comprises a dual-port RAM memory module, a write address module, a full mark logic judgment module, a synchronous to write clock domain module, a read address module, an empty mark logic judgment module and a synchronous to read clock domain module; wherein:

the write address module and the full mark logic judgment module work in a write clock domain; the address reading module and the empty mark logic judgment module work in a reading clock domain;

the write address module has three input ports: a write clock port wclk, a write reset port wrst and a write enable port wr _ en; two output ports: a write address port waddr and a Gray code write address port wptr; the write address port waddr is connected with a write address input end of the dual-port RAM memory module, and the Gray code write address port wptr is connected with an input port of the full mark logic judgment module;

the full flag logic judgment module has four input ports: the write clock port wclk, the write reset port wrst, the gray code write address port wptr and the read address synchronous write clock domain port wq2_ rptr, the read address synchronous write clock domain port wq2_ rptr is connected with the synchronous write clock module, and the output port is provided with: full flag port wfull; the full mark port wfull is connected with the dual-port RAM memory module;

the read address module has three input ports: the read clock port rclk, the read reset port rrst and the read enable port rd _ en are provided by external input; two output ports: reading address port raddr and Gray code reading address port rptr; the read address port raddr is connected with a read address input end of the dual-port RAM memory module, and the Gray code read address port rptr is connected with an input port of the empty mark logic judgment module;

the empty flag logic judgment module has four input ports: a read clock port rclk, a read reset port rrst, a Gray code read address port rptr and a write address synchronous read clock domain port rq2_ wptr; the write address synchronous read clock domain port rq2_ wptr is connected with the synchronous read clock domain module; one output port: an empty flag port repty, the empty flag port repty connected to the dual port RAM memory module;

the module synchronized to the writing clock domain works in the writing clock domain, and the input of the module is connected with a Gray code reading address port rptr;

the synchronous to read clock domain module works in a read clock domain, and the input of the synchronous to read clock domain module is connected with a Gray code write address port wptr;

the dual-port RAM memory module is provided with eleven input ports which are respectively a write data port wdata, a write clock port wclk, a write reset port wrst, a write enable port wr _ en, a write address port waddr, a full mark port wfull, a read clock port rclk, a read reset port rrst, a read enable port rd _ en, a read address port raddr and an empty mark port rempty, and one output port: the read data port rdata.

2. The cross-clock-domain depth self-configurable FIFO system of claim 1, wherein the read data port rdata of the dual-port RAM memory module reads data only in the read clock domain; the write data port wdata only writes data in a write clock domain; when the empty mark port is 1, data cannot be read; when the full flag port is 1, data cannot be written; the read-write data bit width of the dual-port RAM memory module is set automatically, and the read-write address is configured automatically.

3. The cross-clock-domain depth self-configurable FIFO system of claim 1, wherein the synchronization to the write clock domain module synchronizes a gray code read address port wptr, which has been synchronized once under a read clock in the read address module, to wq2_ rptr by a two-stage D flip-flop under control of the write clock.

4. The cross-clock-domain depth self-configurable FIFO system of claim 1, wherein the synchronous to read clock domain module synchronizes the gray code write address port rptr, which has been synchronized once under the write clock in the write address module, to rq2_ wptr by a two-stage D flip-flop under control of the read clock.

5. The cross-clock-domain depth self-configurable FIFO system of claim 2, wherein the write data can only be written when write enable port wr en is valid and full flag port wfull is not 1.

6. The cross-clock-domain depth self-configurable FIFO system of claim 2, wherein the read data can only be read when the read enable port rd _ en is active and the empty flag port repeat is not 1.

7. The cross-clock-domain depth self-configurable FIFO system of claim 1, wherein the full flag logic determines that the highest bits of the data of the Gray code write address port wptr and the data of the synchronous write clock domain port wq2_ rptr are different and the second highest bits are different.

8. The cross-clock-domain depth self-configurable FIFO system of claim 1, wherein the empty flag logic determination module determines that the gray code read address port rptr data and the synchronous read clock domain port rq2_ wptr data are the same.

Technical Field

The invention belongs to the field of digital integrated circuit design, and mainly relates to a cross-clock domain data transmission interaction problem.

Background

In a chip system, high-speed real-time data acquisition and high-performance data transmission in different clock domains are not separated from an asynchronous FI first-in first-out queue (FIFO) to serve as a cache. With the ever-expanding scale of integrated circuits, a system often requires a plurality of different clock controls in the integrated circuit chips of today. But communication and interaction between data is hindered due to the cross-clock domain transmission of data. Meanwhile, the data transmission across clock domains is easy to cause a metastable state phenomenon. Asynchronous FIFO has unique advantage in solving the problem of cross-clock domain transmission of data, can store continuous data in sequence and read the data according to the principle of first-in first-out. Vivado software of Xilinx corporation is provided with an IP core of an asynchronous FIFO, but the IP core of the Vivado software is fixed, application scenes are limited, universality is poor, and particularly the design requirement of data transmission across clock domains under complex conditions can not be met. In the existing technologies, for the design of a cache circuit for transmitting data across clock domains, the circuit structure is complex, the design logic is complex, the universality is poor, and the universality is not good. FPGAs, field programmable gate arrays, are emerging as a semi-custom circuit in the field of application specific integrated circuits. Due to the strong parallel capability of the FPGA, the FPGA is widely applied to the fields of network interface, image processing, video signal processing, digital communication, and the like in recent years. The method is an effective way to construct a comprehensive asynchronous FIFO system by utilizing the internal resources of the FPGA.

Disclosure of Invention

The invention aims to solve the problem of caching data transmission under different clock domains, and provides an integrated FIFO with configurable cross-clock domain depth based on an FPGA. The invention occupies less FPGA internal resources, has simple circuit logic and strong universality, can automatically configure the depth and bit width of data and has high data transmission rate.

The specific technical scheme for realizing the purpose of the invention is as follows:

a cross-clock domain depth self-configuration FIFO system based on FPGA is characterized in that the system comprises a dual-port RAM memory module, a write address module, a full mark logic judgment module, a synchronous to write clock domain module, a read address module, an empty mark logic judgment module and a synchronous to read clock domain module; wherein:

the write address module and the full mark logic judgment module work in a write clock domain; the address reading module and the empty mark logic judgment module work in a reading clock domain;

the write address module has three input ports: a write clock port wclk, a write reset port wrst and a write enable port wr _ en; two output ports: a write address port waddr and a Gray code write address port wptr; the write address port waddr is connected with a write address input end of the dual-port RAM memory module, and the Gray code write address port wptr is connected with an input port of the full mark logic judgment module;

the full flag logic judgment module has four input ports: the write clock port wclk, the write reset port wrst, the gray code write address port wptr and the read address synchronous write clock domain port wq2_ rptr, the read address synchronous write clock domain port wq2_ rptr is connected with the synchronous write clock module, and the output port is provided with: full flag port wfull; the full mark port wfull is connected with the dual-port RAM memory module;

the read address module has three input ports: the read clock port rclk, the read reset port rrst and the read enable port rd _ en are provided by external input; two output ports: reading address port raddr and Gray code reading address port rptr; the read address port raddr is connected with a read address input end of the dual-port RAM memory module, and the Gray code read address port rptr is connected with an input port of the empty mark logic judgment module;

the empty flag logic judgment module has four input ports: a read clock port rclk, a read reset port rrst, a Gray code read address port rptr and a write address synchronous read clock domain port rq2_ wptr; the write address synchronous read clock domain port rq2_ wptr is connected with the synchronous read clock domain module; one output port: an empty flag port repty, the empty flag port repty connected to the dual port RAM memory module;

the module synchronized to the writing clock domain works in the writing clock domain, and the input of the module is connected with a Gray code reading address port rptr;

the synchronous to read clock domain module works in a read clock domain, and the input of the synchronous to read clock domain module is connected with a Gray code write address port wptr;

the dual-port RAM memory module is provided with eleven input ports which are respectively a write data port wdata, a write clock port wclk, a write reset port wrst, a write enable port wr _ en, a write address port waddr, a full mark port wfull, a read clock port rclk, a read reset port rrst, a read enable port rd _ en, a read address port raddr and an empty mark port rempty, and one output port: the read data port rdata.

The read data port rdata of the dual-port RAM memory module only reads data in a read clock domain; the write data port wdata only writes data in a write clock domain; when the empty mark port is 1, data cannot be read; when the full flag port is 1, data cannot be written; the read-write data bit width of the dual-port RAM memory module is set automatically, and the read-write address is configured automatically.

The synchronizing to write clock domain module synchronizes the gray code read address port wptr, which has been synchronized once under the read clock in the read address module, to wq2_ rptr through two stages of D flip-flops under the control of the write clock. The purpose is to further reduce the probability of data metastability transmission under cross-clock domain transmission.

And under the control of the read clock, the synchronous to read clock domain module synchronizes the Gray code write address port rptr which is synchronized once under the write clock in the write address module into rq2_ wptr through a two-stage D flip-flop. The purpose is to further reduce the probability of data metastability transmission under cross-clock domain transmission.

The write data can only be written when the write enable port wr _ en is active and the full flag port wfull is not 1.

The read data can be read only when the read enable port rd _ en is active and the null flag port repty is not 1.

The full mark logic judgment module judges that the highest bits of the gray code write address port wptr data and the synchronous write clock domain port wq2_ rptr data are different, and the second highest bits are also different.

And the empty mark logic judgment module judges that the data of the Gray code read address port rptr is the same as the data of the synchronous read clock domain port rq2_ wptr.

The invention has the advantages that:

1. the circuit of the invention has simple structure and strong universality.

2. The integrated circuit of the invention occupies less resources and has small area.

3. The invention directly compares the gray code addresses, has simple judgment logic and leads the data transmission rate to be faster.

4. The data bit width and the storage depth of the invention can be set by self, and the invention is flexible and convenient.

Drawings

FIG. 1 is a block diagram of the system of the present invention;

FIG. 2 is a simulation of the present invention.

Detailed Description

The invention is described in detail below with reference to the figures and examples.