阅读说明：本技术 一种基于随机计算的无误差加法器 (Error-free adder based on random calculation ) 是由 卢有亮 王浩 张恒源 赵成 卢鹏宇 陈瑜 滕云龙 元硕成 于 2019-09-25 设计创作，主要内容包括：本发明公开一种基于随机计算的无误差加法器,应用于数字电路优化设计领域,针对现有的随机加法器存在的误差问题,本发明的无误差加法器包括：输入转换器、随机加法器以及输出转换器；所述输入转换器用于将输入数据转换成随机序列,所述输入随机加法器的随机序列中“0”和“1”可以为任意位置,所述随机加法器用于完成随机序列的加法运算,随机加法器的输出包括：加法结果与误差；所述输出转换器用于将加法结果通过累加转换回传统二进制数值域,并对误差根据其级联级数进行移位运算和累加进行补偿得到无误差的最终结果,本发明的无误差加法器具有很好的普适性。(The invention discloses an error-free adder based on random calculation, which is applied to the field of digital circuit optimization design and aims at solving the error problem of the existing random adder, and the error-free adder comprises the following components: an input converter, a random adder, and an output converter; the input converter is used for converting input data into a random sequence, the random sequence of the input random adder can have any position of '0' and '1', the random adder is used for completing addition operation of the random sequence, and the output of the random adder comprises: adding the result and the error; the output converter is used for converting the addition result to the traditional binary numerical value domain through accumulation, and carrying out shift operation and accumulation on the error according to the cascade stage number of the error to compensate and obtain the final error-free result.)

1. An error-free adder based on random computation, wherein "0" and "1" in the random sequence of the input random adder can be any position, and the output of the random adder comprises: the addition result and the error.

2. The random computation-based error-free adder according to claim 1, wherein when the first addition result of the two-input random adder is 1, the addition result is 0 and the error is 1; when the addition result is 1 again, the addition result is output as 1, and the error is 0.

3. An error-free adder based on stochastic computing according to claim 2, wherein the stochastic adder is a scaled adder.

4. A random computation based error-free adder according to claim 3, further comprising an output converter, the output converter comprising: the accumulator is used for converting an addition result back to a conventional binary number value and sending the addition result to the compensation unit; the compensation unit adds the error output by the random adder and the effective value output by the accumulator to obtain an error-free result.

5. An error-free adder based on random computation of claim 4, wherein the random adders are cascaded.

6. The random computation-based error-free adder according to claim 5, wherein when the random adders are cascaded, the error-free result is obtained by performing shift addition according to the number of cascaded stages where the final addition result and the error are obtained by the cascaded random adders.

7. A random computation based error-free adder according to any one of claims 4-6, further comprising: an input converter; the input converter includes: the device comprises a normalization module and a random sequence generation module, wherein the normalization module is used for converting input data into a probability domain, and the random sequence generation module converts the probability domain input data output by the normalization module into a probability domain random sequence.

8. An error-free adder based on stochastic computing according to claim 6, wherein the input converter is common to the output converter when the stochastic adders are cascaded.

9. A digital signal processing system comprising at least an error-free adder according to any of claims 1 to 8.

10. A communication system comprising at least an error-free adder according to any of claims 1 to 8.

Technical Field

The invention belongs to the field of digital circuit optimization design, and relates to an implementation method of an error-free random computing unit.

Background

With the development of information technology, the complexity of various required signal processing algorithms is rapidly increased, and the traditional semiconductor process is close to the physical limit, and Moir thinks that Moire's law is dark and discolored by 2020. The optimization of integrated circuits mainly comes from the innovation of their design architecture, so it is necessary to research new algorithms to optimize the design of integrated circuits.

The main idea of scholars to apply random computation to neural networks and digital signal processing is to convert the conventional binary representation into a string of random sequences, in which the probability value is represented by the ratio of "1" to the total length of the sequence. The calculation is completed by a corresponding random calculation unit. The method has the advantages that basic logic gate circuits can be greatly reduced, so that a critical path is shorter, and the overall power consumption and the resource occupation are greatly reduced. However, the conventional random adder used in this method is generally implemented by an or gate or a multiplexer, and the or gate will take "1" when "0" and "1" are added; the multiplexer requires that the randomness of the selection sequence involved in the computation is high enough that otherwise uncontrollable computation errors occur, which is difficult to implement. These computational units are less accurate and cannot meet high-accuracy scenarios.

Disclosure of Invention

In order to solve the technical problem, the invention provides an error-free adder based on random calculation, and the positions of '0' and '1' in an input random sequence can be arbitrary and can be used under a high-precision condition.

The technical scheme adopted by the invention is as follows: an error-free adder based on random computation, comprising: an input converter, a random adder, and an output converter; the input converter is used for converting input data into a random sequence, the random adder is used for completing addition operation of the random sequence, and the output converter is used for converting the random sequence after passing through the random adder into a traditional binary numerical value;

the "0" and "1" in the random sequence input to the random adder may be any positions, and the output of the random adder includes: the addition result and the error.

The input converter includes: the device comprises a normalization module and a random sequence generation module, wherein the normalization module is used for converting input data into a probability domain, and the random sequence generation module converts the probability domain input data output by the normalization module into a probability domain random sequence.

When the addition result of the two input random adders is 1 for the first time, the addition result is output to be 0, and the error is 1; when the addition result is 1 again, the addition result is output as 1, and the error is 0.

The random adder is a scaling adder.

The output converter includes: the accumulator is used for converting an addition result back to a conventional binary number value and sending the addition result to the compensation unit; the compensation unit adds the error output by the random adder and the effective value output by the accumulator to obtain an error-free result.

The random adders may be cascaded.

When the random adders are cascaded, the final addition result and the cascade number of the cascade where the errors are located are obtained according to the cascaded random adders, and the error-free result is obtained by shifting and adding.

A digital signal processing system at least comprises the error-free adder.

A communication system comprises at least the error-free adder.

The invention has the beneficial effects that: the error-free adder is suitable for random computation and structurally comprises an input converter, a random adder and an output converter, wherein the random adder is a scaling adder and can be cascaded; the random adder and the output converter are sequentially connected in a circuit mode, input data are converted into a random sequence in the input converter, the random sequence serves as the input of the random adder, the positions of '0' and '1' in the input sequence of the random adder can be random, the output of the random adder is sent into the output converter, the conversion from the random sequence to a traditional binary numerical value domain is completed, and error compensation is carried out on the result, so that the random adder is free of error output; the error-free adder of the invention has the following advantages:

1. compared with the traditional adder, the adder uses fewer basic gate circuits, reduces resource consumption and shortens a critical path;

2, compared with the traditional random adder, the precision is higher;

3. the method is easy to realize in FPGA;

4. compared with the traditional binary adder, the input/output converter can be shared in large-scale cascade addition, so that the resources and the power consumption can be further saved;

5. the error-free adder can also be applied to a digital signal processing system and a communication system, and can reduce resources and power consumption.

Drawings

FIG. 1 is a diagram of a conventional random adder;

wherein, fig. 1(a) is a conventional random adder implemented by an or gate; FIG. 1(b) is a conventional random adder implemented by a multiplexer;

FIG. 2 is a diagram of an error-free adder according to the present invention;

FIG. 3 is a diagram of an input converter architecture;

FIG. 4 is a diagram of an error-free adder cascade;

FIG. 5 is a diagram of an output converter architecture;

fig. 6 is a simulation result diagram.

Detailed Description

The core of the invention is that the adder designed based on the random computing method is realized without error and can be infinitely cascaded, the positions of '0' and '1' in the input sequence can be arbitrary, and the FPGA realization mode of the adder is provided.

The invention is described in detail below with reference to the accompanying drawings:

the function of the two-input adder is z ═ x + y, where x and y represent the input data and z is the adder output. The input data is k bits wide. The conventional random adder is implemented by an or gate as shown in fig. 1(a) or a multi-way gate as shown in fig. 1(b), wherein the random adder implemented by the or gate requires that one path of two paths of input random sequences is in centralized distribution, and the other path is in uniform distribution; while the random adder implemented by the multiplexer contains uncertainty. Errors are generated in the calculation process of the two traditional random adders. In order to solve the error problem of the conventional adder, the present invention provides an error-free adder based on random computation as shown in fig. 2.

Fig. 2 is a diagram showing a structure of a random adder in the present embodiment. The structure comprises an input converter for converting input data into a random sequence in a probability domain, wherein the input converter sends the generated random sequence into a random adder to complete addition operation in the random domain, the output of the random adder is sent into an output converter to complete conversion from the random sequence to a traditional binary number and carry out error compensation on an output result to obtain a final error-free output result z.

The implementation of the input converter, the random adder and the output converter is described in detail below:

as shown in fig. 3, the input converter functions to convert input data into a probability domain, and includes: a normalization module and a random sequence generation module, wherein the normalization module is used for performing unified standard normalization on the input waveform data x and y to [0,1 ]]In between, a transition from the binary value domain to the probability domain is effected. Conversion formula is p_x＝(x+2^k-1)/2^k，p_y＝(y+2^k-1)/2^k(ii) a And the random sequence generation module converts the probability domain input data output by the normalization module into a probability domain random sequence.

The random adder proposed by the present invention has no requirement for the positions of "0" and "1" in the input sequence, and for convenience of explaining the operating principle of the input converter, the present invention converts the input data into a centrally distributed sequence, based on

Wherein L is 2^kFor example, an input data converter with 3 bits of one bit width is taken as an example, the unsigned number x is 4 to 3' b100, and the length of the converted random sequence is L is 2³Corresponding probability value p 8_xWhen the sequence is generated in the concentrated sequence generation method, X is obtained as 4/8^L＝11110000。

The function of the random adder is to implement random sequence addition operation through a series of logic operations. Assuming that the conventional binary lower-band scaling two-input adder equation is expressed as z ═ 0.5(x + y), the calculation equation based on the random sequence isThen the calculation formula at any one time is 0.5 (X)^L(t)+Y^L(t))＝Z^L(t) when X^L(t)+Y^LWhen (t) is 0 or 2, the formula is calculated accurately. But when X is^L(t)+Y^LWhen (t) is 1, Z^LIn the conventional random adder, the value (t) is 0.5, and the value is randomly set to 0 or 1, thereby generating a calculation error. The invention adopts the mode that when X appears for the first time^L(t)+Y^LWhen t is 1, output Z^L(t) 0, outputting the error as E (t) 1, when X appears again^L(t)+Y^LWhen t is 1, output Z^LWhere (t) is 1, the error is e (t) is 0. When X is present^L(t)+Y^LWhen (t) is 0 or 2, Z^L(t) 0 or Z^L(t) is 1, and the errors e (t) are all 0. After all digits of the two random sequences are completely calculated, Z is output^L(t) while outputting the calculated final error e (l). According to the process, the output logic expression of the random adder at any moment can be obtained as Z^L(t)＝X^L(t)&Y^L(t)|Y^L(t)&E(t)|X^L(t)&E (t), the error logic expression is

The method can be realized by using a hardware description language in the FPGA and paying attention to the timing problem. This calculation is illustrated below, assuming that the input data x is 4 and y is 3, and the conversion is made toInput sequence X^L＝11110000,Y^LThe output is Z as known from the above method, 11100000^L1110000, E1, and sending the output result to the output converter.

The implementation of the cascade of the random adder is shown in fig. 4, when the input is multiple inputs, the cascade is implemented layer by combining the addends participating in the operation in pairs, the input and output converters share the same, the calculation output shifts the final result and each layer of error according to the number of stages, and then the final result and each layer of error are added to obtain the error-free cascade calculation result output.

As shown in fig. 5, the output converter is used to convert the computed random sequence back to the conventional binary value field and perform error compensation output; the method comprises the following steps: an accumulator and a compensation unit. The accumulator being arranged to output Z to the random adder^LAnd accumulating, namely, adopting a scaling adder, so that the compensator needs to carry out left shift operation on the accumulated value and add an output error value E to obtain error-free output. As aforementioned output Z^L1110000, E is 1, the output after accumulator is 3' b011 of traditional binary value domain, in compensator, two inputs have scaling adder to shift left one bit to get 3' b110, and add the output error value E to 1 to get the final output result 3' b111 to 7, which is the same as the original binary value domain a + b 4+3 to 7, and the output is error-free.

Fig. 6 is a diagram showing simulation results of an FPGA-implemented random computation-based error-free adder and a conventional binary adder, where x and y are two 16-bit input data, each computation cycle is changed once, z is a computation result of the random adder of the present invention, E is a computation result of an error bit in a computation process, and z _ true is a computation result implemented by the conventional binary adder, and the computation results have a delay of one computation cycle, which shows that the computation results are completely identical and the designed adder has no error. Compared with the traditional binary adder, the error-free adder based on random calculation provided by the invention can share the input/output converter in large-scale cascade connection, and the resource and the power consumption can be greatly reduced.

It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.