阅读说明：本技术 一种数字孪生系统复杂任务布局紧耦合运行方法及系统 (Digital twin system complex task layout tight coupling operation method and system ) 是由 邹孝付 陶飞 刘蔚然 于 2019-09-25 设计创作，主要内容包括：本发明公开了一种数字孪生系统复杂任务布局紧耦合运行方法及系统,该方法适用于Xilinx公司Virtex-5系列FPGA芯片,包括设计数字孪生系统复杂任务布局紧耦合权值定义模块,该模块完成对FPGA的边和FPGA中正在运行区域的边设定不同的紧耦合权值；设计数字孪生系统复杂任务布局紧耦合度计算模块,该模块基于定义的不同紧耦合权值完成紧耦合度计算。本发明能够在一定程度上解决由于前次任务布局的不合理导致后续任务无法被布局在FPGA上运行的问题,提高数字孪生系统复杂任务在FPGA上运行的效率。(The invention discloses a digital twin system complex task layout tight coupling operation method and a system, wherein the method is suitable for Virtex-5 series FPGA chips of Xilinx company, and comprises a module for designing a digital twin system complex task layout tight coupling weight value definition module, and the module is used for setting different tight coupling weight values on the edge of an FPGA and the edge of an area in the FPGA which is in operation; designing a compact coupling degree calculation module for the complex task layout of the digital twin system, wherein the module completes the compact coupling degree calculation based on different defined compact coupling weights. The method can solve the problem that the subsequent tasks cannot be laid out on the FPGA to run due to unreasonable layout of the previous task to a certain extent, and improves the running efficiency of the complex tasks of the digital twin system on the FPGA.)

1. A digital twin system complex task layout tight coupling operation method is characterized by comprising the following steps:

designing a digital twin system complex task layout tight coupling weight defining module, wherein different tight coupling weights are set for the edge of the FPGA and the edge of an operating area in the FPGA, the tight coupling weight defining module comprises the steps of defining the tight coupling weight of the edge of the FPGA as c1, defining the tight coupling weight of the edge of the operating area in the FPGA as c2, and c1 is more than c 2;

designing a compact coupling degree calculation module of the complex task layout of the digital twin system, and finishing the compact coupling degree calculation based on different defined compact coupling weights, wherein the compact coupling degree calculation module is specifically realized as follows:

① defines the close coupling degree of complex Task layout of digital twin system as C (Task)_i) Wherein i is the number of different tasks;

② degree of tight coupling C (Task)_i) C1 × n + c2 × m, where n denotes the number of times the virtual run area of the ith task coincides with the edge of the FPGA, and m denotes the number of times the virtual run area of the ith task coincides with the edge of the running area in the FPGA;

③ Task_iPerforming multiple random layout in FPGA, andcalculating the resulting plurality of Cs (Task)_i) Selecting C (Task)_i) Maximum layout mode as Task_iThe final operating region of (a).

2. A digital twin system complex task layout close-coupled operation method as claimed in claim 1, wherein: the method is suitable for Virtex-5 series FPGA chips of Xilinx company.

3. A digital twin system complex task layout close-coupled operation system, comprising:

the digital twin system complex task layout tight coupling weight definition module is used for setting different tight coupling weights for the edge of the FPGA and the edge of an operating area in the FPGA, and comprises the steps of defining the tight coupling weight of the edge of the FPGA as c1, defining the tight coupling weight of the edge of the operating area in the FPGA as c2, and defining that c1 is more than c 2;

the calculation module of the tight coupling degree of the complex task layout of the digital twin system completes the calculation of the tight coupling degree based on different defined tight coupling weights, and comprises the following steps:

① defines the close coupling degree of complex Task layout of digital twin system as C (Task)_i) Wherein i is the number of different tasks;

② degree of tight coupling C (Task)_i) C1 × n + c2 × m, where n denotes the number of times the virtual run area of the ith task coincides with the edge of the FPGA, and m denotes the number of times the virtual run area of the ith task coincides with the edge of the running area in the FPGA;

③ Task_iPerforming multiple random layouts in the FPGA, and calculating the resulting multiple Cs (tasks)_i) Selecting C (Task)_i) Maximum layout mode as Task_iThe final operating region of (a).

Technical Field

The invention belongs to the field of electronic engineering and computer science, and particularly relates to a method and a system for tightly coupling and operating complex task layout of a digital twin system.

Background

At present, a digital twinning technology based on a virtual-real interaction and fusion technology has been widely researched by domestic and foreign scholars, and the technology comprises equipment health control, process simulation analysis, production line running state monitoring and the like based on digital twinning drive. One of the key enabling technologies in digital twin is the fusion of data and models, including the fusion of data between manufacturing bottom layer heterogeneous devices and production lines, and the fusion of different device models (mainly referring to certain behavior, rules and physical constraint conditions behind a three-dimensional model), which is a very complex system including the fusion of different protocols and different interface data, and the model fusion of device mechanical properties, thermal properties, material properties, process constraints and the like. The data and model fusion in the digital twin system is finally embodied as the cloud of the algorithm, such as the running of the data/model fusion algorithm on a computer, the running of the data/model fusion algorithm on an embedded system, the accelerated running of the data/model algorithm on an FPGA, and the like. The complex data/model fusion algorithm can be decomposed into tasks with a certain incidence relation, the tasks are required to be operated on hardware, taking the FPGA as an example, the tasks are finally operated on a hardware circuit arranged in the FPGA, the hardware resources of the FPGA are limited, and how to enable larger tasks to be operated in a layout mode under the condition of limited resources is worth researching.

The layout operation of the digital twin complex task on the FPGA is prior, and for the FPGA with limited hardware resources, if the previous task is randomly laid out, the subsequent task does not have enough operation space, therefore, the invention discloses a method and a system for tightly coupling and operating the digital twin system complex task layout, the method is suitable for Virtex-5 series FPGA chips of Xilinx company, the operation of the digital twin complex task on the FPGA is guided by defining a tightly coupled weight and calculating the tight coupling degree of the task under different layout modes, the problem that the subsequent task cannot be laid out and operated on the FPGA due to unreasonable layout of the previous task can be solved to a certain extent, and the efficiency of the operation of the digital twin system complex task on the FPGA is improved.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: the method comprises the design of a digital twin system complex task layout tight coupling weight definition module and the design of a digital twin system complex task layout tight coupling calculation module, can solve the problem that a subsequent task cannot be laid out on an FPGA to run due to unreasonable layout of a previous task to a certain extent, and improves the running efficiency of the digital twin system complex task on the FPGA.

The technical problem to be solved by the invention is realized by adopting the following technical scheme:

a digital twin system complex task layout tight coupling operation method comprises the following steps:

designing a digital twin system complex task layout tight coupling weight defining module, wherein different tight coupling weights are set for the edge of the FPGA and the edge of an operating area in the FPGA, the tight coupling weight defining module comprises the steps of defining the tight coupling weight of the edge of the FPGA as c1, defining the tight coupling weight of the edge of the operating area in the FPGA as c2, and c1 is more than c 2;

designing a compact coupling degree calculation module of the complex task layout of the digital twin system, and finishing the compact coupling degree calculation based on different defined compact coupling weights, wherein the compact coupling degree calculation module is specifically realized as follows:

① defines the close coupling degree of complex Task layout of digital twin system as C (Task)_i) Wherein i is the number of different tasks;

② degree of tight coupling C (Task)_i) C1 × n + c2 × m, where n denotes the number of times the virtual run area of the ith task coincides with the edge of the FPGA, and m denotes the number of times the virtual run area of the ith task coincides with the edge of the running area in the FPGA;

③ Task_iPerforming multiple random layouts in the FPGA, and calculating the resulting multiple Cs (tasks)_i) Selecting C (Task)_i) Maximum layout mode as Task_iThe final operating region of (a).

Furthermore, the method is suitable for Virtex-5 series FPGA chips of Xilinx company.

The invention also provides a digital twin system complex task layout tightly-coupled operation system, which comprises:

the digital twin system complex task layout tight coupling weight definition module is used for setting different tight coupling weights for the edge of the FPGA and the edge of an operating area in the FPGA, and comprises the steps of defining the tight coupling weight of the edge of the FPGA as c1, defining the tight coupling weight of the edge of the operating area in the FPGA as c2, and defining that c1 is more than c 2;

the calculation module of the tight coupling degree of the complex task layout of the digital twin system completes the calculation of the tight coupling degree based on different defined tight coupling weights, and comprises the following steps:

① defines the close coupling degree of complex Task layout of digital twin system as C (Task)_i) Wherein i is the number of different tasks;

② degree of tight coupling C (Task)_i) C1 × n + c2 × m, where n denotes the number of times the virtual run area of the ith task coincides with the edge of the FPGA, and m denotes the number of times the virtual run area of the ith task coincides with the edge of the running area in the FPGA;

③ Task_iPerforming multiple random layouts in the FPGA, and calculating the resulting multiple Cs (tasks)_i) Selecting C (Task)_i) Maximum layout mode as Task_iThe final operating region of (a).

Compared with the prior art, the method has the advantages that the running of the digital twin complex task on the FPGA is guided by defining the tight coupling weight and calculating the tight coupling degree of the task in different layout modes, the problem that the subsequent task cannot be laid out and run on the FPGA due to unreasonable layout of the previous task can be solved to a certain extent, and the running efficiency of the digital twin system complex task on the FPGA is improved.

Drawings

FIG. 1 is a block diagram of the present invention;

FIG. 2(a) is an arbitrary layout diagram;

FIG. 2(b) is a layout of the method according to the invention.

Detailed Description

The present invention is described in further detail below with reference to the attached drawings.

The invention relates to a complex task layout tightly-coupled operation method of a digital twin system, which is suitable for Virtex-5 series FPGA chips of Xilinx company. Data and model fusion in the digital twin key enabling technology is a complex system task, and relates to fusion of data between manufacturing bottom layer heterogeneous equipment and production lines, including fusion of different protocols and different interface data, model fusion of equipment mechanical characteristics, thermal characteristics, material characteristics, process constraints and the like. The complex data/model fusion algorithm can be decomposed into tasks with a certain incidence relation, the tasks are required to be operated on hardware, taking the FPGA as an example, the tasks are finally operated on a hardware circuit arranged in the FPGA, the hardware resources of the FPGA are limited, and how to enable larger tasks to be operated in a layout mode under the condition of limited resources is worth researching. The layout operation of the digital twin complex task on the FPGA is prior, and for the FPGA with limited hardware resources, if the previous task is randomly laid out, the subsequent task does not have enough operation space.

The structural block diagram of the invention is shown in fig. 1, and the specific implementation mode is as follows:

(1) fig. 1 shows a module 1 for defining a tight coupling weight of a complex task layout of a digital twin system, which sets different tight coupling weights for an edge of an FPGA and an edge of a running region in the FPGA, where the tight coupling weight of the edge of the FPGA is defined as c1, the tight coupling weight of the edge of the running region in the FPGA is defined as c2, and c1> c 2. The FPGA edge represents the boundary of a Virtex-5 series FPGA chip of the Xilinx company, the edge of an area in the FPGA which is running represents the boundary of the area in the Virtex-5 series FPGA chip of the Xilinx company, and a complex task of a digital twin system runs in the Virtex-5 series FPGA chip of the Xilinx company;

(2) fig. 1 shows a 2-representation digital twin system complex task layout tight coupling weight definition module, which is specifically implemented as follows:

① define digital twin system complex taskThe tight coupling degree of the service layout is C (Task)_i) Wherein i is the number of different tasks;

② degree of tight coupling C (Task)_i) C1 × n + c2 × m, where n denotes the number of times the virtual run area of the ith task coincides with the edge of the FPGA, and m denotes the number of times the virtual run area of the ith task coincides with the edge of the running area in the FPGA;

③ Task_iPerforming multiple random layouts in the FPGA, and calculating the resulting multiple Cs (tasks)_i) Selecting C (Task)_i) Maximum layout mode as Task_iThe final operating region of (a).

Assume three tasks to be laid out and run on the FPGA as shown in table 1 below, and assume that the close-coupled weight c1 on the FPGA side is equal to 2 and the close-coupled weight c2 on the side of the running region in the FPGA is equal to 1.

TABLE 1 tasks to be laid out for operation

As shown in fig. 2 (a): due to Task₁Is the Task that the first layout runs on the FPGA, its C (Task)₁)＝0；C(Task₂) 2 × 6+1 × 2 ═ 14, but when Task₃And Task₄The Task comes because there are not enough rectangular areas for them to run₃And Task₄The operation fails.

As shown in fig. 2 (b): due to Task₁Is the Task that the first layout runs on the FPGA, its C (Task)₁)＝2×6＝12；C(Task₂)＝2×6+1×2＝14，C(Task₃) The final Task can be seen as 2 × 3+1 × 6 ═ 12₄The layout runs successfully.

C (Task) in FIG. 2(b)₁) Greater than C (Task) in FIG. 2(a)₁) That is to say Task₁The layout run is not arbitrary in fig. 2(b), which takes into account the layout run of the subsequent task, i.e. the closer the previous task layout is, the greater the success rate of the subsequent task layout run.

In summary, the invention discloses a digital twin system complex task layout tight coupling operation method and system, which comprises a digital twin system complex task layout tight coupling weight definition module design and a digital twin system complex task layout tight coupling calculation module design, and can solve the problem that a subsequent task cannot be laid out on an FPGA to run due to unreasonable previous task layout to a certain extent, and improve the operation efficiency of the digital twin system complex task on the FPGA.

Those skilled in the art will appreciate that the invention may be practiced without these specific details.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.