阅读说明：本技术 一种三态门 (Three-state gate ) 是由 沈孙园 于 2019-10-21 设计创作，主要内容包括：本发明公开了一种三态门。一种三态门包括第一PMOS管、第二PMOS管、第一NMOS管和第第二NMOS管。利用本发明提供的三态门可以得到三个稳定的电路输出状态。(The invention discloses a tri-state gate. A tri-state gate comprises a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube. The three-state gate provided by the invention can obtain three stable circuit output states.)

1. A tri-state gate, comprising: the NMOS transistor comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor;

the grid electrode of the first PMOS tube is connected with the input end B, the drain electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube, and the source electrode of the first PMOS tube is connected with a power supply voltage VCC; the grid electrode of the second PMOS tube is connected with the input end A, the drain electrode of the second PMOS tube is connected with the drain electrode of the first NMOS tube and serves as the output end OUT of the tri-state gate, and the source electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube; the grid electrode of the first NMOS tube is connected with the input end A, the drain electrode of the first NMOS tube is connected with the drain electrode of the second PMOS tube and serves as the output end OUT of the tri-state gate, and the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube; the grid electrode of the second NMOS tube is connected with the input end B, the drain electrode of the second NMOS tube is connected with the source electrode of the first NMOS tube, and the source electrode of the second NMOS tube is grounded.

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a tri-state gate.

Background

In order to obtain three stable circuit output states, a tri-state gate with stable performance needs to be arranged.

Disclosure of Invention

The present invention is directed to solving the deficiencies of the prior art and providing a tri-state gate.

A tri-state gate comprises a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube:

the grid electrode of the first PMOS tube is connected with the input end B, the drain electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube, and the source electrode of the first PMOS tube is connected with a power supply voltage VCC; the grid electrode of the second PMOS tube is connected with the input end A, the drain electrode of the second PMOS tube is connected with the drain electrode of the first NMOS tube and serves as the output end OUT of the tri-state gate, and the source electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube; the grid electrode of the first NMOS tube is connected with the input end A, the drain electrode of the first NMOS tube is connected with the drain electrode of the second PMOS tube and serves as the output end OUT of the tri-state gate, and the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube; the grid electrode of the second NMOS tube is connected with the input end B, the drain electrode of the second NMOS tube is connected with the source electrode of the first NMOS tube, and the source electrode of the second NMOS tube is grounded.

When the input end B of the tri-state gate is at a low level and the input end A is at a low level, the grid of the first PMOS tube is at a low level, the grid of the second PMOS tube is at a low level, and the output end OUT of the tri-state gate is at a high level; when the input end B of the tri-state gate is at a high level and the input end A is at a low level, the grid of the first PMOS tube is at a high level, the grid of the first NMOS tube is at a low level, and the output end OUT of the tri-state gate is at a high-resistance state; when the input end B of the tri-state gate is at a low level and the input end A is at a high level, the grid of the first PMOS tube is at a high level, the grid of the second NMOS tube is at a low level, and the output end OUT of the tri-state gate is at a high-resistance state; when the input end B of the tri-state gate is at a high level and the input end A is at a high level, the grid of the first NMOS tube is at a high level, the grid of the second NMOS tube is at a high level, and the output end OUT of the tri-state gate is at a low level.

Drawings

FIG. 1 is a circuit diagram of a tri-state gate of the present invention.

Detailed Description

The present invention will be further explained with reference to the accompanying drawings.

A tristate gate, as shown in FIG. 1, comprises a first PMOS transistor 10, a second PMOS transistor 20, a first NMOS transistor 30 and a second NMOS transistor 40:

the grid electrode of the first PMOS tube 10 is connected with the input end B, the drain electrode is connected with the source electrode of the second PMOS tube 20, and the source electrode is connected with a power supply voltage VCC; the gate of the second PMOS transistor 20 is connected to the input terminal a, the drain is connected to the drain of the first NMOS transistor 30 and serves as the output terminal OUT of the tri-state gate, and the source is connected to the drain of the first PMOS transistor 10; the grid electrode of the first NMOS tube 30 is connected with the input end A, the drain electrode is connected with the drain electrode of the second PMOS tube 20 and serves as the output end OUT of the tri-state gate, and the source electrode is connected with the drain electrode of the second NMOS tube 40; the gate of the second NMOS transistor 40 is connected to the input terminal B, the drain is connected to the source of the first NMOS transistor 30, and the source is grounded.

When the input end B of the tri-state gate is at a low level and the input end a is at a low level, the gate of the first PMOS transistor 10 is at a low level, the gate of the second PMOS transistor 20 is at a low level, and the output end OUT of the tri-state gate is at a high level; when the input end B of the tri-state gate is at a high level and the input end a is at a low level, the gate of the first PMOS transistor 10 is at a high level, the gate of the first NMOS transistor 30 is at a low level, and the output end OUT of the tri-state gate is at a high impedance state; when the input end B of the tri-state gate is at a low level and the input end a is at a high level, the gate of the first PMOS transistor 20 is at a high level, the gate of the second NMOS transistor 40 is at a low level, and the output end OUT of the tri-state gate is at a high impedance state; when the input end B of the tri-state gate is at a high level and the input end a is at a high level, the gate of the first NMOS transistor 30 is at a high level, the gate of the second NMOS transistor 40 is at a high level, and the output end OUT of the tri-state gate is at a low level.

The description of the embodiments provided above is merely illustrative of preferred embodiments of the present invention, and it will be apparent to those skilled in the art that the present invention can be implemented or used in light of the above description. It should be noted that, for those skilled in the art, it is possible to make several modifications and variations without departing from the technical principle of the present invention, and any invention that does not depart from the scope of the essential spirit of the present invention should be construed as the scope of the present invention.