阅读说明：本技术 Fpga重配置分区优化方法及系统 (FPGA reconfiguration partition optimization method and system ) 是由 梅文庆 李淼 杨胜 邱岳烽 郭赞 杨烁 罗云飞 凡林斌 于 2018-06-29 设计创作，主要内容包括：本发明涉及智能芯片技术领域,公开了一种FPGA重配置分区优化方法及系统,以提升FPGA的整体性能。本发明方法包括：确定重配置分区的数量和各所述重配置分区之间的输入输出接口连接关系；在相连接的两重配置分区之间,插入寄存器,并对各所述重配置分区的输入数据和输出数据转换为寄存器类型；对各所述重配置分区内相应各寄存器的位置进行约束,以保证配置分区之间的数据交互在物理上是最短路径,凭此减少延时。(The invention relates to the technical field of intelligent chips, and discloses a method and a system for optimizing a reconfiguration partition of an FPGA (field programmable gate array), so as to improve the overall performance of the FPGA. The method comprises the following steps: determining the number of the reconfiguration subareas and the input and output interface connection relation among the reconfiguration subareas; inserting a register between two connected reconfiguration partitions, and converting input data and output data of each reconfiguration partition into a register type; and constraining the positions of the corresponding registers in the reconfiguration partitions to ensure that the data interaction between the reconfiguration partitions is physically the shortest path, thereby reducing the delay.)

1. An FPGA reconfiguration partition optimization method is characterized by comprising the following steps:

determining the number of the reconfiguration subareas and the input and output interface connection relation among the reconfiguration subareas;

inserting a register between two connected reconfiguration partitions, and converting input data and output data of each reconfiguration partition into a register type;

and constraining the positions of corresponding registers in the reconfiguration partitions to ensure that the data interaction between the reconfiguration partitions is physically the shortest path.

2. The FPGA reconfiguration partition optimization method according to claim 1, wherein a constraint statement of FPGA compiled software is used to constrain a location of each corresponding register within each reconfiguration partition.

3. The FPGA reconfiguration partition optimization method according to claim 1 or 2, further comprising:

judging whether the link between the reconfiguration partitions meets the time sequence requirement or not;

for a path with time delay exceeding a time sequence requirement, selecting a combinational logic unit in at least one reconfiguration partition, cutting the combinational logic unit into at least two combinational logic subunits, and inserting a register between adjacent logic subunits in a Pipeline mode; and re-determining the execution time of the reconfigured partition.

4. The FPGA reconfiguration partition optimization method of claim 3, wherein said links comprise serial links and parallel links; the method further comprises the following steps:

after the execution time of one reconfiguration partition is determined again, based on global clock synchronization consideration, registers are also inserted into other related reconfiguration partitions or transmission links to ensure synchronism, and the maximum clock frequency of the system is calculated.

5. The FPGA reconfiguration partition optimization method according to claim 4, further comprising:

when algorithm processing is executed based on the FPGA, MATLAB is used for algorithm modeling, automatic generation from a model to a Verilog language is realized by means of HDL Workflow Advisor, and floating point numbers adopted during MATLAB modeling are converted into fixed point numbers executed by the FPGA by using HDLCoder.

6. An FPGA reconfiguration partition optimization system comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the steps of the method of any one of claims 1 to 5 are implemented when the computer program is executed by the processor.

Technical Field

The invention relates to the technical field of intelligent chips, in particular to a method and a system for optimizing a reconfiguration partition of an FPGA (field programmable gate array).

Background

An FPGA (Field-Programmable Gate Array), which is a product of further development based on Programmable devices such as PAL, GAL, CPLD, etc. The circuit is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), not only overcomes the defects of the custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited.

The FPGA adopts a concept of a Logic Cell array lca (Logic Cell array), and includes three parts, namely, a configurable Logic module clb (configurable Logic block), an input Output module iob (input Output block), and an internal connection (Interconnect). FPGAs are programmable devices that have a different structure than traditional logic circuits and gate arrays (e.g., PAL, GAL, and CPLD devices). The FPGA utilizes small lookup tables (16 × 1RAM) to realize combinational logic, each lookup table is connected to the input end of a D flip-flop, and the flip-flops drive other logic circuits or drive I/O (input/output) circuits, so that basic logic unit modules capable of realizing both combinational logic functions and sequential logic functions are formed, and the modules are connected with each other or connected to an I/O (input/output) module by utilizing metal connecting wires. The logic of the FPGA is implemented by loading programming data into the internal static memory cells, the values stored in the memory cells determine the logic function of the logic cells and the way of the connections between the modules or between the modules and the I/O and finally the functions that can be implemented by the FPGA, which allows an unlimited number of programming.

The wiring resources are communicated with all units in the FPGA, and the length and the process of the connecting line determine the driving capacity and the transmission speed of signals on the connecting line. The FPGA chip has abundant wiring resources inside, and is divided into 4 different categories according to different processes, lengths, widths and distribution positions. In existing FPGA development, it is generally not necessary to select routing resources directly, and the floorplan router can automatically select routing resources to connect the individual module cells according to the topology and constraint conditions of the input logic netlist. However, if the router is left free to route, there is no guarantee that data interactions between configuration partitions are physically shortest paths, which is detrimental to accurate control of latency.

Disclosure of Invention

The invention aims to disclose a method and a system for optimizing a reconfiguration partition of an FPGA (field programmable gate array), so as to improve the overall performance of the FPGA.

In order to achieve the aim, the invention discloses an FPGA reconfiguration partition optimization method, which comprises the following steps:

determining the number of the reconfiguration subareas and the input and output interface connection relation among the reconfiguration subareas;

inserting a register between two connected reconfiguration partitions, and converting input data and output data of each reconfiguration partition into a register type;

and constraining the positions of corresponding registers in the reconfiguration partitions to ensure that the data interaction between the reconfiguration partitions is physically the shortest path.

Preferably, the present invention may utilize a constraint statement of FPGA compiled software to constrain the location of each corresponding register within each reconfiguration partition.

Corresponding to the method, the invention also discloses an FPGA reconfiguration partition optimization system, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor realizes the steps of the method when executing the computer program.

The invention has the following beneficial effects:

aiming at the complex link relation among the reconfiguration partitions, the input data and the output data of the reconfiguration partitions are converted into register types, and the positions of the corresponding registers in the reconfiguration partitions are constrained to ensure that the data interaction among the reconfiguration partitions is physically the shortest path, so that the time delay is reduced, and the overall performance of the FPGA is improved.

The present invention will be described in further detail below with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:

fig. 1 is a flowchart of an FPGA reconfiguration partition optimization method according to a preferred embodiment of the present invention.

Detailed Description

The embodiments of the invention will be described in detail below with reference to the drawings, but the invention can be implemented in many different ways as defined and covered by the claims.