Semiconductor device with a plurality of transistors

文档序号：1568621 发布日期：2020-01-24 浏览：11次中文

阅读说明：本技术 半导体器件 (Semiconductor device with a plurality of transistors ) 是由金雄来于 2018-11-29 设计创作，主要内容包括：半导体器件包括锁存数据生成电路和列路径电路。当半导体器件进入图案输入模式时,锁存数据生成电路从外部信号中提取图案数据并且从提取的图案数据中生成锁存的数据。列路径电路在图案输入模式下输入写入命令时存储锁存的数据,并且在从输入写入命令的时间点开始经过写入等待时间之后,从存储在列路径电路中的锁存的数据生成模式数据。(The semiconductor device includes a latch data generation circuit and a column path circuit. When the semiconductor device enters a pattern input mode, the latch data generation circuit extracts pattern data from an external signal and generates latched data from the extracted pattern data. The column path circuit stores the latched data when a write command is input in the pattern input mode, and generates pattern data from the latched data stored in the column path circuit after a write latency time elapses from a time point at which the write command is input.)

1. A semiconductor device, comprising:

a latched data generation circuit configured to: extracting pattern data from an external signal and generating latched data from the extracted pattern data when the semiconductor device enters a pattern input mode; and

column path circuitry configured to: in the pattern input mode, storing the latched data when a write command is input, and configured to: generating mode data from the latched data stored in the column path circuit after a write latency elapses from a time point at which the write command is input.

2. The semiconductor device according to claim 1, wherein the latch data generation circuit is configured to latch the external signal in synchronization with an internal clock signal to generate the pattern data, and is configured to latch the pattern data in synchronization with a delay mode signal to generate the latched data.

3. The semiconductor device according to claim 2, wherein in the pattern input mode, the delay mode signal is generated by decoding the external signal input in synchronization with the internal clock signal.

4. The semiconductor device of claim 2, further comprising:

a mode entry control circuit configured to generate a mode signal for placing the semiconductor device in the pattern input mode from the external signal in response to a chip select signal and the internal clock signal; and

a mode signal delay circuit configured to delay the mode signal to generate the delayed mode signal.

5. The semiconductor device of claim 1, wherein the column path circuit is configured to store the latched data in response to a delay mode signal and is configured to output the latched data stored in the column path circuit in response to a delay mode output control signal and a write flag.

6. The semiconductor device as set forth in claim 5,

wherein the delay mode signal is generated in the pattern input mode; and

wherein the delay mode output control signal and the write flag are generated after the write latency has elapsed from a time point at which the write command is input.

7. The semiconductor device of claim 1, wherein the column path circuit comprises:

a pipe latch configured to store the latched data in response to a pipe input signal, which is counted when the delay mode signal is generated, and to output the latched data stored in the pipe latch as pipe data in response to a pipe output signal, which is counted when the delay mode output control signal and the write flag are generated; and

a data decoder configured to decode the pipe data to generate the mode data.

8. The semiconductor device according to claim 7, wherein the data decoder is configured to include a plurality of switches, and is configured to generate the mode data from the pipe data, the pipe data being selectively output from the plurality of switches in response to an option signal.

9. The semiconductor device according to claim 8, wherein a logic level of the option signal is determined according to an electrical open/short state of a fuse included in the semiconductor device.

10. The semiconductor device according to claim 1, wherein the latched data generation circuit reenters the pattern input mode to generate the latched data from the external signal during the write latency after the write command is input.

11. The semiconductor device according to claim 1, wherein the column path circuit receives a write flag and a delay mode output control signal to generate the mode data during the write latency after the write command is input.

12. A semiconductor device, comprising:

a latch data generation circuit configured to generate first latched data from first mode data when the semiconductor device enters a first pattern input mode in which first pattern data having a first logic level combination is input; and

a column path circuit configured to store the first latched data when a first write command is input in the first pattern input mode, and configured to generate first pattern data from the first latched data stored in the column path circuit after a write latency elapses from a time point at which the first write command is input.

13. The semiconductor device according to claim 12, wherein the column path circuit is configured to store the first latched data when a second write command is input during a period corresponding to the write latency after the first write command is input, and is configured to generate second mode data from the first latched data stored in the column path circuit after the write latency elapses from a time point at which the second write command is input.

14. The semiconductor device according to claim 12, wherein the latched data generation circuit is configured to generate second latched data from second pattern data when the semiconductor device enters a second pattern input mode in which the second pattern data having a second logic level combination is input during a period corresponding to the write latency after the first write command is input.

15. The semiconductor device according to claim 14, wherein the column path circuit is configured to store the second latched data when a second write command is input after the second latched data is generated, and is configured to generate second mode data from the second latched data stored in the column path circuit after the write latency has elapsed from a time point at which the second write command is input.

16. The semiconductor device according to claim 12, wherein the latch data generation circuit is configured to latch an external signal in synchronization with an internal clock signal to generate the first pattern data, and is configured to latch the first pattern data in synchronization with a delay mode signal to generate the first latched data.

17. The semiconductor device of claim 12, wherein the column path circuit is configured to store the first latched data in response to a delay mode signal and is configured to output the first latched data stored in the column path circuit in response to a delay mode output control signal and a write flag.

18. The semiconductor device of claim 12, wherein the column path circuit comprises:

a pipe latch configured to store the first latched data in response to a pipe input signal, the pipe input signal being counted when the delay mode signal is generated, and configured to output the first latched data stored in the pipe latch as pipe data in response to a pipe output, the pipe output signal being counted when the delay mode output control signal and the write flag are generated; and

a data decoder configured to decode the pipe data to generate the first mode data.

19. The semiconductor device of claim 18, wherein the data decoder is configured to include a plurality of switches and to generate the first mode data from the pipe data, the pipe data being selectively output from the plurality of switches in response to an option signal.

20. The semiconductor device according to claim 19, wherein a logic level of the option signal is determined according to an electrical open/short state of a fuse included in the semiconductor device.

21. A semiconductor device, comprising:

a column path circuit configured to store the latched data when a first write command is input in the pattern input mode, and configured to generate first pattern data from the latched data stored in the column path circuit after a write latency elapses from a time point at which the first write command is input,

wherein the column path circuit stores the latched data when a second write command is input during a period corresponding to the write latency after the first write command is input, and generates second mode data from the latched data stored in the column path circuit after the write latency elapses from a time point at which the second write command is input.

Technical Field

Various embodiments of the present invention generally relate to semiconductor devices that perform column operations.

Background

In general, a semiconductor device such as a Dynamic Random Access Memory (DRAM) device may include a plurality of bank groups composed of a cell array selected by an address. Each bank group may be implemented to include a plurality of banks. The semiconductor device may select any one of a plurality of bank groups, and may perform a column operation for outputting data stored in a cell array included in the selected bank group via an input/output (I/O) line.

Disclosure of Invention

According to one embodiment, a semiconductor device includes a latch data generation circuit and a column path circuit. The latch data generation circuit generates first latched data from first pattern data when the semiconductor device enters a first pattern input mode in which the first pattern data having a first logic level combination is input. The column path circuit stores the first latched data when the first write command is input in the first pattern input mode, and generates first pattern data from the first latched data stored in the column path circuit after a write latency time elapses from a time point at which the first write command is input.

According to one embodiment, a semiconductor device includes a latch data generation circuit and a column path circuit. When the semiconductor device enters a pattern input mode, the latch data generation circuit extracts pattern data from an external signal and generates latched data from the extracted pattern data. The column path circuit stores the latched data when a first write command is input in the pattern input mode, and generates first mode data from the latched data stored in the column path circuit after a write latency elapses from a time point at which the first write command is input. The column path circuit stores the latched data when a second write command is input during a period corresponding to the write latency after the first write command is input, and generates second pattern data from the latched data stored in the column path circuit after the write latency elapses from a time point at which the second write command is input.

Drawings

Fig. 1 is a block diagram illustrating a configuration of a semiconductor device according to one embodiment of the present disclosure.

Fig. 2 is a timing diagram illustrating an operation of an internal clock generation circuit included in the semiconductor device of fig. 1.

Fig. 3 is a block diagram illustrating a configuration of a mode control circuit included in the semiconductor device of fig. 1.

Fig. 4 is a block diagram illustrating a configuration of a latched data generating circuit included in the semiconductor device of fig. 1.

Fig. 5 is a graph illustrating an operation of the mode control circuit shown in fig. 3 and an operation of the latch data generation circuit shown in fig. 4.

Fig. 6 is a block diagram illustrating a configuration of a column control circuit included in the semiconductor device of fig. 1.

Fig. 7 is a block diagram illustrating a configuration of a column path circuit included in the semiconductor device of fig. 1.

Fig. 8 is a block diagram illustrating a configuration of a pattern data generation circuit included in the column path circuit of fig. 7.

Fig. 9 is a block diagram illustrating a configuration of a pipe latch included in the pattern data generation circuit of fig. 8.

Fig. 10 is a circuit diagram illustrating a configuration of a first pipe data generating circuit included in the pipe latch of fig. 9.

Fig. 11 and12 are circuit diagrams illustrating a configuration of a data decoder included in the pattern data generation circuit of fig. 8.

Fig. 13 and 14 are diagrams illustrating an operation of the data decoder shown in fig. 11 and 12.

Fig. 15 and 16 are timing diagrams illustrating an operation of the semiconductor device shown in fig. 1.

Fig. 17 is a block diagram illustrating a configuration of an electronic system using the semiconductor device shown in fig. 1.

Detailed Description

Various embodiments of the present disclosure will be described hereinafter with reference to the accompanying drawings. However, the embodiments described herein are for illustrative purposes only and are not intended to be the scope of the present disclosure.

As shown in fig. 1, a semiconductor device 1 according to an embodiment may include: an internal clock generation circuit 11, a mode control circuit 12, a latch data generation circuit 13, a column control circuit 14, a column path circuit 15, and a core circuit 16.

The internal clock generation circuit 11 may generate a first internal clock signal CLKr and a second internal clock signal CLKf from the clock signal CLK. The internal clock generation circuit 11 may buffer the clock signal CLK to generate a first internal clock signal CLKr, and may invert the buffered clock signal CLK to generate a second internal clock signal CLKf. The first internal clock signal CLKr may be generated to have the same phase as the clock signal CLK, and the second internal clock signal CLKf may be generated to have an opposite phase to the clock signal CLK. The operation of the internal clock generation circuit 11 will be described later with reference to fig. 2.

The mode control circuit 12 may generate a delay mode signal CAs _ WRXD and a delay mode output control signal WRX _ END from the first to fifth internal signals CA <1:5> in response to the first internal clock signal CLKr, the second internal clock signal CLKf, and the chip select signal CS. The external signal may include a command and an address. The mode control circuit 12 may decode the first to fourth external signals CA <1:4> input in synchronization with the chip selection signal CS and the first internal clock signal CLKr to generate a decoded command (CASd of fig. 3), and may latch the decoded command (CASd of fig. 3) in synchronization with the second internal clock signal CLKf to generate a mode command (CASF of fig. 3) for placing the semiconductor device 1 in various modes including a pattern input mode. In the pattern input mode, first to sixteenth mode data DC _ WRX <1:16> generated by decoding the first to fourth latch data LC <1:4> may be stored in the core circuit 16. When the mode command (CASF of fig. 3) is generated, the mode control circuit 12 may generate a mode signal (CAs _ WRX of fig. 3) for placing the semiconductor device 1 in the pattern input mode according to a logic level of the fifth external signal CA <5> input in synchronization with the second internal clock signal CLKf. Mode control circuit 12 may delay the mode signal (CAS _ WRX of fig. 3) to generate a delayed mode signal CAS _ WRXD. The delayed mode signal CAS _ WRXD may be generated to latch the first to fourth latch data LC <1:4> in the pipe latch (63 in fig. 8) included in the column path circuit 15. If the mode command (CASF of FIG. 3) and the mode signal (CAS _ WRX of FIG. 3) are generated, mode control circuitry 12 may generate the mode output control signal (WRX _ EN of FIG. 3). The mode control circuit 12 may shift the mode output control signal (WRX _ EN of fig. 3) by the write latency (write latency) to generate the delayed mode output control signal WRX _ END. The delay mode output control signal WRX _ END may be generated to output the first to fourth latch data LC <1:4> latched by the pipe latch (63 of fig. 8). The chip selection signal CS may be generated to have a predetermined logic level to select a chip including the semiconductor device 1. According to an embodiment, the number of bits included in the external signal for generating the delay mode signal CAS _ WRXD and the delay mode output control signal WRX _ END may be set to be different. The operation of the mode control circuit 12 will be described later with reference to fig. 4 and 5.

The latch data generation circuit 13 may generate first to fourth latch data LC <1:4> from the first to fourth external signals CA <1:4> in response to the second internal clock signal CLKf and the delay mode signal CAS _ WRXD. The latch data generation circuit 13 may generate the first to fourth latch data LC <1:4> used in the pattern input mode. The latch data generation circuit 13 may receive the first to fourth external signals CA <1:4> in synchronization with the second internal clock signal CLKf and may latch the first to fourth external signals CA <1:4> in synchronization with the delay mode signal CAs _ WRXD to generate the first to fourth latch data LC <1:4 >. The number of bits included in the external signal input to the latch data generation circuit 13 and the number of bits included in the latch data generated by the latch data generation circuit 13 may be set to be different according to the embodiment. The configuration and operation of the latch data generation circuit 13 will be described later with reference to fig. 4 and 5.

If the number of bits included in the external signal is "L" (where "L" denotes a natural number), the column control circuit 14 may generate the write flag WTTF and the column control pulses WTTAYP from the first to lth external signals CA <1: L > in response to the first and second internal clock signals CLKr and CLKf. The column control circuit 14 may generate a write signal (EWT of fig. 6) for performing a write operation according to a logic level combination of the first to lth external signals CA <1: L > input in response to the first and second internal clock signals CLKr and CLKf. The column control circuit 14 may delay the write signal (EWT of fig. 6) to generate the write flag WTTF and the column control pulse WTTAYP. The column control circuit 14 may delay the write signal (EWT of fig. 6) by a period corresponding to the write delay to generate the write flag WTTF and the column control pulse WTTAYP. The delay time of the write signal (EWT of fig. 6) for generating the write flag WTTF and the column control pulse WTTAYP in the column control circuit 14 may be set to be different according to the embodiment. The number of bits included in the external signal for generating the write flag WTTF and the column control pulse WTTAYP may be set to be different according to the embodiment. The configuration and operation of the column control circuit 14 will be described later with reference to fig. 6.

The column path circuit 15 may generate first to sixteenth mode data DC _ WRX <1:16> from the first to fourth latch data LC <1:4> in response to the delay mode signal CAS _ WRXD, the delay mode output control signal WRX _ END, and the write flag WTTF. The column path circuit 15 may store the first to fourth latch data LC <1:4> into the pipe latches (63 of fig. 8) of the column path circuit 15 in response to the delayed mode signal CAS _ WRXD. In one embodiment, in the pattern input mode, when a write command (WR of fig. 16) is input via the external signal CA <1: L >, the column path circuit 15 may store the first to fourth latch data LC <1:4> into the pipe latch (63 of fig. 8) of the column path circuit 15. The column path circuit 15 may output the first to fourth latch data LC <1:4> stored in the pipe latch (63 of fig. 8) as the first to fourth pipe data (PD <1:4> in fig. 8) in response to the delay mode output control signal WRX _ END and the write flag WTTF. In one embodiment, the column path circuit 15 may output the first to fourth latch data LC <1:4> stored in the pipe latch (63 of fig. 8) as the first to fourth pipe data (PD <1:4> of fig. 8) after the write latency elapses from a time point at which the write command (WR of fig. 16) is input via the external signal CA <1: L >. The column path circuit 15 may decode the first to fourth pipe data (PD <1:4> of fig. 8) to generate the first to sixteenth mode data DC _ WRX <1:16 >. The number of bits included in the latch data and the number of bits included in the mode data may be set to be different according to the embodiment. If the write flag WTTF and the column control pulse WTTAY are generated, the column path circuit 15 may generate first to Mth column bank group addresses AYP _ BG <1: M > from first to Lth external signals CA <1: L > in response to the first and second internal clock signals CLKr and CLKf. In the pattern input mode, the first to mth column bank group addresses AYP _ BG <1: M > may have a logic level combination for selecting a cell array included in the core circuit 16 storing the first to sixteenth mode data DC _ WRX <1:16 >. The first to mth column bank group addresses AYP _ BG <1: M > may include information on bank groups, banks, and column paths included in the core circuit 16. The number of bits "M" included in the first to mth column bank group addresses AYP _ BG <1: M > may be set to be different according to an embodiment. The configuration and operation of the column path circuit 15 will be described later with reference to fig. 7 to 14.

Referring to fig. 2, a first internal clock signal CLKr and a second internal clock signal CLKf are illustrated as being generated from a clock signal CLK in the internal clock generation circuit 11. The first internal clock signal CLKr may be generated to have the same phase as the clock signal CLK, and the second internal clock signal CLKf may be generated to have an opposite phase to the clock signal CLK.

As shown in fig. 3, the mode control circuit 12 may include: a mode entry control circuit 21, a mode signal delay circuit 22, and a mode output control circuit 23.

The mode entry control circuit 21 may include: a mode command generating circuit 211, a command/address latch circuit 212, and a mode signal generating circuit 213. The mode command generating circuit 211 may include a mode command decoder 215 and a mode command output circuit 216. The mode command decoder 215 may decode the first to fourth external signals CA <1:4> input in synchronization with the chip selection signal CS and the first internal clock signal CLKr to generate a decoded command CASd. If the first to fourth external signals CA <1:4> having a predetermined combination of logic levels are input to the mode command decoder 215 in synchronization with the rising edge of the first internal clock signal CLKr while the chip selection signal CS has a logic "high" level, the mode command decoder 215 may generate a decoded command CASd. The mode command output circuit 216 may latch the decoded command CASd in synchronization with a rising edge of the second internal clock signal CLKf, and may generate the mode command CASF from a latch command of the decoded command CASd. The mode command output circuit 216 may be implemented with a D flip-flop. The command/address latch circuit 212 may generate a latched external signal CAf <5> from the fifth external signal CA <5> in response to the second internal clock signal CLKf. The command/address latch circuit 212 may latch the fifth external signal CA <5> in synchronization with the rising edge of the second internal clock signal CLKf, and may output a latch signal of the fifth external signal CA <5> as the latched external signal CAf <5 >. If the fifth external signal CA <5> having a logic "high" level is input to the command/address latch circuit 212 in synchronization with the rising edge of the second internal clock signal CLKf, the command/address latch circuit 212 may generate the latched external signal CAf <5> having a logic "high" level. The command/address latch circuit 212 may be implemented with a D flip-flop. The mode signal generating circuit 213 may include an AND gate AND12 that performs a logical AND operation of the latched external signal CAf <5> AND the mode command CASF to generate the mode signal CAS _ WRX. If both the latched external signal CAf <5> and the mode command CASF have a logic "high" level, the mode signal generating circuit 213 may generate the mode signal CAS _ WRX having a logic "high" level.

If the first to fourth external signals CA <1:4> having a predetermined combination of logic levels are input to the mode entry control circuit 21 in synchronization with the rising edge of the first internal clock signal CLKr while the chip selection signal CS has a logic "high" level, the mode entry control circuit 21 may generate a mode command CASF for entering various modes including a pattern input mode. If the fifth external signal CA <5> having a logic "high" level is input to the mode entry control circuit 21 in synchronization with the second internal clock signal CLKf while the mode command CASF is generated, the mode entry control circuit 21 may generate a mode signal CAs _ WRX for entering the pattern input mode.

The mode signal delay circuit 22 may delay the mode signal CAS _ WRX to generate a delayed mode signal CAS _ WRXD. The delayed mode signal CAS _ WRXD may be generated to latch the first to fourth latch data LC <1:4> in the pipe latch (63 of fig. 8). The delay time of the mode signal CAS _ WRXD in the mode signal delay circuit 22 may be set to be different according to the embodiment.

The mode output control circuit 23 may include: a Column Address Strobe (CAS) delay circuit 231, a mode output control signal generation circuit 232, and a mode output delay circuit 233. The "CAS" delay circuit 231 may delay the mode command CASF to generate a delayed mode command CASFD. The delay time of the mode command CASF in the "CAS" delay circuit 231 may be set to be different according to the embodiment. The mode output control signal generation circuit 232 may generate the mode output control signal WRX _ EN if both the delayed mode command CASFD and the mode signal CAS _ WRX are generated. The mode output delay circuit 233 may delay the mode output control signal WRX _ EN in response to the write latency signal WL <1: L > to generate the delayed mode output control signal WRX _ END. The write latency signal WL <1: L > may have a logic level combination corresponding to the write latency of the semiconductor device 1. The mode output delay circuit 233 may shift the mode output control signal WRX _ EN by the write latency corresponding to the write latency signal WL <1: L > to generate the delayed mode output control signal WRX _ END.

As described above, the mode output control circuit 23 may shift the mode output control signal WRX _ EN, which is generated if both the mode command CASF and the mode signal CAS _ WRX are generated, by the write latency to generate the delayed mode output control signal WRX _ END. The delay mode output control signal WRX _ END may be generated to output the first to fourth latch data LC <1:4> latched by the pipe latch (63 of fig. 8).

As shown in fig. 4, the latch data generation circuit 13 may include: a first latch data generation circuit 31, a second latch data generation circuit 32, a third latch data generation circuit 33, and a fourth latch data generation circuit 34.

The first latch data generation circuit 31 may include a first pattern data generation circuit 311 and a first latch data output circuit 312. The first pattern data generation circuit 311 may latch the first external signal CA <1> in synchronization with a rising edge of the second internal clock signal CLKf, and may output a latch signal of the first external signal CA <1> as the first pattern data DC <1 >. The first latch data output circuit 312 may latch the first pattern data DC <1> if the delay mode signal CAS _ WRXD is generated, and may output the latched data of the first pattern data DC <1> as the first latch data LC <1 >. Each of the first pattern data generation circuit 311 and the first latch data output circuit 312 may be implemented with a D flip-flop.

The second latch data generation circuit 32 may include a second pattern data generation circuit 321 and a second latch data output circuit 322. The second pattern data generation circuit 321 may latch the second external signal CA <2> in synchronization with a rising edge of the second internal clock signal CLKf, and may output a latch signal of the second external signal CA <2> as the second pattern data DC <2 >. The second latch data output circuit 322 may latch the second pattern data DC <2> if the delay mode signal CAS _ WRXD is generated, and may output the latch data of the second pattern data DC <2> as the second latch data LC <2 >. Each of the second pattern data generation circuit 321 and the second latch data output circuit 322 may be implemented with a D flip-flop.

The third latch data generation circuit 33 may include a third pattern data generation circuit 331 and a third latch data output circuit 332. The third pattern data generation circuit 331 may latch the third external signal CA <3> in synchronization with a rising edge of the second internal clock signal CLKf, and may output a latch signal of the third external signal CA <3> as the third pattern data DC <3 >. The third latch data output circuit 332 may latch the third pattern data DC <3> if the delay mode signal CAS _ WRXD is generated, and may output the latch data of the third pattern data DC <3> as the third latch data LC <3 >. Each of the third pattern data generation circuit 331 and the third latch data output circuit 332 may be implemented with a D flip-flop.

The fourth latch data generation circuit 34 may include a fourth pattern data generation circuit 341 and a fourth latch data output circuit 342. The fourth pattern data generation circuit 341 may latch the fourth external signal CA <4> in synchronization with the rising edge of the second internal clock signal CLKf, and may output the latch signal of the fourth external signal CA <4> as the fourth pattern data DC <4 >. If the delay mode signal CAS _ WRXD is generated, the fourth latch data output circuit 342 may latch the fourth pattern data DC <4>, and may output the latch data of the fourth pattern data DC <4> as the fourth latch data LC <4 >. Each of the fourth pattern data generation circuit 341 and the fourth latch data output circuit 342 may be implemented with a D flip-flop.

As described above, the latch data generation circuit 13 may generate the first to fourth latch data LC <1:4> from the first to fourth external signals CA <1:4> in response to the second internal clock signal CLKf and the delay mode signal CAS _ WRXD. In the pattern input mode, the latch data generation circuit 13 may generate the first to fourth latch data LC <1:4> stored into the core circuit 16. The latch data generation circuit 13 may receive the first to fourth external signals CA <1:4> in synchronization with the second internal clock signal CLKf and may latch the first to fourth external signals CA <1:4> in synchronization with the delay mode signal CAs _ WRXD to generate the first to fourth latch data LC <1:4 >. In one embodiment, the latch data generation circuit 13 may reenter the pattern input mode by the external signals CA <1: L > during a write latency (i.e., a write latency period) after the input of the write command (WR of fig. 15) to generate the latch data from the first to fourth external signals CA <1:4 >.

As shown in fig. 5, an operation for setting the mode command CASF and the mode signal CAS _ WRX in the mode control circuit 12 is illustrated, and an operation for setting the first to fourth pattern data <1:4> in the latch data generation circuit is illustrated.

The mode command CASF may be generated if the chip select signal CS has a logic "high" level and the first to fourth external signals CA <1:4> are set to have a logic level combination "L, L, H, H" in synchronization with a rising edge of the first internal clock signal CLKr. If the chip select signal CS has a logic "high" level, the fifth, sixth and seventh external signals CA <5:7> may be set to the first, second and third set commands WS _ WR, WS _ RD and WS _ FS, respectively, in synchronization with the rising edge of the first internal clock signal CLKr. The first set command WS _ WR may be generated to receive a clock for a data I/O operation when performing a write operation. The second set command WS _ RD may be generated to receive a clock for a data I/O operation when a read operation is performed. The third set command WS _ FS may be generated for a multi-bank operation. The first to seventh external signals CA <1:7> may be set to the first to fourth pattern data DC <1:4>, the mode signal CAs _ WRX, the signal having the active logic level V, and the control signal B3, respectively, for determining a burst sequence in synchronization with a rising edge of the second internal clock signal CLKf after the mode command CASF is generated. The active logic level V may be set to a logic "high" level or a logic "low" level.

As shown in fig. 6, the column control circuit 14 may include: a write signal generation circuit 41, a write flag generator 42, and a column control pulse generator 43.

The write signal generation circuit 41 may decode the first to lth external signals CA <1: L > in synchronization with the first and second internal clock signals CLKr and CLKf to generate a write signal EWT for performing a write operation. To generate the write signal EWT, a write command (WR of fig. 15) may be input to the semiconductor device 1 via the first to lth external signals CA <1: L > in synchronization with the first and second internal clock signals CLKr and CLKf. According to an embodiment, a clock for generating the write signal EWT may be set to the first internal clock signal CLKr or the second internal clock signal CLKf. The number of bits "L" included in the first to lth external signals CA <1: L > used to generate the write signal EWT may be set to be different according to embodiments.

The write flag generator 42 may shift the write signal EWT by a predetermined period to generate the write flag WTTF. The write flag generator 42 may shift the write signal EWT by a period set according to the write latency to generate the write flag WTTF.

The column control pulse generator 43 may shift the write signal EWT by a predetermined period to generate the column control pulse WTTAYP. The column control pulse generator 43 may shift the write signal EWT by a period set according to the write latency to generate the column control pulse WTTAYP.

As shown in fig. 7, the column path circuit 15 may include a pattern data generation circuit 51 and a column bank group address generation circuit 52.

The mode data generation circuit 51 may generate first to sixteenth mode data DC _ WRX <1:16> from among the first to fourth latch data LC <1:4> in response to the delayed mode signal CAS _ WRXD, the delayed mode output control signal WRX _ END, and the write flag WTTF. The mode data generation circuit 51 may store the first to fourth latch data LC <1:4> into the pipe latch (63 in fig. 8) in response to the delayed mode signal CAS _ WRXD. The mode data generation circuit 51 may output the first to fourth latch data LC <1:4> stored in the pipe latch (63 of fig. 8) as the first to fourth pipe data (PD <1:4> of fig. 8) in response to the delay mode output control signal WRX _ END and the write flag WTTF. The pattern data generation circuit 51 may decode the first to fourth pipe data (PD <1:4> of fig. 8) to generate the first to sixteenth pattern data DC _ WRX <1:16 >. In one embodiment, when the mode data generation circuit 51 receives the delay mode output control signal WRX _ END and the write flag WTTF during a write latency (i.e., a write latency period) after the write command (WR of fig. 15) is input, the mode data generation circuit 51 may output the first to fourth latch data LC <1:4> stored in the pipe latch (63 of fig. 8) as the first to fourth pipe data (PD <1:4> of fig. 8), and the mode data generation circuit 51 may decode the first to fourth pipe data (PD <1:4> of fig. 8) to generate the first to sixteenth mode data DC _ WRX <1:16 >.

If the write flag WTTF and the column control pulse WTTAYP are generated, the column bank group address generating circuit 52 may generate first to mth column bank group addresses AYP _ BG <1: M > from first to lth external signals CA <1: L > in response to the first and second internal clock signals CLKr and CLKf. In the pattern input mode, the first to mth column bank group addresses AYP _ BG <1: M > may have a logic level combination for selecting a cell array included in the core circuit 16 storing the first to sixteenth mode data DC _ WRX <1:16 >. The first to mth column bank group addresses AYP _ BG <1: M > may include information on bank groups, banks, and column paths included in the core circuit 16.

As shown in fig. 8, the pattern data generation circuit 51 may include: a pipe input counter 61, a pipe output counter 62, a pipe latch 63, and a data decoder 64.

The pipe input counter 61 may sequentially generate the first to third pipe input signals PIN <1:3> in response to the delay mode signal CAS _ WRXD. The pipe input counter 61 may generate a first pipe input signal PIN <1> when the delay mode signal CAS _ WRXD is generated for the first time. When the delayed mode signal CAS _ WRXD is generated for the second time, the pipe input counter 61 may generate a second pipe input signal PIN <2 >. When the delayed mode signal CAS _ WRXD is generated for the third time, the pipe input counter 61 may generate a third pipe input signal PIN <3 >. For example, the pipe input counter 61 may count the first to third pipe input signals PIN <1:3> when the delayed mode signal CAS _ WRXD is generated for the first, second and third times.

The pipe output counter 62 may sequentially generate the first to third pipe output signals POUT <1:3> in response to the delay mode output control signal WRX _ END and the write flag WTTF. When the delay mode output control signal WRX _ END and the write flag WTTF are generated for the first time, the pipe output counter 62 may generate a first pipe output signal POUT <1 >. When the delay mode output control signal WRX _ END and the write flag WTTF are generated for the second time, the pipe output counter 62 may generate a second pipe output signal POUT <2 >. When the delay mode output control signal WRX _ END and the write flag WTTF are generated for the third time, the pipe output counter 62 may generate a third pipe output signal POUT <3 >. For example, pipe output counter 62 may count the first through third pipe output signals POUT <1:3> when the delay mode output control signal WRX _ END and the write flag WTTF are generated for the first, second, and third times.

The pipe latch 63 may generate first to fourth pipe data PD <1:4> from the first to fourth latch data LC <1:4> in response to the first to third pipe input signals PIN <1:3> and the first to third pipe output signals POUT <1:3 >. The pipe latch 63 may latch (i.e., store) the first to fourth latch data LC <1:4> in response to the first to third pipe input signals PIN <1:3 >. The pipe latch 63 may output latched data (i.e., stored data) of the first to fourth latch data LC <1:4> as the first to fourth pipe data PD <1:4> in response to the first to third pipe output signals POUT <1:3 >. The configuration and operation of the pipe latch 63 will be described later with reference to fig. 9 and 10.

The data decoder 64 may decode the first through fourth pipe data PD <1:4> to generate first through sixteenth mode data DC _ WRX <1:16 >. The logic level combinations of the first to fourth pipe data PD <1:4> and the logic level combinations of the first to sixteenth mode data DC _ WRX <1:16> generated by the data decoder 64 in response to the logic level combinations of the first to fourth pipe data PD <1:4> may be set to be different according to an embodiment. The configuration and operation of the data decoder 64 will be described later with reference to fig. 11 to 14.

As shown in fig. 9, the pipe latch 63 may include: a first pipe data generation circuit 71, a second pipe data generation circuit 72, a third pipe data generation circuit 73, and a fourth pipe data generation circuit 74.

The first pipe data generation circuit 71 may generate first pipe data PD <1> from the first latch data LC <1> in response to the first to third pipe input signals PIN <1:3> and the first to third pipe output signals POUT <1:3 >. The first pipe data generation circuit 71 may latch the first latch data LC <1> in response to the first to third pipe input signals PIN <1:3 >. The first pipe data generation circuit 71 may output the latched data of the first latch data LC <1> as the first pipe data PD <1> in response to the first to third pipe output signals POUT <1:3 >. The configuration and operation of the first pipeline data generation circuit 71 will be described later with reference to fig. 10.

The second pipe data generation circuit 72 may generate second pipe data PD <2> from the second latch data LC <2> in response to the first to third pipe input signals PIN <1:3> and the first to third pipe output signals POUT <1:3 >. The second pipe data generation circuit 72 may latch the second latch data LC <2> in response to the first to third pipe input signals PIN <1:3 >. The second pipe data generation circuit 72 may output the latched data of the second latch data LC <2> as second pipe data PD <2> in response to the first to third pipe output signals POUT <1:3 >.

The third pipeline data generation circuit 73 may generate third pipeline data PD <3> from third latch data LC <3> in response to the first to third pipeline input signals PIN <1:3> and the first to third pipeline output signals POUT <1:3 >. The third pipe data generation circuit 73 may latch the third latch data LC <3> in response to the first to third pipe input signals PIN <1:3 >. The third pipeline data generation circuit 73 may output latched data of the third latch data LC <3> as third pipeline data PD <3> in response to the first to third pipeline output signals POUT <1:3 >.

The fourth pipe data generation circuit 74 may generate fourth pipe data PD <4> from fourth latch data LC <4> in response to the first to third pipe input signals PIN <1:3> and the first to third pipe output signals POUT <1:3 >. The fourth pipe data generation circuit 74 may latch the fourth latch data LC <4> in response to the first to third pipe input signals PIN <1:3 >. The fourth pipe data generation circuit 74 may output the latched data of the fourth latch data LC <4> as fourth pipe data PD <4> in response to the first to third pipe output signals POUT <1:3 >.

As shown in fig. 10, the first pipeline data generation circuit 71 may include: a data input circuit 81, a data latch circuit 82, a pattern data output circuit 83, and a pattern data output latch 84.

The data input circuit 81 may include inverters IV811 to IV 816. The inverter IV811 may invert the buffered first pipe input signal PIN <1> to output an inverted buffered signal of the first pipe input signal PIN <1 >. If the first pipe input signal PIN <1> has a logic "high" level, the inverter IV812 may invert the buffered first latch data LC <1> to output the inverted buffered data of the first latch data LC <1> to the node nd 81. Inverter IV813 may invert the buffered second pipe input signal PIN <2> to output an inverted buffered signal of the second pipe input signal PIN <2 >. If the second pipe input signal PIN <2> has a logic "high" level, the inverter IV814 may invert the buffered first latch data LC <1> to output the inverted buffered data of the first latch data LC <1> to the node nd 83. Inverter IV815 may invert the buffered third pipe input signal PIN <3> to output an inverted buffered signal of the third pipe input signal PIN <3 >. If the third pipe input signal PIN <3> has a logic "high" level, the inverter IV816 may invert the buffered first latch data LC <1> to output the inverted buffered data of the first latch data LC <1> to the node nd 85.

The data latch circuit 82 may include inverters IV821 to IV 826. The inverter IV821 may invert the signal of the buffer node nd81 to output an inverted buffered signal of the node nd81 to the node nd 82. The inverter IV822 may invert the signal of the buffer node nd82 to output an inverted buffered signal of the node nd82 to the node nd 81. That is, the inverters IV821 and IV822 may latch signals of the nodes nd81 and nd 82. The inverter IV823 may invert the signal of the buffer node nd83 to output an inverted buffered signal of the node nd83 to the node nd 84. The inverter IV824 may invert the signal of the buffer node nd84 to output an inverted buffered signal of the node nd84 to the node nd 83. That is, the inverter IV823 and the inverter IV824 may latch signals of the node nd83 and the node nd 84. The inverter IV825 may invert the signal of the buffer node nd85 to output an inverted buffered signal of the node nd85 to the node nd 86. The inverter IV826 may invert the signal of the buffer node nd86 to output an inverted buffered signal of the node nd86 to the node nd 85. That is, the inverter IV825 and the inverter IV826 may latch signals of the node nd85 and the node nd 86.

The pattern data output circuit 83 may include inverters IV831 to IV 836. Inverter IV831 may invert the buffered first pipe output signal POUT <1> to output an inverted buffered signal of first pipe output signal POUT <1 >. If the first pipe output signal POUT <1> has a logic "high" level, the inverter IV832 may invert the signal of the buffer node nd82 to output the inverted buffered data of the signal of the node nd82 to the node nd 87. Inverter IV833 may invert the buffered second pipe output signal POUT <2> to output an inverted buffered signal of second pipe output signal POUT <2 >. If the second pipe output signal POUT <2> has a logic "high" level, the inverter IV834 may invert the signal of the buffer node nd84 to output the inverted buffered data of the signal of the node nd84 to the node nd 87. Inverter IV835 may invert the buffered third pipe output signal POUT <3> to output an inverted buffered signal of the third pipe output signal POUT <3 >. If the third pipe output signal POUT <3> has a logic "high" level, the inverter IV836 may invert the signal of the buffer node nd86 to output the inverted buffered data of the signal of the node nd86 to the node nd 87.

The pattern data output latch 84 may include an inverter IV841 and an inverter IV 842. The inverter IV841 may invert the signal of the buffer node nd87 to output the inverted buffered signal of the node nd87 as the first pipe data PD <1> via the node nd 88. The inverter IV842 may invert the signal of the buffer node nd88 to output an inverted buffered signal of the node nd88 to the node nd 87. That is, the inverters IV841 and IV842 can latch signals of the nodes nd87 and nd 88.

As described above, the first pipe data generation circuit 71 may latch the first latch data LC <1> in response to the first to third pipe input signals PIN <1:3 >. The first pipe data generation circuit 71 may output the latch data of the first latch data LC <1> as the first pipe data PD <1> in response to the first to third pipe output signals POUT <1:3 >.

As shown in fig. 11 and12, the data decoder 64 may include: an inverted option signal generating circuit 910, a first mode data selecting circuit 911, a second mode data selecting circuit 912, a third mode data selecting circuit 913, a fourth mode data selecting circuit 914, a fifth mode data selecting circuit 915, a sixth mode data selecting circuit 916, a seventh mode data selecting circuit 917, an eighth mode data selecting circuit 918, a ninth mode data selecting circuit 921, a tenth mode data selecting circuit 922, an eleventh mode data selecting circuit 923, a twelfth mode data selecting circuit 924, a thirteenth mode data selecting circuit 925, a fourteenth mode data selecting circuit 926, a fifteenth mode data selecting circuit 927, and a sixteenth mode data selecting circuit 928.

The inverting option signal generating circuit 910 may include: an inverter IV911 inverts the buffer option signal OPT to generate an inverted option signal OPTB. In one embodiment, the logic level of the option signal OPT may be determined according to an electrical open/short state of a fuse (not shown) included in the semiconductor device 1. According to an embodiment, the option signal OPT may be provided by an external device or may be generated by the semiconductor device 1.

The first mode data selection circuit 911 may include switches SW911 and SW912, and an inverter IV911, an inverter IV912, and an inverter IV 931. The switch SW911 may selectively output the second pipe data PD <2> or the first pipe data PD <1 >. The switch SW912 may selectively output the fourth pipe data PD <4> or the third pipe data PD <3 >. If the option signal OPT has a logic "low" level, the inverter IV911 may invert the output signal of the buffer switch SW911 to output an inverted buffer signal of the output signal of the switch SW 911. If the option signal OPT has a logic "high" level, the inverter IV912 may invert the output signal of the buffer switch SW912 to output an inverted buffer signal of the output signal of the switch SW 912. The inverter 931 may invert the output signal of the buffer inverter IV911 or the inverter IV912 to output the inverted buffer signal of the output signal of the inverter IV911 or the inverter IV912 as the fourth mode data DC _ WRX <4 >. In one embodiment, the switch SW911 may be configured to output the first pipe data PD <1>, the switch SW912 may be configured to output the fourth pipe data PD <4>, and the option signal OPT may be set to have a logic "high" level. Accordingly, the first mode data selection circuit 911 may output the fourth pipe data PD <4> as the fourth mode data DC _ WRX <4 >.

The second mode data selection circuit 912 may include switches SW913 and SW914 and inverters IV913, IV914 and IV 932. The switch SW913 may selectively output the second pipe data PD <2> or the first pipe data PD <1 >. The switch SW914 may selectively output the fourth pipe data PD <4> or the third pipe data PD <3 >. The inverter IV913 may invert the output signal of the buffer switch SW913 to output an inverted buffer signal of the output signal of the switch SW913 if the option signal OPT has a logic "low" level. If the option signal OPT has a logic "high" level, the inverter IV914 may invert the output signal of the buffer switch SW914 to output an inverted buffer signal of the output signal of the switch SW 914. The inverter 932 may invert the output signal of the buffer inverter IV913 or the inverter IV914 to output the inverted buffer signal of the output signal of the inverter IV913 or the inverter IV914 as the eighth mode data DC _ WRX <8 >. In one embodiment, the switch SW913 may be configured to output the first pipe data PD <1>, the switch SW914 may be configured to output the fourth pipe data PD <4>, and the option signal OPT may be set to have a logic "high" level. Accordingly, the second mode data selection circuit 912 may output the fourth pipe data PD <4> as the eighth mode data DC _ WRX <8 >.

The third mode data selection circuit 913 may include switches SW915 and SW916, and an inverter IV915, an inverter IV916, and an inverter IV 933. The switch SW915 may selectively output the second pipe data PD <2> or the first pipe data PD <1 >. The switch SW916 may selectively output the fourth pipe data PD <4> or the third pipe data PD <3 >. If the option signal OPT has a logic "low" level, the inverter IV915 may invert the output signal of the buffer switch SW915 to output an inverted buffered signal of the output signal of the switch SW 915. If the option signal OPT has a logic "high" level, the inverter IV916 may invert the output signal of the buffer switch SW916 to output an inverted buffer signal of the output signal of the switch SW 916. The inverter 933 may invert the output signal of the buffer inverter IV915 or the inverter IV916 to output the inverted buffer signal of the output signal of the inverter IV915 or the inverter IV916 as the third mode data DC _ WRX <3 >. In one embodiment, the switch SW915 may be configured to output the first pipe data PD <1>, the switch SW916 may be configured to output the third pipe data PD <3>, and the option signal OPT may be set to have a logic "high" level. Accordingly, the third mode data selection circuit 913 may output the third pipe data PD <3> as the third mode data DC _ WRX <3 >.

The fourth mode data selection circuit 914 may include switches SW917 and SW918 and inverters IV917, IV918, and IV 934. The switch SW917 may selectively output the second pipe data PD <2> or the first pipe data PD <1 >. The switch SW918 may selectively output the fourth pipe data PD <4> or the third pipe data PD <3 >. The inverter IV917 may invert the output signal of the buffer switch SW917 to output an inverted buffer signal of the output signal of the switch SW917 if the option signal OPT has a logic "low" level. If the option signal OPT has a logic "high" level, the inverter IV918 may invert the output signal of the buffer switch SW918 to output an inverted buffer signal of the output signal of the switch SW 918. The inverter 934 may invert the output signal of the buffer inverter IV917 or the inverter IV918 to output the inverted buffer signal of the output signal of the inverter IV917 or the inverter IV918 as the seventh mode data DC _ WRX <7 >. In one embodiment, the switch SW917 may be configured to output the first pipe data PD <1>, the switch SW918 may be configured to output the third pipe data PD <3>, and the option signal OPT may be set to have a logic "high" level. Accordingly, the fourth mode data selection circuit 914 may output the third pipe data PD <3> as seventh mode data DC _ WRX <7 >.

The fifth mode data selection circuit 915 may include switches SW921 and SW922 and inverters IV921, IV922 and IV 935. The switch SW921 may selectively output the fourth pipe data PD <4> or the third pipe data PD <3 >. The switch SW922 may selectively output the second pipe data PD <2> or the first pipe data PD <1 >. If the option signal OPT has a logic "low" level, the inverter IV921 may invert the output signal of the buffer switch SW921 to output an inverted buffered signal of the output signal of the switch SW 921. If the option signal OPT has a logic "high" level, the inverter IV922 may invert the output signal of the buffer switch SW922 to output an inverted buffered signal of the output signal of the switch SW 922. The inverter 935 may invert the output signal of the buffer inverter IV921 or the inverter IV922 to output the inverted buffered signal of the output signal of the inverter IV921 or the inverter IV922 as the second mode data DC _ WRX <2 >. In one embodiment, the switch SW921 may be configured to output the third pipe data PD <3>, the switch SW922 may be configured to output the second pipe data PD <2>, and the option signal OPT may be set to have a logic "high" level. Accordingly, the fifth mode data selection circuit 915 may output the second pipe data PD <2> as the second mode data DC _ WRX <2 >.

The sixth mode data selection circuit 916 may include switches SW923 and SW924, and inverters IV923, IV924, and IV 936. The switch SW923 may selectively output the fourth pipe data PD <4> or the third pipe data PD <3 >. The switch SW924 may selectively output the second pipe data PD <2> or the first pipe data PD <1 >. If the option signal OPT has a logic "low" level, the inverter IV923 may invert the output signal of the buffer switch SW923 to output an inverted buffered signal of the output signal of the switch SW 923. If the option signal OPT has a logic "high" level, the inverter IV924 may invert the output signal of the buffer switch SW924 to output an inverted buffer signal of the output signal of the switch SW 924. The inverter 936 may invert the output signal of the buffer inverter IV923 or the inverter IV924 to output the inverted buffer signal of the output signal of the inverter IV923 or the inverter IV924 as the sixth mode data DC _ WRX <6 >. In one embodiment, the switch SW923 may be configured to output the third pipe data PD <3>, the switch SW924 may be configured to output the second pipe data PD <2>, and the option signal OPT may be set to have a logic "high" level. Accordingly, the sixth mode data selection circuit 916 may output the second pipe data PD <2> as sixth mode data DC _ WRX <6 >.

The seventh mode data selecting circuit 917 may include switches SW925 and SW926, and an inverter IV925, an inverter IV926, and an inverter IV 937. The switch SW925 may selectively output the fourth pipe data PD <4> or the third pipe data PD <3 >. The switch SW926 may selectively output the second pipe data PD <2> or the first pipe data PD <1 >. If the option signal OPT has a logic "low" level, the inverter IV925 may invert the output signal of the buffer switch SW925 to output an inverted buffered signal of the output signal of the switch SW 925. If the option signal OPT has a logic "high" level, the inverter IV926 may invert the output signal of the buffer switch SW926 to output an inverted buffer signal of the output signal of the switch SW 926. The inverter 937 may invert the output signal of the buffer inverter IV925 or the inverter IV926 to output the inverted buffered signal of the output signal of the inverter IV925 or the inverter IV926 as the first mode data DC _ WRX <1 >. In one embodiment, the switch SW925 may be configured to output the third pipe data PD <3>, the switch SW926 may be configured to output the first pipe data PD <1>, and the option signal OPT may be set to have a logic "high" level. Accordingly, the seventh mode data selection circuit 917 may output the first pipe data PD <1> as the first mode data DC _ WRX <1 >.

The eighth mode data selecting circuit 918 may include switches SW927 and SW928 and an inverter IV927, an inverter IV928, and an inverter IV 938. The switch SW927 may selectively output the fourth pipe data PD <4> or the third pipe data PD <3 >. The switch SW928 may selectively output the second pipe data PD <2> or the first pipe data PD <1 >. If the option signal OPT has a logic "low" level, the inverter IV927 may invert the output signal of the buffer switch SW927 to output an inverted buffer signal of the output signal of the switch SW 927. If the option signal OPT has a logic "high" level, the inverter IV928 may invert the output signal of the buffer switch SW928 to output an inverted buffer signal of the output signal of the switch SW 928. The inverter 938 may invert the output signal of the buffer inverter IV927 or the inverter IV928 to output an inverted buffered signal of the output signal of the inverter IV927 or the inverter IV928 as the fifth mode data DC _ WRX <5 >. In one embodiment, the switch SW927 may be configured to output the third pipe data PD <3>, the switch SW928 may be configured to output the first pipe data PD <1>, and the option signal OPT may be set to have a logic "high" level. Accordingly, the eighth mode data selection circuit 918 may output the first pipe data PD <1> as fifth mode data DC _ WRX <5 >.

The ninth mode data selection circuit 921 may include switches SW941 and SW942 and inverters IV941, IV942 and IV 961. The switch SW941 may selectively output the second pipe data PD <2> or the first pipe data PD <1 >. The switch SW942 may selectively output the fourth pipe data PD <4> or the third pipe data PD <3 >. If the option signal OPT has a logic "low" level, the inverter IV941 may invert the output signal of the buffer switch SW941 to output an inverted buffer signal of the output signal of the switch SW 941. The inverter IV942 may invert the output signal of the buffer switch SW942 to output an inverted buffer signal of the output signal of the switch SW942 if the option signal OPT has a logic "high" level. The inverter 961 may invert the output signal of the buffer inverter IV941 or the inverter IV942 to output an inverted buffer signal of the output signal of the inverter IV941 or the inverter IV942 as the twelfth mode data DC _ WRX <12 >. In one embodiment, the switch SW941 may be configured to output the first pipe data PD <1>, the switch SW942 may be configured to output the fourth pipe data PD <4>, and the option signal OPT may be set to have a logic "high" level. Accordingly, the ninth mode data selection circuit 921 may output the fourth pipe data PD <4> as the twelfth mode data DC _ WRX <12 >.

The tenth mode data selection circuit 922 may include switches SW943 and SW944, and inverters IV943, IV944, and IV 962. The switch SW943 may selectively output the second pipe data PD <2> or the first pipe data PD <1 >. The switch SW944 may selectively output the fourth pipe data PD <4> or the third pipe data PD <3 >. If the option signal OPT has a logic "low" level, the inverter IV943 may invert the output signal of the buffer switch SW943 to output an inverted buffer signal of the output signal of the switch SW 943. If the option signal OPT has a logic "high" level, the inverter IV944 may invert the output signal of the buffer switch SW944 to output an inverted buffer signal of the output signal of the switch SW 944. The inverter 962 may invert the output signal of the buffer inverter IV943 or the inverter IV944 to output an inverted buffer signal of the output signal of the inverter IV943 or the inverter IV944 as the sixteenth mode data DC _ WRX <16 >. In one embodiment, the switch SW943 may be configured to output the first pipe data PD <1>, the switch SW944 may be configured to output the fourth pipe data PD <4>, and the option signal OPT may be set to have a logic "high" level. Accordingly, the tenth mode data selection circuit 922 may output the fourth pipe data PD <4> as the sixteenth mode data DC _ WRX <16 >.

The eleventh mode data selecting circuit 923 may include switches SW945 and SW946 and inverters IV945, IV946 and IV 963. The switch SW945 may selectively output the second pipe data PD <2> or the first pipe data PD <1 >. The switch SW946 may selectively output the fourth pipe data PD <4> or the third pipe data PD <3 >. If the option signal OPT has a logic "low" level, the inverter IV945 may invert the output signal of the buffer switch SW945 to output an inverted buffered signal of the output signal of the switch SW 945. If the option signal OPT has a logic "high" level, the inverter IV946 may invert the output signal of the buffer switch SW946 to output an inverted buffered signal of the output signal of the switch SW 946. The inverter 963 may invert the output signal of the buffer inverter IV945 or the inverter IV946 to output the inverted buffered signal of the output signal of the inverter IV945 or the inverter IV946 as the eleventh mode data DC _ WRX <11 >. In one embodiment, the switch SW945 may be configured to output the first pipe data PD <1>, the switch SW946 may be configured to output the third pipe data PD <3>, and the option signal OPT may be set to have a logic "high" level. Accordingly, the eleventh mode data selection circuit 923 may output the third pipe data PD <3> as eleventh mode data DC _ WRX <11 >.

The twelfth mode data selecting circuit 924 may include switches SW947 and SW948 and inverters IV947, IV948 and IV 964. The switch SW947 may selectively output the second pipe data PD <2> or the first pipe data PD <1 >. The switch SW948 may selectively output the fourth pipe data PD <4> or the third pipe data PD <3 >. If the option signal OPT has a logic "low" level, the inverter IV947 may invert the output signal of the buffer switch SW947 to output an inverted buffer signal of the output signal of the switch SW 947. If the option signal OPT has a logic "high" level, the inverter IV948 may invert the output signal of the buffer switch SW948 to output an inverted buffer signal of the output signal of the switch SW 948. The inverter 964 may invert the output signal of the buffer inverter IV947 or the inverter IV948 to output the inverted buffer signal of the output signal of the inverter IV947 or the inverter IV948 as the fifteenth mode data DC _ WRX <15 >. In one embodiment, the switch SW947 may be configured to output the first pipe data PD <1>, the switch SW948 may be configured to output the third pipe data PD <3>, and the option signal OPT may be set to have a logic "high" level. Accordingly, the twelfth mode data selection circuit 924 may output the third pipe data PD <3> as fifteenth mode data DC _ WRX <15 >.

The thirteenth mode data selection circuit 925 may include switches SW951 and SW952, and inverters IV951, IV952, and IV 965. The switch SW951 may selectively output the fourth pipe data PD <4> or the third pipe data PD <3 >. The switch SW952 may selectively output the second pipe data PD <2> or the first pipe data PD <1 >. If the option signal OPT has a logic "low" level, the inverter IV951 may invert the output signal of the buffer switch SW951 to output an inverted buffer signal of the output signal of the switch SW 951. If the option signal OPT has a logic "high" level, the inverter IV952 may invert the output signal of the buffer switch SW952 to output an inverted buffer signal of the output signal of the switch SW 952. The inverter 965 may invert the output signal of the buffer inverter IV951 or the inverter IV952 to output an inverted buffer signal of the output signal of the inverter IV951 or the inverter IV952 as tenth mode data DC _ WRX <10 >. In one embodiment, the switch SW951 may be configured to output the third pipe data PD <3>, the switch SW952 may be configured to output the second pipe data PD <2>, and the option signal OPT may be set to have a logic "high" level. Accordingly, the thirteenth mode data selection circuit 925 may output the second pipe data PD <2> as tenth mode data DC _ WRX <10 >.

The fourteenth mode data selecting circuit 926 may include switches SW953 and SW954 and inverters IV953, IV954 and IV 966. The switch SW953 may selectively output the fourth pipe data PD <4> or the third pipe data PD <3 >. The switch SW954 may selectively output the second pipe data PD <2> or the first pipe data PD <1 >. If the option signal OPT has a logic "low" level, the inverter IV953 may invert the output signal of the buffer switch SW953 to output an inverted buffer signal of the output signal of the switch SW 953. If the option signal OPT has a logic "high" level, the inverter IV954 may invert the output signal of the buffer switch SW954 to output an inverted buffer signal of the output signal of the switch SW 954. The inverter 966 may invert the output signal of the buffer inverter IV953 or the inverter IV954 to output the inverted buffer signal of the output signal of the inverter IV953 or the inverter IV954 as the fourteenth mode data DC _ WRX <14 >. In one embodiment, the switch SW953 may be configured to output the third pipe data PD <3>, the switch SW954 may be configured to output the second pipe data PD <2>, and the option signal OPT may be set to have a logic "high" level. Accordingly, the fourteenth mode data selection circuit 926 may output the second pipe data PD <2> as fourteenth mode data DC _ WRX <14 >.

The fifteenth mode data selection circuit 927 may include switches SW955 and SW956, and inverters IV955, IV956, and IV 967. The switch SW955 may selectively output the fourth pipe data PD <4> or the third pipe data PD <3 >. The switch SW956 may selectively output the second pipe data PD <2> or the first pipe data PD <1 >. If the option signal OPT has a logic "low" level, the inverter IV955 may invert the output signal of the buffer switch SW955 to output an inverted buffered signal of the output signal of the switch SW 955. If the option signal OPT has a logic "high" level, the inverter IV956 may invert the output signal of the buffer switch SW956 to output an inverted buffered signal of the output signal of the switch SW 956. The inverter 967 may invert the output signal of the buffer inverter IV955 or the inverter IV956 to output the inverted buffer signal of the output signal of the inverter IV955 or the inverter IV956 as the ninth mode data DC _ WRX <9 >. In one embodiment, the switch SW955 may be configured to output the third pipe data PD <3>, the switch SW956 may be configured to output the first pipe data PD <1>, and the option signal OPT may be set to have a logic "high" level. Accordingly, the fifteenth mode data selection circuit 927 may output the first pipe data PD <1> as ninth mode data DC _ WRX <9 >.

The sixteenth mode data selecting circuit 928 may include switches SW957 and SW958 and inverters IV957, IV958, and IV 968. The switch SW957 may selectively output the fourth pipe data PD <4> or the third pipe data PD <3 >. The switch SW958 may selectively output the second pipe data PD <2> or the first pipe data PD <1 >. If the option signal OPT has a logic "low" level, the inverter IV957 may invert the output signal of the buffer switch SW957 to output an inverted buffer signal of the output signal of the switch SW 957. If the option signal OPT has a logic "high" level, the inverter IV958 may invert the output signal of the buffer switch SW958 to output an inverted buffer signal of the output signal of the switch SW 958. The inverter 968 may invert the output signal of the buffer inverter IV957 or the inverter IV958 to output the inverted buffer signal of the output signal of the inverter IV957 or the inverter IV958 as the thirteenth mode data DC _ WRX <13 >. In one embodiment, the switch SW957 may be configured to output the third pipe data PD <3>, the switch SW958 may be configured to output the first pipe data PD <1>, and the option signal OPT may be set to have a logic "high" level. Accordingly, the sixteenth mode data selection circuit 928 may output the first pipe data PD <1> as the thirteenth mode data DC _ WRX <13 >.

Referring to fig. 13 and 14, various logic level combinations of the first to sixteenth mode data DC _ WRX <1:16> generated by the data decoder 64 according to the logic level combinations of the first to fourth pipe data PD <1:4> are illustrated. If the first through fourth pipe data PD <1:4> having various logic level combinations shown in fig. 13 are input to the data decoder 64, the first through sixteenth mode data DC _ WRX <1:16> having various logic level combinations shown in fig. 14 may be generated.

Referring again to fig. 13 and 14, each of the first mode data DC _ WRX <1>, the fifth mode data DC _ WRX <5>, the ninth mode data DC _ WRX <9>, and the thirteenth mode data DC _ WRX <13> may be set to have the same logic level as the first pipe data PD <1 >. Each of the second mode data DC _ WRX <2>, the sixth mode data DC _ WRX <6>, the tenth mode data DC _ WRX <10>, and the fourteenth mode data DC _ WRX <14> may be set to have the same logic level as the second pipe data PD <2 >. Each of the third mode data DC _ WRX <3>, the seventh mode data DC _ WRX <7>, the eleventh mode data DC _ WRX <11>, and the fifteenth mode data DC _ WRX <15> may be set to have the same logic level as the third pipe data PD <3 >. Each of the fourth mode data DC _ WRX <4>, the eighth mode data DC _ WRX <8>, the twelfth mode data DC _ WRX <12>, and the sixteenth mode data DC _ WRX <16> may be set to have the same logic level as the fourth pipe data PD <4 >.

The operation of the semiconductor device 1 will be described below with reference to fig. 15 and 16. In fig. 15 and 16, the operation of the semiconductor device 1 is illustrated with reference to the clock signal CLK.

Referring to fig. 15, the operation of the semiconductor device 1 may be described in connection with an example in which a first command for generating a mode signal CAS _ WRX, first to fourth pattern data DC <1:4> having a first logic level combination "X", and a first write command WR are input to the semiconductor device 1 via first to lth external signals CA <1: L >, and thereafter, a second command for generating a mode signal CAS _ WRX, first to fourth pattern data DC <1:4> having a second logic level combination "Y", and a second write command WR are input to the semiconductor device 1 via first to lth external signals CA <1: L >.

As shown in fig. 15, the mode signal CAS _ WRX and the delayed mode command CASFD may be sequentially generated by a command for generating the mode signal CAS _ WRX, and the mode output control signal WRX _ EN may be enabled to have a logic "high" level in synchronization with a point of time when both the mode signal CAS _ WRX and the delayed mode command CASFD are generated. The write signal EWT may be generated by a write command WR. The delayed mode output control signal WRX _ END may be generated by delaying the mode output control signal WRX _ EN by a delay time set according to the write latency, and the write flag WTTF may be generated by delaying the write signal EWT by a delay time set according to the write latency. The first to sixteenth mode data DC _ WRX <1:16> may be output while the delay mode output control signal WRX _ END is enabled to have a logic "high" level and the write flag WTTF is generated. The first to sixteenth mode data DC _ WRX <1:16> output by the first write command WR may be generated by decoding the first to fourth pattern data DC <1:4> having the first logic level combination "X", and the first to sixteenth mode data DC _ WRX <1:16> output by the second write command WR may be generated by decoding the first to fourth pattern data DC <1:4> having the second logic level combination "Y".

As described above, the semiconductor device 1 according to one embodiment may receive and latch the pattern data DC <1:4> having a predetermined logic level combination before the write command WR is input to the semiconductor device 1, and may receive and latch the pattern data DC <1:4> having another predetermined logic level combination to perform a separate write operation during a period set by the write latency after the write command WR is input to the semiconductor device 1. That is, the semiconductor device 1 can perform a plurality of write operations for various logic level combinations of pattern data.

For example, when the semiconductor device 1 enters a first pattern input mode in which the pattern data DC <1:4> having the first logical combination is input, the latch data generation circuit (13 of fig. 1) may generate the latch data LC <1:4> having the first logical combination from the pattern data DC <1:4> having the first logical combination. In the first pattern input mode, when the first write command WR is input via the external signal CA <1: L >, the column path circuit (15 of fig. 1) may store the latch data LC <1:4> having the first logic combination into the pipe latch (63 of fig. 8) of the column path circuit (15 of fig. 1). The latch data generation circuit (13 in fig. 1) may generate the latch data LC <1:4> having the second logic combination from the pattern data DC <1:4> having the second logic combination when the semiconductor device 1 enters the second pattern input mode in which the pattern data DC <1:4> having the second logic combination is input during a period corresponding to the write latency after the first write command WR is input. The column path circuit (15 of fig. 1) may output the latch data LC <1:4> having the first logic combination stored in the pipe latch (63 of fig. 8) as the first to fourth pipe data (PD <1:4> of fig. 8) based on the first logic combination after the write latency elapses from a time point at which the first write command WR is input. Then, the column path circuit (15 of fig. 1) may decode the first to fourth pipe data (PD <1:4> of fig. 8) based on the first logical combination to generate the pattern data DC _ WRX <1:16> based on the first logical combination. After the latch data LC <1:4> having the second logic combination is generated by the latch data generation circuit (13 of fig. 1), the column path circuit (15 of fig. 1) may store the latch data LC <1:4> having the second logic combination into the pipe latch (63 of fig. 8) of the column path circuit (15 of fig. 1) when the second write command WR is input via the external signal CA <1: L >. After the write latency elapses from the time point at which the second write command WR is input, the column path circuit (15 of fig. 1) may output the latch data LC <1:4> having the second logical combination stored in the pipe latch (63 of fig. 8) as the first to fourth pipe data (PD <1:4> of fig. 8) based on the second logical combination. Then, the column path circuit (15 of fig. 1) may decode the first to fourth pipe data (PD <1:4> of fig. 8) based on the second logical combination to generate the pattern data DC _ WRX <1:16> based on the second logical combination.

Referring to fig. 16, the operation of the semiconductor device 1 can be described in connection with the following example: a command for generating the mode signal CAS _ WRX, the first to fourth pattern data DC <1:4> having the third logic level combination "Z", and the first write command WR are input to the semiconductor device 1 via the first to lth external signals CA <1: L >, and thereafter, after the first write command WR is input, the second write command WR is input to the semiconductor device 1 via the first to lth external signals CA <1: L >.

As shown in fig. 16, the mode signal CAS _ WRX and the delayed mode command CASFD may be sequentially generated by a command for generating the mode signal CAS _ WRX, and the mode output control signal WRX _ EN may be enabled to have a logic "high" level in synchronization with a point of time when both the mode signal CAS _ WRX and the delayed mode command CASFD are generated. The write signal EWT may be generated by a write command WR. The delayed mode output control signal WRX _ END may be generated by delaying the mode output control signal WRX _ EN by a delay time set according to the write latency, and the write flag WTTF may be generated by delaying the write signal EWT by a delay time set according to the write latency. The first to sixteenth mode data DC _ WRX <1:16> may be output while the delay mode output control signal WRX _ END is enabled to have a logic "high" level and the write flag WTTF is generated. The first to sixteenth pattern data DC _ WRX <1:16> output by the first write command WR may be generated by decoding the first to fourth pattern data DC <1:4> having the third logic level combination "Z", and the first to sixteenth pattern data DC _ WRX <1:16> output by the second write command WR may also be generated by decoding the first to fourth pattern data DC <1:4> having the third logic level combination "Z".

As described above, the semiconductor device 1 according to one embodiment may receive and latch the pattern data DC <1:4> having a predetermined logic level combination before the write command WR is input to the semiconductor device 1, and may sequentially receive a plurality of write commands WR after the pattern data DC <1:4> are latched. Therefore, even if any additional pattern data is not received, the semiconductor device 1 can perform a plurality of write operations corresponding to the latched pattern data DC <1:4 >. Therefore, the power consumption of the semiconductor device 1 can be reduced.

For example, when the semiconductor device 1 enters a first pattern input mode in which the pattern data DC <1:4> having a first logical combination is input, the latch data generation circuit (13 of fig. 1) may generate the latch data LC <1:4> having the first logical combination from the pattern data DC <1:4> having the first logical combination. In the first pattern input mode, when the first write command WR is input via the external signal CA <1: L >, the column path circuit (15 of fig. 1) may store the latch data LC <1:4> having the first logic combination into the pipe latch (63 of fig. 8) of the column path circuit (15 of fig. 1). The column path circuit (15 of fig. 1) may output the latch data LC <1:4> having the first logic combination stored in the pipe latch (63 of fig. 8) as the first to fourth pipe data (PD <1:4> of fig. 8) after the write latency elapses from the time point at which the first write command WR is input. Then, the column path circuit (15 of fig. 1) may decode the first to fourth pipe data (PD <1:4> of fig. 8) to generate the mode data DC _ WRX <1:16> based on the first logical combination. When a second write command WR is input via the external signal CA <1: L > during a period corresponding to the write latency after the first write command WR is input, the column path circuit (15 of fig. 1) may store the latch data LC <1:4> having the first logic combination into the pipe latch (63 of fig. 8) of the column path circuit (15 of fig. 1). After the write latency elapses from the time point at which the second write command WR is input, the column path circuit (15 in fig. 1) may output the latch data LC <1:4> having the first logic combination stored in the pipe latch (63 in fig. 8) as the first to fourth pipe data (PD <1:4> in fig. 8). Then, the column path circuit (15 of fig. 1) may decode the first to fourth pipe data (PD <1:4> of fig. 8) to generate the mode data DC _ WRX <1:16> for the second time based on the first logical combination.

The semiconductor device 1 described with reference to fig. 1 may be applied to an electronic system including a memory system, a graphic system, a computing system, a mobile system, and the like. For example, as shown in fig. 17, an electronic system 1000 according to one embodiment may include: data storage circuitry 1001, memory controller 1002, buffer memory 1003, and input/output (I/O) interface 1004.

The data storage circuit 1001 may store data output from the memory controller 1002 or may read the stored data and output it to the memory controller 1002 according to a control signal output from the memory controller 1002. The data storage circuit 1001 may include the semiconductor device 1 shown in fig. 1. Further, the data storage circuit 1001 may include a nonvolatile memory capable of holding data stored therein even when power supply to the nonvolatile memory is interrupted. The nonvolatile memory may be a flash memory such as a nor type flash memory or a nand type flash memory, a phase change random access memory (PRAM), a Resistive Random Access Memory (RRAM), a Spin Transfer Torque Random Access Memory (STTRAM), a Magnetic Random Access Memory (MRAM), or the like.

The memory controller 1002 may receive a command output from an external device (e.g., a host device) via the I/O interface 1004 and may decode the command output from the host device to control an operation for inputting data to the data storage circuit 1001 or the buffer memory 1003 or an operation for outputting data stored in the data storage circuit 1001 or the buffer memory 1003. Although fig. 17 illustrates the memory controller 1002 having a single block, the memory controller 1002 may include one controller for controlling the data storage circuit 1001 and another controller for controlling the buffer memory 1003 composed of a volatile memory.

The buffer memory 1003 may temporarily store data to be processed by the memory controller 1002. That is, the buffer memory 1003 can temporarily store data output from or input to the data storage circuit 1001. The buffer memory 1003 may store data output from the memory controller 1002 according to a control signal. The buffer memory 1003 may read the stored data and output it to the memory controller 1002. The buffer memory 1003 may include a volatile memory such as a Dynamic Random Access Memory (DRAM), a mobile DRAM, or a Static Random Access Memory (SRAM).

The I/O interface 1004 may physically and electrically connect the memory controller 1002 to an external device (i.e., a host). Accordingly, the memory controller 1002 may receive control signals and data provided from an external device (i.e., a host) via the I/O interface 1004 and may output data output from the memory controller 1002 to the external device (i.e., the host) via the I/O interface 1004. That is, electronic system 1000 may communicate with a host via I/O interfaces 1004. The I/O interface 1004 may include any of a variety of interface protocols, such as Universal Serial Bus (USB), Multi-media card (MMC), peripheral component interconnect (PCI-E), Serial Attached SCSI (SAS), Serial AT attachment (SATA), parallel AT attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Device Interface (ESDI), and Integrated Drive Electronics (IDE).

The electronic system 1000 may be used as a secondary storage device for a host or an external storage device. The electronic system 1000 may include: a Solid State Disk (SSD), a USB memory, a Secure Digital (SD) card, a mini secure digital (mSD) card, a mini secure digital (mini SD) card, a Secure Digital High Capacity (SDHC) card, a memory stick card, a Smart Media (SM) card, a multimedia card (MMC), an embedded multimedia card (eMMC), a Compact Flash (CF) card, and the like.

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Semiconductor device with a plurality of transistors

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