Semiconductor memory device and method of operating semiconductor memory device
阅读说明:本技术 半导体存储器设备和半导体存储器设备的操作方法 (Semiconductor memory device and method of operating semiconductor memory device ) 是由 崔训对 金和平 于 2019-07-16 设计创作,主要内容包括:本发明构思涉及一种半导体存储器设备。该半导体存储器设备可以包括:第一缓冲器,被配置为接收第一信号;第二缓冲器,被配置为接收第二信号;检测器,被配置为将由第一缓冲器接收的第一信号的第一相位与由第二缓冲器接收的第二信号的第二相位进行比较并生成检测信号;以及校正器,响应于检测信号被激活或去激活。当校正器响应于检测信号被激活时,校正器可以被配置为校正由第一缓冲器接收的第一信号和由第二缓冲器接收的第二信号。(The present inventive concept relates to a semiconductor memory device. The semiconductor memory device may include: a first buffer configured to receive a first signal; a second buffer configured to receive a second signal; a detector configured to compare a first phase of a first signal received by the first buffer with a second phase of a second signal received by the second buffer and generate a detection signal; and a corrector activated or deactivated in response to the detection signal. When the corrector is activated in response to the detection signal, the corrector may be configured to correct the first signal received by the first buffer and the second signal received by the second buffer.)
1. A semiconductor memory device, comprising:
a memory cell array including memory cells;
an address buffer configured to receive address information on the memory unit from an external device;
a command buffer configured to receive a command for accessing the memory unit from an external device;
a first strobe buffer configured to receive a first signal and a second signal from an external device; and
a first data buffer configured to receive data from an external device in synchronization with the first signal and the second signal,
wherein the first strobe buffer comprises:
a first buffer configured to receive a first signal,
a second buffer configured to receive a second signal,
a detector configured to compare a first phase of the first signal received by the first buffer with a second phase of the second signal received by the second buffer and generate a detection signal, an
A corrector configured to be activated or deactivated in response to the detection signal, and correct the first signal received by the first buffer and the second signal received by the second buffer when activated in response to the detection signal.
2. The semiconductor memory device according to claim 1, wherein the corrector is activated in response to a first phase of the first signal and a second phase of the second signal being different from each other.
3. The semiconductor memory device of claim 1, wherein the corrector is deactivated in response to the first phase of the first signal being the same as the second phase of the second signal.
4. The semiconductor memory device according to claim 1, wherein the detector comprises:
a first logic operator configured to deactivate the corrector in response to both the first phase and the second phase being in a logic high state; and
a second logic operator configured to deactivate the corrector in response to both the first phase and the second phase being in a logic low state.
5. The semiconductor memory device of claim 1, wherein the detector is configured to detect a first phase of the first signal at a first node in the first buffer and a second phase of the second signal at a second node in the second buffer, and
the corrector is configured to: (i) correcting the first phase of the first signal at a third node, the third node being in the first buffer and distinct from the first node; and (ii) correcting the second phase of the second signal at a fourth node, the fourth node being in the second buffer and different from the second node.
6. The semiconductor memory device according to claim 5, wherein the first buffer includes at least one inverter between the first node and the third node, and the second buffer includes at least another inverter between the second node and the fourth node.
7. The semiconductor memory device according to claim 5, wherein the corrector comprises:
a first inverter having a first input connected to the third node in the first buffer and a first output connected to the fourth node in the second buffer; and
a second inverter having a second input connected to the fourth node in the second buffer and a second output connected to the third node in the first buffer.
8. The semiconductor memory device according to claim 5, further comprising:
another corrector connected to the fifth node in the first buffer and the sixth node in the second buffer, the another corrector configured to correct the first signal and the second signal.
9. The semiconductor memory device according to claim 1, further comprising:
a second strobe buffer configured to output the third signal and the fourth signal to an external device; and
a second data buffer configured to output second data to the external device in synchronization with the third signal and the fourth signal.
10. The semiconductor memory device according to claim 1, further comprising:
control logic circuitry configured to activate the first data buffer, the first buffer, and the second buffer in response to the command being a write command.
11. The semiconductor memory device of claim 10, wherein the control logic circuit is further configured to deactivate the first data buffer, the first buffer, the second buffer, and the detector in response to the command not being a write command.
12. The semiconductor memory device according to claim 1, further comprising:
a row decoder configured to select some memory cells from the memory cell array in response to address information; and
a write driver/sense amplifier configured to perform a write or read operation on the memory cell selected by the row decoder.
13. A semiconductor memory device, comprising:
a memory cell array including memory cells;
an address buffer configured to receive address information on the memory unit from an external device;
a command buffer configured to receive a command for accessing the memory unit from an external device;
a control logic circuit configured to activate a first signal in response to receiving a write command for the memory cell array from an external device;
a first gate buffer configured to receive a first gate signal and a second gate signal from an external device, compare a first phase of the first gate signal with a second phase of the second gate signal in response to the first signal being activated, correct the first gate signal and the second gate signal in response to the first phase and the second phase being different from each other, and output the corrected first gate signal and the second gate signal as a third gate signal and a fourth gate signal;
a first data buffer configured to latch a first data signal received from an external device in synchronization with a third strobe signal and a fourth strobe signal in response to a first signal being activated;
a second strobe buffer configured to output a third signal and a fourth signal to an external device in response to receiving a read command for the memory cell array from the external device; and
a second data buffer configured to output the second data signal to the external device in synchronization with the third signal and the fourth signal.
14. The semiconductor memory device according to claim 13, wherein the control logic circuit is further configured to deactivate the first signal in response to receiving another command different from the write command from the external device.
15. The semiconductor memory device of claim 13, wherein the first strobe buffer is further configured to block a current for correcting the first strobe signal and the second strobe signal in response to the first signal being deactivated.
16. The semiconductor memory device of claim 13, wherein the first strobe buffer is further configured to block current for correcting the first strobe signal and the second strobe signal in response to the first signal being activated and the first phase being the same as the second phase.
17. The semiconductor memory device of claim 13, wherein the first strobe buffer comprises:
a first operator configured to output a result of a nor logic between the first strobe signal and the second strobe signal as a first intermediate signal;
a second operator configured to output a result of the nand logic between the first strobe signal and the second strobe signal as a second intermediate signal;
a third operator configured to output a result of the nand logic between the inverted signal of the first intermediate signal and the second intermediate signal as a third intermediate signal; and
a fourth operator configured to output a result of NOR logic between the third intermediate signal and the first signal as the second signal,
the first signal is a low level activation signal, and
the first strobe buffer is configured to activate correction of the first strobe signal and the second strobe signal in response to the second signal being high.
18. The semiconductor memory device of claim 13, wherein the control logic circuit is further configured to activate or deactivate a second signal,
the first strobe buffer is configured to correct the first strobe signal and the second strobe signal depending on the first signal, the first phase and the second phase in response to the second signal being activated, an
The first strobe buffer is further configured to correct the first strobe signal and the second strobe signal independently of the first phase and the second phase using the first signal in response to the second signal being activated.
19. A method of operating a semiconductor memory device, comprising:
receiving a write command at a command buffer of a semiconductor memory device;
receiving address information associated with a write command at an address buffer of a semiconductor memory device;
receiving a first strobe signal and a second strobe signal;
correcting the first strobe signal and the second strobe signal in response to a first phase of the first strobe signal being different from a second phase of the second strobe signal after receiving the write command;
receiving data at a data buffer of the semiconductor memory device in synchronization with the first strobe signal and the second strobe signal; and
the received data is written in the memory cells of the semiconductor memory device corresponding to the address information.
20. The method of claim 19, further comprising:
stopping correction of the first and second strobe signals in response to the first phase being the same as the second phase after receiving the write command; and
in response to receiving another command different from the write command, the correction of the first strobe signal and the second strobe signal is stopped regardless of whether the first phase is different from the second phase.
Technical Field
The present inventive concept relates to a semiconductor circuit, and in particular, to a semiconductor memory device configured to correct a strobe signal (strobe), and/or a method of operating the same.
Background
A semiconductor device (e.g., a semiconductor memory device) is configured to perform data communication with an external device. The semiconductor memory device may store data received from an external device and may transmit the stored data to the external device. A strobe signal (e.g., a data strobe signal) may be used for data communication between a semiconductor device (e.g., a semiconductor memory device) and an external device.
When data is transferred from an external device to the semiconductor memory device, the data strobe signal may be transferred to the semiconductor memory device together with the data. The data strobe signal may transition between a high logic level and a low logic level, and the transition of the data strobe signal may be used to inform the semiconductor memory device of the timing of latching each bit of data.
When data is transferred from the semiconductor memory device to an external device, the data strobe signal may be transferred to the external device together with the data. The data strobe signal may transition between a high logic level and a low logic level, and the transition of the data strobe signal may be used to inform an external device of the timing at which each bit of data is latched.
As the transmission speed of data increases, a data strobe signal is applied to a variety of semiconductor devices or semiconductor memory devices, for example, to improve the accuracy of data transmission. In order to further improve the accuracy of data transmission, many studies have been made to improve the transmission accuracy of the data strobe signal. In addition, methods for reducing power consumed to improve transmission accuracy of the data strobe signal are being studied.
Disclosure of Invention
Some example embodiments of the inventive concepts provide a semiconductor memory device configured to correct a data strobe signal at a reduced power, thereby improving accuracy of data transmission at the reduced power, and a method of operating the semiconductor memory device.
According to some example embodiments of the inventive concepts, a semiconductor memory device may include: a memory cell array including memory cells; an address buffer configured to receive address information on the memory unit from an external device; a command buffer configured to receive a command for accessing the memory unit from an external device; a first strobe buffer configured to receive a first signal and a second signal from an external device; and a first data buffer configured to receive data from the external device in synchronization with the first signal and the second signal. The strobe buffer includes: a first buffer configured to receive a first signal; a second buffer configured to receive a second signal; a detector configured to compare a first phase of the first signal received by the first buffer with a second phase of the second signal received by the second buffer and generate a detection signal; and a corrector configured to be activated or deactivated in response to the detection signal, and correct the first signal received by the first buffer and the second signal received by the second buffer when activated in response to the detection signal.
According to some example embodiments of the inventive concepts, a semiconductor memory device may include: a memory cell array including memory cells; an address buffer configured to receive address information on the memory unit from an external device; a command buffer configured to receive a command for accessing the memory unit from an external device; a control logic circuit configured to activate a first signal in response to receiving a write command for the memory cell array from an external device; a first gate buffer configured to receive the first gate signal and the second gate signal from the external device, compare a first phase of the first gate signal with a second phase of the second gate signal in response to the first signal being activated, correct the first gate signal and the second gate signal in response to the first phase and the second phase being different from each other, and output the corrected first gate signal and the second gate signal as a third gate signal and a fourth gate signal. The memory device further includes: a first data buffer configured to latch a first data signal received from an external device in synchronization with a third strobe signal and a fourth strobe signal in response to a first signal being activated; a second strobe buffer configured to output a third signal and a fourth signal to an external device in response to receiving a read command for the memory cell array from the external device; and a second data buffer configured to output the second data signal to the external device in synchronization with the third signal and the fourth signal.
According to some example embodiments of the inventive concepts, a method of operating a semiconductor memory device may include: receiving a write command at a command buffer of a semiconductor memory device; receiving address information associated with a write command at an address buffer of a semiconductor memory device; receiving a first strobe signal and a second strobe signal; correcting the first strobe signal and the second strobe signal in response to a first phase of the first strobe signal being different from a second phase of the second strobe signal after receiving the write command; receiving data at a data buffer of the semiconductor memory device in synchronization with the first strobe signal and the second strobe signal; and writing the received data in a memory cell of the semiconductor memory device corresponding to the address information.
Drawings
Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The drawings represent non-limiting example embodiments as described herein.
Fig. 1 is a block diagram illustrating a semiconductor memory device according to some example embodiments of the inventive concepts.
Fig. 2 is a flowchart illustrating a method of operating a semiconductor memory apparatus according to some example embodiments of the inventive concepts.
Fig. 3 is a block diagram illustrating a first strobe buffer according to some example embodiments of the inventive concepts.
Fig. 4 illustrates a detector according to some example embodiments of the inventive concept.
Fig. 5 shows a first example of the operation of the detector of fig. 4.
Fig. 6 shows a second example of the operation of the detector of fig. 4.
Fig. 7 shows a third example of the operation of the detector of fig. 4.
Fig. 8 shows a fourth example of the operation of the detector of fig. 4.
Fig. 9 illustrates a detector according to some example embodiments of the inventive concepts.
Fig. 10 illustrates a corrector according to some example embodiments of the inventive concept.
Fig. 11 illustrates a first strobe buffer according to some example embodiments of the inventive concepts.
It should be noted that these drawings are intended to illustrate the general features of methods, structures and/or materials used in certain example embodiments, and to supplement the written description provided below. However, the drawings are not to scale and may not accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the scope of values or properties encompassed by example embodiments. For example, the relative thicknesses and positioning of particles, layers, regions and/or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numbers in the various figures is intended to indicate the presence of similar or identical elements or features.
Detailed Description
Example embodiments of the present inventive concept will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.
Fig. 1 is a block diagram illustrating a semiconductor memory device 10 according to some example embodiments of the inventive concepts. Referring to fig. 1, a semiconductor memory device 10 may include a memory cell array 11, a row decoder 12, a write driver/sense amplifier 13, a control logic circuit 14, an address buffer 15, a command buffer 16, a first gate buffer 17, a first data buffer 18, a second gate buffer 19, and/or a second data buffer 20.
The memory cell array 11 may include a plurality of memory cells. The memory cells may include various memory cells such as Dynamic Random Access Memory (DRAM) cells, Static Random Access Memory (SRAM) cells, phase change memory cells, magnetic memory cells, resistive memory cells, and/or FLASH memory (FLASH) memory cells. The memory cells may be connected to the row decoder 12 through word lines WL and may be connected to write drivers/sense amplifiers 13 through bit lines BL.
The row decoder 12 may receive a row address RA from an address buffer 15. The row decoder 12 may decode the row address RA and may select the word line WL based on the result of the decoding. The row decoder 12 may apply a first voltage to selected ones of the word lines WL, and may apply a second voltage different from the first voltage to unselected word lines.
The write driver/sense amplifier 13 may receive a column address CA from the address buffer 15. The write driver/sense amplifier 13 may decode the column address CA, and may select the bit line BL based on the result of the decoding. The write driver/sense amplifier 13 may apply a third voltage to selected ones of the bit lines BL, and may apply a fourth voltage different from the third voltage to unselected bit lines. Although fig. 1 shows the write driver/sense amplifier 13 as one circuit, the inventive concept is not so limited. For example, the write driver/sense amplifier 13 may be included in one circuit, or may be a separate circuit, e.g., the write driver is separate from the sense amplifier.
Control logic circuit 14 may receive commands CMD from command buffer 16. The control logic circuit 14 may control the row decoder 12 and the write driver/sense amplifier 13 according to the command CMD. For example, the control logic circuit 14 may control the row decoder 12 and the write driver/sense amplifier 13 to perform a write operation or a read operation on a selected memory cell of the memory cells of the memory cell array 11. The control logic circuit 14 may control the row decoder 12 and the write driver/sense amplifier 13 to perform an erase operation on the selected memory cell.
The control logic circuit 14 may control the first signal/
When the command CMD is a read command, the control logic circuit 14 may activate the second signal/EN 2 (e.g., the signal may be set to a low level). When command CMD is another command (i.e., not a read command), control logic circuit 14 may deactivate second signal/EN 2 (e.g., may set the signal to a high level).
The control logic circuit 14 may control the detection control signal DET _ ON. For example, when the correction operations ON the first and second data strobe signals DQS1 and DQS2 are activated, the control logic circuit 14 may activate the detection control signal DET _ ON (e.g., to a high level). When the correction operation is deactivated, the control logic circuit 14 may deactivate the detection control signal DET _ ON (e.g., to a low level).
The control logic circuit 14 can control the detection control signal DET _ ON at various timings. For example, when power is supplied to the semiconductor memory device 10, a decision may be made whether to activate the correction operation. When power is supplied, a decision whether to activate the correction operation may be made based on the setting of a mode register (not shown). The mode register may be included as part of the semiconductor memory device 10, or alternatively may not be part of the semiconductor device 10, and may be external to the semiconductor device 10. While maintaining the power supply, the semiconductor memory device 10 may maintain the detection control signal DET _ ON in an activated or deactivated state (active or inactive state).
As another example, the control logic circuit 14 may activate the detection control signal DET _ ON when a write operation is performed. For example, the detection control signal DET _ ON may have an activation period (activationperiod) similar to the first signal/
The address buffer 15 may receive an address ADDR from an external device (e.g., a controller of the semiconductor memory device 10). The address buffer 15 may transfer a row address RA of the received address ADDR to the row decoder 12, and may transfer a column address CA to the write driver/sense amplifier 13. The command buffer 16 may transfer a command CMD received from an external device (e.g., a controller) to the control logic circuit 14.
The first strobe buffer 17 may receive the first data strobe signal DQS1 and the second data strobe signal DQS2 from an external device (e.g., a controller). For example, after receiving a write command as the command CMD, each of the first and second data strobe signals DQS1 and DQS2 may be toggled between a high level and a low level (toggle). The first data strobe signal DQS1 and the second data strobe signal DQS2 may be complementary signals, such as signals that are "180 degrees out of phase" with respect to each other.
The first strobe buffer 17 may rearrange the switching timings of the first and second data strobe signals DQS1 and DQS2, and may output the rearranged signals as the third and fourth data strobe signals DQS3 and DQS 4. The first strobe buffer 17 may include a
The
When the phase of the first data strobe signal DQS1 is the same as the phase of the second data strobe signal DQS2 (e.g., the first data strobe signal DQS1 and the second data strobe signal DQS2 do not toggle), the
The
If the switching timings of the first and second data strobe signals DQS1 and DQS2 are not consistent with each other, skew may occur, and in this case, the
In some example embodiments, the first strobe buffer 17 may perform the correction operation only when the first and second data strobe signals DQS1 and DQS2 toggle, and may stop the correction operation when the first and second data strobe signals DQS1 and DQS2 do not toggle. When the correction operation is stopped, the current flowing in the
When the first signal/
For example, the first data buffer 18 may store the level of the first data signal DQ1 at the timing at which the third data strobe signal DQS3 and the fourth data strobe signal DQS4 toggle. The first data buffer 18 may deserialize (deserialize) the level DQ1L of the stored first data signal DQ1, and may transfer the deserialized result to the write driver/sense amplifier 13.
When the second signal/EN 2 is activated, the second strobe buffer 19 may be activated. The second strobe buffer 19 may output the fifth data strobe signal DQS5 and the sixth data strobe signal DQS6 to an external device (e.g., a controller). For example, the second strobe buffer 19 may receive a clock signal from an external device and may generate the fifth data strobe signal DQS5 and the sixth data strobe signal DQS6 from the clock signal.
When the second signal/EN 2 is activated, the second data buffer 20 may be activated. The second data buffer 20 may receive a level DQ2L of a second data signal DQ2 from the write driver/sense amplifier 13. The second data buffer 20 may serialize (serialize) the level of the second data signal DQ2 and output the second data signal DQ2 in synchronization with the fifth data strobe signal DQs5 and the sixth data strobe signal DQs 6.
For example, the first data strobe signal DQS1 and the fifth data strobe signal DQS5 may communicate with an external device (e.g., a controller) through the same signal line. The second data strobe signal DQS2 and the sixth data strobe signal DQS6 may communicate with an external device (e.g., a controller) through the same signal line. The first data signal DQ1 and the second data signal DQ2 may communicate with an external device (e.g., a controller) through the same signal line.
Fig. 2 is a flowchart illustrating a method of operating the semiconductor memory apparatus 10 according to some example embodiments of the inventive concepts. Referring to fig. 1 and 2, in step S110, the
Upon detecting a difference between the first data strobe signal DQS1 and the second data strobe signal DQS2, the
In step S130, the
Fig. 3 is a block diagram illustrating a
Referring to fig. 1 and 3, the
The
The output of a specific one (e.g., 117) of the
The
The
The output of a specific one (e.g., 127) of the
The
For example, the
When the first signal/
As shown in fig. 3, the
The
For example, the
As shown in fig. 3, the
Fig. 4 illustrates a
The
The
The fifth sub operator 132_5 may perform a NAND logic (NAND) operation on the output of the
The
When the detection control signal DET _ ON is activated (e.g., to a high level), the
The
The tenth sub-operator 135_5 may perform a NAND logic (NAND) operation on the output of the
The
If the first signal/
Fig. 5 shows a first example of the operation of the
The detection control signal DET _ ON may be fixed to an active state (e.g., a high level). However, as described above, the detection control signal DET _ ON may be activated depending ON the write command. If a write command WR is received as the command CMD, the first signal/
Even if the first signal/
The
When the output of the
The
The
When the output of the
As shown in fig. 5, the first and
Fig. 6 shows a second example of the operation of the
The detection control signal DET _ ON may be fixed to an active state (e.g., a high level). However, as described above, the detection control signal DET _ ON may be activated depending ON the write command. If a write command WR is received as the command CMD, the first signal/
Even if the first signal/
The
When the output of the
The
The
When the output of the
As shown in fig. 6, the third, fourth, and
As described with reference to fig. 5 and 6, if no other command is received after the write command WR is received, the first signal/
Therefore, even if the first signal/
Fig. 7 shows a third example of the operation of the
Unlike as described with reference to fig. 4, the detection control signal DET _ ON may be fixed to a deactivated state (e.g., a low level). If the detection control signal DET _ ON is in a deactivated state, the
Therefore, the
When the first signal/
Fig. 8 illustrates a fourth example of the operation of the
Unlike as described with reference to fig. 6, the detection control signal DET _ ON may be fixed to a deactivated state (e.g., a low level). If the detection control signal DET _ ON is in a deactivated state, the
Therefore, the
When the first signal/
Fig. 9 illustrates a
When compared to the
Fig. 10 illustrates a
The first transistor T1 and the second transistor T2 may be PMOS transistors. An inverted signal/EN 3 of the third signal EN3 may be transmitted to the gate of the first transistor T1. The third intermediate signal SI3 may be transmitted to the gate of the second transistor T2. The third transistor T3 and the fourth transistor T4 may be NMOS transistors. The third intermediate signal SI3 may be transmitted to the gate of the third transistor T3. The third signal EN3 may be transmitted to the gate of the fourth transistor T4.
The second correcting
The fifth transistor T5 and the sixth transistor T6 may be PMOS transistors. An inverted signal/EN 3 of the third signal EN3 may be transmitted to the gate of the fifth transistor T5. The fourth intermediate signal SI4 may be transmitted to the gate of the sixth transistor T6. The seventh transistor T7 and the eighth transistor T8 may be NMOS transistors. The fourth intermediate signal SI4 may be transmitted to the gate of the seventh transistor T7. The third signal EN3 may be transmitted to the gate of the eighth transistor T8.
The third intermediate signal SI3 may be transmitted to the first correcting
When the duty ratio of the third intermediate signal SI3 does not coincide with the duty ratio of the fourth intermediate signal SI4, there may be a period in which both the third intermediate signal SI3 and the fourth intermediate signal SI4 have a high level or a low level. The
Likewise, when skew occurs in the third intermediate signal SI3 and the fourth intermediate signal SI4, there may be a period in which both the third intermediate signal SI3 and the fourth intermediate signal SI4 have a high level or a low level. The
If the third intermediate signal SI3 and the fourth intermediate signal SI4 pass through subsequent inverters (e.g., 116 and 126) (e.g., see fig. 3), the timing at which the third intermediate signal SI3 and the fourth intermediate signal SI4 switch may change. Accordingly, the
As shown in fig. 10, if the third signal EN3 is deactivated (e.g., to a low level), it is possible to inhibit, e.g., prevent, a current from flowing through the
Fig. 11 illustrates a
The
For example, the
The
As described with reference to fig. 11, one detector may be used to activate or deactivate two or more correctors. As the number of correctors increases, power consumption in the
In the foregoing embodiments, the inventive concept has been described with reference to the example of the semiconductor memory device 10. However, the inventive concept can be applied to any semiconductor device that receives a signal (particularly, a strobe signal).
In the above embodiments, some components are referred to by using the term "block". The block may be implemented in hardware configured to execute machine-readable instructions comprising software, such as Integrated Circuits (ICs), application specific ICs (asics), Field Programmable Gate Arrays (FPGAs), and Complex Programmable Logic Devices (CPLDs). Further, the block may include a circuit or Intellectual Property (IP) implemented with semiconductor devices in the IC.
According to some example embodiments of the inventive concepts, the data strobe signal may be corrected only when the data strobe signal transitions to phases different from each other. When the data strobe signals are fixed to the same phase, correction of the data strobe signals is deactivated, and thus, a semiconductor memory device correcting the data strobe signals with reduced power and a method of operating the semiconductor memory device can be provided.
Although exemplary embodiments of the inventive concept have been particularly shown and described, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.
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