Semiconductor circuit and method of operating the same
阅读说明:本技术 半导体电路及其操作方法 (Semiconductor circuit and method of operating the same ) 是由 林榆瑄 王超鸿 于 2018-10-17 设计创作,主要内容包括:本发明公开了一种半导体电路及其操作方法。半导体电路的操作方法包括以下步骤:在第一时间操作存储器电路以获得第一存储器状态信号S1;第一时间之后的第二时间操作存储器电路以获得第二存储器状态信号S2;计算第一存储器状态信号S1和第二存储器状态信号S2的差异以获得状态差异信号SD;计算以得到未补偿输出数据信号OD,未补偿输出数据信号OD相关于输入数据信号ID和第二存储器状态信号S2;以及对状态差异信号SD与未补偿输出数据信号OD进行计算以获得补偿输出数据信号OD’。(The invention discloses a semiconductor circuit and an operating method thereof. The method of operating a semiconductor circuit comprises the steps of: operating the memory circuit at a first time to obtain a first memory state signal S1; operating the memory circuit at a second time after the first time to obtain a second memory state signal S2; calculating a difference of the first memory state signal S1 and the second memory state signal S2 to obtain a state difference signal SD; calculating to obtain an uncompensated output data signal OD, the uncompensated output data signal OD being related to the input data signal ID and the second memory state signal S2; and calculating the state difference signal SD and the uncompensated output data signal OD to obtain a compensated output data signal OD'.)
1. A method of operating a semiconductor circuit, comprising:
operating a memory circuit at a first time to obtain a first memory state signal S1;
operating the memory circuit at a second time after the first time to obtain a second memory state signal S2;
calculating a difference between the first memory state signal S1 and the second memory state signal S2 to obtain a state difference signal SD;
calculating to obtain an uncompensated output data signal OD related to an input data signal ID and the second memory status signal S2; and
the state difference signal SD and the uncompensated output data signal OD are calculated to obtain a compensated output data signal OD'.
2. The method of operating the semiconductor circuit of claim 1, comprising:
programming a reference memory array at the first time to obtain the first memory state signal; and
the first memory state signal is stored in a memory device.
3. The method of claim 2, wherein the reference Memory array comprises a resistive random access Memory (ReRAM), a phase change Memory (phase change Memory), or a bridge-type Memory (bridge-access Memory), and the Memory device comprises a flash Memory (flash Memory), a Read-Only Memory (ROM), or a one-time-programmable (OTP) Memory, wherein the reference Memory array and the main Memory array have the same Memory structure.
4. The method of operating the semiconductor circuit of claim 1, comprising:
reading cell state signals of a plurality of memory cells of a reference memory array at the second time; and
the memory cell state signals are calculated to obtain the second memory state signal S2.
5. The method of claim 4, wherein the second memory state signal S2 is less than the largest of the memory cell state signals and greater than the smallest of the memory cell state signals.
6. The method of claim 4, wherein the second memory state signal S2 is an arithmetic mean (mean), median (mean), or mode of the memory cell state signals.
7. The method of operating the semiconductor circuit of claim 1, wherein:
the first and second memory state signals S1 and S2 have a first electrical measurement unit,
the input data signal ID has a second electrical property measurement unit,
the uncompensated output data signal OD and the compensated output data signal OD' have a third electrical measurement unit,
the first electrical property measurement unit, the second electrical property measurement unit and the third electrical property measurement unit are different electrical property measurement units and accord with ohm law with each other.
8. A semiconductor circuit, comprising:
a main memory array;
a reference memory array;
a memory device for storing a first memory state signal S1 obtained by operating the reference memory array at a first time; and
a processing circuit for reading a second memory state signal S2 of the reference memory array at a second time after the first time and for calculating an uncompensated output data signal OD associated with an input data signal ID and another second memory state signal S2 of the primary memory array at the second time, the memory device being electrically coupled to the processing circuit.
9. The semiconductor circuit of claim 8, wherein the reference Memory array and the main Memory array comprise resistive-random-access Memory (ReRAM), phase-change Memory (phase-change Memory), or bridge-type Memory (bridge-access Memory), and the Memory device comprises flash Memory (flash Memory), Read-Only Memory (ROM), or one-time-programmable (OTP) Memory.
10. The semiconductor circuit of claim 8, wherein the reference memory array and the main memory array have the same memory structure.
Technical Field
The present invention relates to a semiconductor circuit and an operating method thereof, and more particularly, to a neural network and an operating method thereof, which belong to the technical field of integrated circuits.
Background
With the development of software technology, the deep learning of the neural network defined by software greatly improves the artificial intelligence capability, such as image recognition, voice recognition, natural language understanding and decision-making, through a universal learning process. The appearance of a Hardware Neural Network (HNN) further reduces the Hardware size, cost and power consumption of deep learning systems. HNNs, which are composed of a network of neurons interconnected by synapses, may have thousands of synapses, where the weights (weights) of the synapses (synapses) may be optimized during training.
Disclosure of Invention
The invention relates to a semiconductor circuit and an operation method thereof.
According to an aspect of the present invention, there is provided a method of operating a semiconductor circuit, comprising the steps of: operating the memory circuit at a first time to obtain a first memory state signal S1; operating the memory circuit at a second time after the first time to obtain a second memory state signal S2; calculating a difference of the first memory state signal S1 and the second memory state signal S2 to obtain a state difference signal SD; calculating to obtain an uncompensated output data signal OD, the uncompensated output data signal OD being related to the input data signal ID and the second memory state signal S2; and calculating the state difference signal SD and the uncompensated output data signal OD to obtain a compensated output data signal OD'.
According to another aspect of the invention, a semiconductor circuit is provided that includes a main memory array, a reference memory array, a memory device, and a processing circuit. The memory device is configured to store a first memory state signal S1 obtained by operating the reference memory array at a first time. The processing circuit is used for reading a second memory status signal S2 of the reference memory array at a second time after the first time, and is used for calculating an uncompensated output data signal OD. The uncompensated output data signal OD is related to the input data signal ID and to another second memory state signal S2 for the primary memory array at a second time. The memory device is electrically coupled to the processing circuit.
For a better understanding of the above and other aspects of the invention, reference should be made to the following detailed description of the embodiments, taken in conjunction with the accompanying drawings, in which:
drawings
Fig. 1 illustrates a semiconductor circuit according to an embodiment concept.
Fig. 2 illustrates a method of operating a semiconductor circuit according to an embodiment concept.
Fig. 3 and 4 illustrate a method of operating a semiconductor circuit according to an embodiment concept.
Fig. 5 retains conductance range curve results of a test at 150 ℃ using a semiconductor circuit of compensated output data according to an embodiment concept.
Fig. 6 is the results of a 150 ℃ retention test using a comparative example with uncompensated output data.
Fig. 7 illustrates a method of operating a semiconductor circuit according to another embodiment concept.
Fig. 8 shows curve results of a 150 ℃ retention test for a semiconductor circuit using compensated output data according to an embodiment concept.
Fig. 9 is the results of a 150 ℃ retention test using a comparative example with uncompensated output data.
[ notation ] to show
102: a processing circuit;
106: a memory device;
108: a primary memory array;
110: a reference memory array;
122: a data input;
124: a data output terminal;
s552, S554, S556, S558, S560: and (5) carrying out the following steps.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.
Fig. 1 illustrates a semiconductor circuit according to an embodiment concept. Fig. 2 illustrates a method of operating a semiconductor circuit according to an embodiment concept.
Referring to fig. 1, the semiconductor circuit includes a memory circuit and a
Referring to fig. 1 and fig. 2, the method for operating the semiconductor circuit includes step S552: the memory circuit is operated at a first time t1 to obtain a first memory state signal S1. In one embodiment, the
A first memory state signal S1 (e.g., conductance G) from the
In one embodiment, the
In one embodiment,
Then, step S554 is performed: the memory circuit is operated at a second time t2 after the first time t1 to obtain a second memory state signal S2.
A second memory state signal S2 (e.g., conductance G) from the
In one embodiment, the
In one embodiment, the
Then, step S556 is performed: the difference of the first memory state signal S1 and the second memory state signal S2 is calculated to obtain a state difference signal SD. The
Step S558 is performed after step S552: to obtain the uncompensated output data signal OD. The uncompensated output data signal OD is related to the input data signal ID at the
Step S560: the state difference signal SD and the uncompensated output data signal OD are calculated to obtain a compensated output data signal OD'. In one embodiment, the
The first and second memory state signals S1 and S2 have a first electrical measurement unit, the input data signal ID has a second electrical measurement unit, the uncompensated output data signal OD and the compensated output data signal OD 'have a third electrical measurement unit, and the first, second and third electrical measurement units are different electrical measurement units and conform to ohm' S law. In one embodiment, the first electrical property measurement unit is a conductance (electrical conductivity) unit, the second electrical property measurement unit is a voltage unit, and the third electrical property measurement unit is a current unit.
In one embodiment, SD is S2-S1, OD is ID S2, and OD is OD- (SD).
Fig. 3 and 4 illustrate a method of operating a semiconductor circuit according to an embodiment concept. Referring to FIG. 3, a plurality of input data V1, V2, V3 … (i.e., voltage V)iI 1, 2, 3 …) are multiplied by the weight G stored in the memory cell of the primary memory array, respectively1、G2、G3… (i.e. conductance G)iI 1, 2, 3 …, the conductance at the first time t1 may be denoted as Gi,t1The conductance at the second time t1 may be labeled Gi,t2) Each product of (1)1、I2、I3(i.e. current I)iI1, 2, 3 …, the current at the first time t1 may be denoted as Ii,t1The current at the second time t2 can be labeled as Ii,t2) Is the sum of the output data Iout=∑Vi*Gi. Referring to FIG. 4, in this embodiment, the memory state G stored from the memory cells of the
FIG. 7 illustrates a method of operating a semiconductor circuit according to another concept of an embodiment in which two reference memory states are taken between a maximum memory state and a minimum memory state stored by memory cells of a
While the present invention has been described with reference to the above embodiments, it is not intended to be limited thereto. Those skilled in the art to which the invention pertains will readily appreciate that various modifications and adaptations can be made without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention is defined by the claims of the application.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
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