In-memory arithmetic device for neural network
阅读说明:本技术 用于类神经网路的存储器内运算装置 (In-memory arithmetic device for neural network ) 是由 林榆瑄 王超鸿 李明修 于 2019-02-27 设计创作,主要内容包括:本发明公开了一种用于类神经网路的存储器内运算装置,该存储器内运算装置包括多个突触层。此些突触层包括一第一类型突触层及一第二类型突触层。第一类型突触层包括多个第一类型存储单元,第二类型的突触层包括多个第二类型存储单元。第一类型存储单元相异于第二类型存储单元。第一类型存储单元和第二类型存储单元可以是不同类型的存储器,具有不同的结构、不同的存储器材料及/或不同的读/写算法,任一其中之一可导致稳定性或数据储存准确性的变化。(The invention discloses an in-memory operation device for a neural network, which comprises a plurality of synapse layers. The synapse layers comprise a first type synapse layer and a second type synapse layer. The first type of synapse layer comprises a plurality of first type memory cells and the second type of synapse layer comprises a plurality of second type memory cells. The first type of memory cell is different from the second type of memory cell. The first type of memory cells and the second type of memory cells may be different types of memory, having different structures, different memory materials, and/or different read/write algorithms, either of which may result in variations in stability or data storage accuracy.)
1. An apparatus, comprising:
the memory device comprises a plurality of synapse layers, wherein at least one of the synapse layers is a first type synapse layer comprising a plurality of first type memory cells, at least one of the synapse layers is a second type synapse layer comprising a plurality of second type memory cells, and the first type memory cells are different from the second type memory cells.
2. The apparatus of claim 1, comprising a peripheral circuit that performs write operations in the first type of memory cells with a first write algorithm, the peripheral circuit performing write operations in the second type of memory cells with a second write algorithm, the first write algorithm being different from the second write algorithm.
3. The apparatus of claim 1, wherein the first type of memory cells are read-only memory cells and the second type of memory cells are reprogrammable memory cells.
4. The apparatus of claim 1, wherein the first type of memory cells are volatile memory cells and the second type of memory cells are non-volatile memory cells.
5. The apparatus according to claim 1, wherein at least one of the first type of synapse layers and the second type of synapse layers comprises:
a memory cell array having M rows and N columns of memory cells, each memory cell in the memory cell array storing a weight factor;
a first set of access lines coupled to respective columns of the memory cells; and
a second set of access lines is coupled to the columns of the memory cells.
6. The apparatus of claim 5, wherein signals representing inputs are recorded on first access lines of the first set of access lines; a current sensed on a particular one of the second set of access lines is a product of the input and the weighting factors stored in a particular row of memory cells coupled to the particular one of the second set of access lines.
7. The apparatus of claim 5, wherein a product of at least one of the first type of synapse layers and the second type of synapse layers is an input to the other of the first type of synapse layers and the second type of synapse layers.
8. A method of manufacturing a device, comprising:
forming a plurality of synapse layers, at least one of the synapse layers being a first type synapse layer comprising a plurality of first type memory cells, at least one of the synapse layers being a second type synapse layer comprising a plurality of second type memory cells, the first type memory cells being different from the second type memory cells.
9. The method of claim 8, further comprising a peripheral circuit performing write operations with a first write algorithm on the first type of memory cells and a second write algorithm on the second type of memory cells, the first write algorithm being different from the second write algorithm.
10. The method of claim 9, wherein the peripheral circuit further performs read operations in the first type of memory cells with a first read algorithm, and the peripheral circuit further performs read operations in the second type of memory cells with a second read algorithm, the first read algorithm being different from the second read algorithm.
Technical Field
The present invention relates to an in-memory computing device (in-memory computing device), and more particularly, to an in-memory computing device including a plurality of types of memory cells.
Background
Neural network (neural network) is an information processing method inspired by the way that biological nervous system processes information. With the development of large training data sets and complex learning algorithms, neural networks have facilitated significant advances in many areas such as computer vision, speech recognition, and natural language processing.
The basic computational unit in a neural network is a neuron (neuron). Neurons receive input from other neurons or from outside to compute output. Fig. 1 illustrates a
in the above-described sum-of-products, each product term is the product of a variable input Xi and a weight Wi. The variable inputs Xi to which the weights Wi correspond may be different. Similarly, the outputs of other neurons in the hidden layer can also be calculated. The outputs of two neurons in the
The neural network is used to learn the information most representative of the large data set. Hidden layers near the input layer learn higher-order generic patterns, while hidden layers near the output layer learn more data specific patterns. Training is the stage where the neural network learns from training data. During training, connections of the synapse layer are assigned weights depending on the results of the training period. Inference (inference) is the phase of reasoning about/predicting input data by predicting and generating output data. The inference accuracy of the neural network is the ratio of correctly predicting or inferring the input data.
In-memory computing (In-memory computing) is a method by which memory cells within an In-memory computing device may be used for data processing and memory storage. The neural network may be implemented in an in-memory computing device. The weights for the product-sum function may be stored in memory locations of the in-memory arithmetic device. The product-sum function may be a circuit operation in an in-memory arithmetic device that implements this function through an array of memory cells.
Variations in memory cells, erroneous read and write operations, and other non-ideal device characteristics may cause the memory cell weights stored in the in-memory computing device to fluctuate. In particular, programmable non-volatile memory cells (e.g., floating gate memories (floating gate memories), phase change memories (phase change memories), resistive random access memories (resistive RAMs), etc.) are used in-memory computing devices, and the fluctuation of the storage weight may cause the neural network to output less accurate output data. Therefore, it is desirable to provide an in-memory operation device with higher inference accuracy.
Disclosure of Invention
An integrated circuit is described that includes an in-memory computing device (in-memory computing device) that implements a neural network. The in-memory computing device has a plurality of synapse layers (synapse layers). These synapse layers include a plurality of first type of synapse layers (first of synthetic layers) and a plurality of second type of synapse layers (second of synthetic layers). The first type synapse layer comprises a plurality of first type of memory cells (first type of memory cells), and the second type synapse layer comprises a plurality of second type of memory cells (second type of memory cells). The first type of memory cell has more accurate data storage and/or more stable read/write operations than the second type of memory cell. The trend of the fluctuation of the weight stored in the first type of memory cell is lower compared to the second type of memory cell. The first type of memory cell and the second type of memory cell may not be identical in structure of the memory cell, size of the memory cell, and/or algorithm in performing the read/write operation.
In some embodiments, the weight stored in the first and second type memory cells may be the resistance of the memory cell. For example, the memory cells are, for example, resistive random access memory (resistive RAM), magnetic random access memory (magnetic RAM), ferroelectric random access memory (ferroelectric RAM), and charge trapping memory (charge trapping memories). In some embodiments, the stored weight may be information stored in a memory location, such as bits "0" and "1" in static random access memory (static RAM) and dynamic random access memory (dynamic RAM). In some embodiments, the values of the weights may be stored in a column of memory cells, where each memory cell represents a binary number.
The first type and second type synapse layers may comprise an array of memory cells having M columns and N rows. Each memory cell in the array of memory cells stores a weight factor Wmn. Rows of memory cells in the array are coupled to a first set of first access lines and columns of memory cells are coupled to a second set of second access lines. The memory cell array may further include a decoder and driver circuit (decoder and driver circuit), a sensing circuit (sensing circuit) and an activation function circuit (activation function circuit). The decoding and driving circuit is electrically coupled to the first access line set and the second access line set. Sensing circuitry, such as sense amplifiers (sense amplifiers), is electrically coupled to the second set of access lines.
In some embodiments, the signals of the first access line of the first set of access lines represent the inputs Xm of the columns. The output current sensed by the sensing circuit on a particular second access line of the set of second access lines may represent the product of the input Xm and the weight factor Wmn through a row of memory cells coupled to the particular second access line. In some embodiments, the output sensed in the memory array in the first type of synapse layer or the second type of synapse layer is an input signal to the memory cell array in the other synapse layer.
Some embodiments of the in-memory computing device may further include a multiply and accumulate unit (multiply and accumulate unit). The multiplication and accumulation unit may receive the weight factors and the inputs stored in the storage units of the first type and the second type of synapse layers to estimate the product sum of the inputs and the weight factors.
Some embodiments of the in-memory computing device may further include a plurality of third type of synapse layers (third type of synaptic layers) including a third type of memory cells (third type of memory). The third type of memory cell is different from the first type of memory cell and the second type of memory cell.
The invention also provides a method for manufacturing an in-memory computing device as described herein.
In order to better appreciate the above and other aspects of the present invention, reference will now be made in detail to the embodiments illustrated in the accompanying drawings.
Drawings
Embodiments of the present technology are described in detail with reference to fig. 1 to 12.
FIG. 1 illustrates a neural network.
FIG. 2 depicts an in-memory computing device having a first type of synapse layer and a second type of synapse layer.
Fig. 3A and 3B illustrate resistance values of the first type memory cell.
Fig. 4A, 4B and 4C illustrate resistance values of the second type memory cell.
FIG. 5 depicts a first example of a simplified chip block diagram of an in-memory computing device having a first type of synapse layer and a second type of synapse layer.
FIG. 6 depicts a memory system having two synapse layers of a first type and two synapse layers of a second type.
FIG. 7 illustrates an array of first-type memory cells in the first-type synapse layer of FIG. 6.
FIG. 8 illustrates an array of first-type memory cells in the first-type synapse layer of FIG. 6 and an array of second-type memory cells in the second-type synapse layer.
FIG. 9 illustrates a row of memory cells storing values of weights.
FIG. 10 is a simplified block diagram of an integrated circuit including an in-memory operation device having a first type of synapse layer and a second type of synapse layer and a multiply-and-accumulate unit.
FIG. 11 illustrates inference accuracy of an in-memory computing device having a first type of synapse layer and a second type of synapse layer.
FIG. 12 depicts a simplified flow diagram of an in-memory computing device for fabricating an integrated circuit in accordance with the present technique.
[ notation ] to show
100: neural network
102. 106, 108, 110: hidden layer
104: output layer
112. 114, 116, 118: synapse layer
200. 502, 600: memory system
210. 220, 230: first type of synapse layer
240. 250, 260: synapse layer of a second type
302. 402, a step of: low resistance extension
303. 404: high resistance extension
306. 406: first resistance extension
308. 408: second resistance extension
310. 410: third resistance extension
312. 412: fourth resistance extension
416: resistance range
500. 1000: in-memory arithmetic device
503: bus line
504: controller
505: data bus
512: bias configuration state machine
590: buffer circuit
593: input/output circuit
610. 620: first type of synapse layer
611. 621: first type memory cell array
612、761、762、763、781、782、841、842、843、853、854、
901: a first set of access lines
613. 771, 772, 851, 852, 863, 864, 865, 911, 912, 913: second set of access lines
615. 625, 635, 645: column decoder/driver
616. 626, 636, 646: row decoder/driver
617. 627, 637, 647: sensing circuit
618. 628, 638, 648: data buffer
614. 624, 634, 644: activation function circuit
630. 640: synapse layer of a second type
631. 641: second type memory cell array
711、712、713、721、722、723、731、732、741、742、751、
752: first type memory cell
811、812、821、822、831、832、871、872、873、881、882、
883: memory cell
861. 862: a third access line
900: a portion of a column of memory cells of a first type of memory cell
921. 922, 923: first type memory cell
1010: multiply and accumulate unit
1210. 1220 and 1230: step (ii) of
Detailed Description
Embodiments of the present technology are described in detail with reference to fig. 1 to 12.
Referring to fig. 1, inference accuracy (inference accuracy) of a neural network (neural network)100 may depend on weights stored in some synaptic layers (synapse layers) rather than weights stored in other synaptic layers. For example, the accuracy of storing weights is more important at the synapse layer near the input layer (input layer)102 than at the output layer (output layer) 104. In other words, fluctuations in weights in the synapse layer near the
FIG. 2 is an exemplary simplified diagram of a memory system 200 of an in-memory computing device (in-memory computing device). The memory system 200 includes a plurality of first type of synapse layers (e.g., synapse layers 210, 220, 230) and a plurality of second type of synapse layers (e.g., synapse layers 240, 250, 260). For clarity, FIG. 2 depicts only three layers of a first type of synapse layer and a second type of synapse layer. However, any combination of one or more of the first type of synapse layers with one or more of the second type of synapse layers may be used in a memory system implementing the techniques described herein.
The first type of synapse layer in the memory system 200 comprises first type of memory cells (first type of memory cells) that may be used to store weights near the input layer. The second type of synapse layer in the memory system 200 comprises second type of memory cells (second type of memory cells), which may be used to store weights near the output layer.
The overall inference accuracy of the neural network can be increased by using the first type of memory cells in the first type of synapse layer as compared to the second type of memory cells, which may store more accurate weights or may be less prone to weight fluctuations. The first type of memory cell has more accurate data storage and/or more stable read/write operations than the second type of memory cell. The first type of memory cell may be different from the second type of memory cell in terms of memory cell type, memory cell structure, or memory cell size. The first type of memory cell is also less prone to device variations and operation failures, such as read or write operation failures.
The memory cells of the first type memory cells may be volatile memory cells (such as Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM)) or non-volatile memory cells (such as mask read only memory (mask ROM), fuse read only memory (fuse ROM), and resistive random access memory (resistive RAM)). The memory cells of the first type of memory cells may be read-only memory cells (e.g., mask ROM, fuse ROM) or reprogrammable memory cells (e.g., SRAM, DRAM, and resistive RAM). In some embodiments, the weights stored in the first type of memory cells may be the data stored in the memory cells, such as storing bits "0" and "1" in SRAM and DRAM. The accuracy of the weights stored in the SRAM or DRAM cells can be handled by sense amplifiers connected to the memory cells. In some embodiments, the weight stored in the first type of memory cell may BE obtained by sensing the resistance of a memory cell, such as resistive RAM, floating gate Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), dielectric charge trapping devices (SONOS), BE-SONOS, TANOS, MABE-SONOS, and phase change memories (phase change memories).
The second type of memory cell is more prone to weight fluctuations, device variations, and operational failures than the first type of memory cell. The second type of memory cell may BE a non-volatile memory cell such as resistive RAM, floating gate MOSFET, dielectric charge trapping devices (e.g., SONOS, BE-SONOS, TANOS, MA BE-SONOS), phase change memory, ferroelectric random access memory (ferroelectric RAMs), and magnetic random access memory (magnetic RAM). The second type of memory cells may be reprogrammable memory cells such that the weights stored in the second type of memory cells may be changed during training or tuning of the neural network to improve inference accuracy.
In some embodiments, the weight stored in the second type of memory cell can BE obtained by sensing the resistance of the memory cell, such as resistive RAM, floating gate MOSFET, memory cells of dielectric charge trapping devices (e.g., SONOS, BE-SONOS, TANOS, MABE-SONOS), and phase change memory, among others.
Fig. 3A and 4A show distributions of resistance values of the first-type memory cell and the second-type memory cell, respectively. The memory cell in fig. 3A and 4A has two resistance states. The first type of memory cell in fig. 3A has a low resistance spread 302 and a high resistance spread 303. The second type memory cell in fig. 4A also has a low resistance extension 402 and a high resistance extension 404. The resistance spread of the first type memory cell is narrower than the resistance spread (resistance spreads) of the second type memory cell. The first type memory cell in fig. 3A is less prone to resistance drift (resistance drift) and noise (e.g., random telegraph noise (random electrogram noise), thermal noise (thermal noise), etc.) than the second type memory cell in fig. 4B. The second type memory cell is more prone to resistance drift and thermal noise than the first type memory cell. Reprogramming the second type memory cell to a low resistance (low resistance) may create resistance anywhere in the low resistance spread. In other words, less accurate weights may be stored in the second type of memory cells.
In some embodiments of the first type of memory cell, the stored weight may be two or more bits of data stored in the memory cell, such as bits "0" and "1" stored in SRAM, DRAM, and Read Only Memory (ROM).
Fig. 3B and 4B illustrate resistance values of the first type memory cell and the second type memory cell, respectively, which store two or more bits of data per memory cell. Such a memory cell has a plurality of resistive layers (resistance levels), such as the first resistance extension (first resistance spread)306, the second resistance extension (second resistance spread)308, the third resistance extension (third resistance spread)310, and the fourth resistance extension (fourth resistance spread)312 of the first type memory cell in fig. 3B, and the
In some embodiments, the first type of memory cell and the second type of memory cell may comprise different memory cells, i.e. the structure of the first type of memory cell is different from the structure of the second type of memory cell. The first type of memory cells may include volatile memory cells (e.g., SRAM and DRAM) and the second type of memory cells may include non-volatile memory cells (e.g., resistive RAM). In some embodiments, the first type of memory cell may include a read-only memory cell (e.g., fuse ROM) and the second type of memory cell may include a reprogrammable memory cell (e.g., resistive RAM, phase-tracking memory, charge-trapping memory).
In some embodiments of in-memory computing, the first type memory cells and the second type memory cells may comprise the same type of memory (e.g., resistive RAM), and the first type memory cells may be larger in size than the second type memory cells. Larger first type memory cells will be less noisy than second type memory cells, which results in less weight fluctuations in the first type memory cells. In some casesIn an embodiment, a manufacturing process (failure process) of the first type of memory cell may be different from a manufacturing process of the second type of memory cell, which results in the first type of memory cell having less device variations than the second type of memory cell. In some embodiments, the memory material used for data storage in the first type of memory cell may be different from the memory material used in the second type of memory cell. For example, the first type memory cell may be HfOxResistive random access memories (resistive RAMs) as materials, and the second type memory cell can be a CoOxResistive random access memories (resistive RAMs) as a material.
In some embodiments, different algorithms may be utilized to read or write data to the first type of memory cells and the second type of memory cells. For example, when bits of a charge trapping memory are stored as first-type memory cells and second-type memory cells, incremental-step-pulse programming (ISPP) can be used to shrink threshold voltage distribution (threshold voltage distribution) and resistance spread of the first-type memory cells, and single-pulse programming (single-pulse programming) can be used for the second-type memory cells.
In some embodiments, the memory system 200 may include a plurality of third type of synapse layers (third type of synthetic layer). The third type of synapse layer may comprise third type of memory cells (third type of memycells) which may be used to store weights to intermediate synapse layers (middle synapse layers) of the neural network. The weights stored in the third type of memory cells may be less accurate than the weights stored in the first type of memory cells, but more accurate than the weights stored in the second type of memory cells. In some embodiments, memory system 200 may include any number of types of memory cells, each type of memory cell having a different degree of weight fluctuation.
FIG. 5 illustrates a first example of a simplified chip block diagram of an in-
The Input/
The
FIG. 6 depicts a
The first-
Memory cell addresses (Memory cell addresses) and input data from an external source are provided from the
Similar to the first type of
The
The first type memory cells and the second type memory cells include phase change memories, resistive RAMs, ferroelectric RAMs, and magnetic RAMs, and the first access lines may be bit lines (bit lines) and the second access lines may be word lines (word lines), or vice versa. For a charge trapping memory, the first access line may be a word line and the second access line may be a bit line. The charge trapping memory may also have a third access line (third access lines), such as a source line (source lines).
FIG. 7 shows an example of the first type memory cell arrays 611 and 621 of the two first type synapse layers 610 and 620 in FIG. 6. The first type memory cell arrays 611 and 621 may be a resistive RAM in which the resistance of the memory cell represents the weight stored in the memory cell. The first type memory cell array includes M columns and N rows of memory cells. Each memory cell in the array represents a weight factor Wmn for the cell. The memory cell array 611 of the first type memory cells includes two columns and three rows. The memory cells of the first
A second set of access lines (e.g., 791, 792, 793) is coupled to the first type memory cells in the rows of first type memory cells. A first set of access lines (e.g., 781, 782) is coupled to the first type memory cells in each column of first type memory cells. A first set of access lines (e.g., 781, 782) is coupled to column decoder/
Sense circuitry 617 is coupled to each second access line in the second set of access lines through row decoder/drivers 616. The current sense signal (e.g., y1, y2, y3) at a particular second access line (e.g., 791, 792, 793) in the second set of access lines may represent a product sum of inputs by respective weight factors. The sense signals y1, y2, y3 may be stored in the data buffer 618. The stored sensing signal may be transmitted into the second type memory cell array 621 of the second type synapse layer 620 of the
The first type memory cell array 621 includes three columns and two rows. Each memory cell in the array represents a weight factor Wmn for the cell. The
A second set of access lines (e.g., 771, 772) is coupled to the memory cells in the columns of memory cells. A first set of access lines (e.g., 761, 762, and 763) is coupled to the memory cells in each column of memory cells. A first set of access lines (e.g., 761, 762, 763) is coupled to the column decoder/
Sensing circuit 627 is coupled to each second access line of the second set of access lines through row decoder/drivers 626. The current sense signal (e.g., z1, z2) at a particular second access line (e.g., 771, 772) in the second set of access lines may represent a product sum of inputs by various weighting factors. The sensing signals z1, z2 may be stored in a data buffer 628. The stored sensing signals may be sent into the second type memory cell array 631 of the second type synapse layer 630 of the
FIG. 8 shows a first type of memory cell employing a first type of synapse layer 620 of a charge trapping memory and a second type of memory cell employing a second type of synapse layer 630 of a resistive random access memory.
The array of first type memory cells 621 includes three columns and two rows of first type memory cells, wherein a third set of access lines (e.g., source lines of a charge trapping memory) is coupled to the first type memory cells in each row of first type memory cells. The first type of memory cells in the array may each include a transistor having a voltage threshold, representing a weight factor Wmn for the cell. The
A second set of access lines (e.g., 851, 852) is coupled to the first type memory cells in the rows of the first type memory cells. A first set of access lines (e.g., 841, 842, 843) is coupled to the first type memory cells in each column of first type memory cells. A first set of access lines (e.g., 841, 842, and 843) is coupled to column decoder/
A third set of access lines (e.g., 861, 862) is coupled to row decoder/driver 626. Sensing circuitry 627 is coupled to each third access line of the third set of access lines. The current sense signal (e.g., z1, z2) at a particular second access line (e.g., 861, 862) in the third set of access lines may represent a product sum of inputs by respective weight factors. The sensing signals z1, z2 may be stored in a data buffer 628. The stored sensing signals z1, z2 may be sent into the second type memory cell array 631 of the second type synapse layer 630 of the
The memory cell array 631 of the second type memory cell includes two columns and three rows of the resistance RAM. Each second type memory cell in the array represents a weight factor W for the cell. The
A second set of access lines (e.g., 863, 864, and 865) are coupled to the memory cells in the rows of memory cells. A first set of access lines (e.g., 853, 854) is coupled to the memory cells in each column of memory cells. A first set of access lines (e.g., 853, 854) is coupled to the column decoder/
The current sense signal (e.g., a1, a2, a3) at a particular second access line (e.g., 863, 864, 865) in the second set of access lines may represent a product sum of inputs by respective weight factors. The sensing signals a1, a2, a3 may be stored in the data buffer 638.
The representative number of the weight may also be stored in the first type memory cell array. FIG. 9 illustrates a portion of a row of memory cells (memory cells) of the first type of
FIG. 10 is a simplified chip block diagram of a second example of an in-
The first type of memory cells in the first type of synapse layer of the
The
FIG. 11 shows the accuracy of inference for an in-memory computing device with a total of nine synapse layers. The first N synapse layers are of a first type having SRAM devices as first type memory cells, and the remaining N-9 synapse layers are of a second type having resistive RAM devices as second type memory cells. When all synapse layers are of the first type, the inference accuracy is 90.94%. The inference accuracy is determined by the average accuracy after classifying 10,000 test image data. When all synapse layers are of the second type, the inference accuracy is 16.73%. When there are one first type of synapse layer and eight second type of synapse layers, the inference accuracy is 84.45%. The accuracy of the inference increases to 87.78% for an additional first type of synapse layer. When all synapse layers are of the first type, increasing the number of synapse layers of the first type to four improved inference accuracies.
FIG. 12 is a simplified flow diagram of an in-memory computing device for use in fabricating integrated circuit devices in accordance with the present technique. In
The first type of storage unit is less prone to weight fluctuations than the second type of storage unit. In some embodiments, the manufacturing process for the first type of memory cell may be different than the manufacturing process for the second type of memory cell, the first type of memory cell having less device variability than the second type of memory cell.
In some embodiments of the in-memory operation device, the first type memory cells and the second type memory cells may comprise the same type of memory cells (e.g., resistive RAMs), and the first type memory cells may be larger in size than the second type memory cells, the larger first type memory cells will have less noise than the second type memory cells, which results in less weight fluctuation in the first type memory cells.
In some embodiments, the first type of memory cell and the second type of memory cell may comprise different memory cells, i.e. the structure of the first type of memory cell is different from the structure of the second type of memory cell. The first type of memory cells may include volatile memory cells (e.g., SRAM and DRAM) and the second type of memory cells may include non-volatile memory cells (e.g., resistive RAM). In some embodiments, the first type of memory cell may include a read-only memory cell (e.g., a fuse ROM), and the second type of memory cell may include a reprogrammable memory cell (e.g., a resistive RAM).
The first type of memory cells may be volatile memory cells (e.g., SRAM and DRAM) or non-volatile memory cells (e.g., mask ROM, fuse ROM, and resistive RAM). The first type of memory cells may be read-only memory cells (e.g., mask ROM, fuse ROM) or reprogrammable memory cells (e.g., SRAM, DRAM, and resistive RAM). In some embodiments, the weight stored in the first type of memory cell may BE a resistance of the memory cell, such as a resistive RAM, a floating gate MOSFET, a dielectric charge trapping device (e.g., SONOS, BE-SONOS, TANOS, MA BE-SONOS), and a phase change memory. In some embodiments, the stored weight may be two or more bits of information stored in a memory cell, such as bits "0" and "1" in SRAM, DRAM, and ROM.
The second type of memory cell may BE a non-volatile memory cell such as a resistive RAM, a floating gate MOSFET, a dielectric charge trapping device (e.g., SONOS, BE-SONOS, TANOS, MA BE-SONOS), a phase change memory, a ferroelectric RAMs, and magnetic RAMs. In some embodiments, the weight stored in the second type of memory cell may BE a resistance of the memory cell, such as a resistive RAM, a floating gate MOSFET, a dielectric charge trapping device (e.g., SONOS, BE-SONOS, TANOS, MA BE-SONOS), and a phase change memory.
At step 1330, peripheral circuits (peripheral circuits) are formed that support the in-memory computing device. The peripheral circuits may be column decoders/drivers (e.g., column decoders/
While the present invention has been described with reference to the above embodiments, it is not intended to be limited thereto. Various modifications and alterations can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the present invention is defined by the scope of the appended claims.