阅读说明：本技术 一种碳化硅功率器件堆叠栅介质及制造方法 (Silicon carbide power device stacked gate dielectric and manufacturing method thereof ) 是由 王颖 隋金池 曹菲 包梦恬 于成浩 于 2019-10-09 设计创作，主要内容包括：本发明公开一种碳化硅功率器件AlON/Al<Sub>2</Sub>O<Sub>3</Sub>堆叠栅介质,所述电容结构包括：SiC衬底、堆叠栅介质层和正负金属电极；在所述SiC衬底层上设有SiC外延层；所述堆叠栅介质层包括Al<Sub>2</Sub>O<Sub>3</Sub>过渡层和AlON介质层；所述SiC外延层上设有所述Al<Sub>2</Sub>O<Sub>3</Sub>过渡层,所述Al<Sub>2</Sub>O<Sub>3</Sub>过渡层上设有所述AlON介质层；所述正负电极分别从所述AlON介质层的表面和所述SiC衬底的背面连接。本发明与应用厚度为50nm的SiO2介质层的常规器件比较,可以提高栅介质的临界击穿电场,提高了器件的可靠性。(The invention discloses a silicon carbide power device AlON/Al 2 O 3 Stacked gate dielectrics, the capacitor structure comprising: the SiC substrate, the stacked gate dielectric layer and the positive and negative metal electrodes; a SiC epitaxial layer is arranged on the SiC substrate layer; the stacked gate dielectric layer comprises Al 2 O 3 A transition layer and an AlON dielectric layer; the SiC epitaxial layer is provided with the Al 2 O 3 Transition layer of said Al 2 O 3 The transition layer is provided with the AlON dielectric layer; and the positive electrode and the negative electrode are respectively connected from the surface of the AlON dielectric layer and the back of the SiC substrate. Compared with the conventional device using the SiO2 dielectric layer with the thickness of 50nm, the invention can improve the critical breakdown electric field of the gate dielectric and improve the reliability of the device.)

1. Silicon carbide power device AlON/Al₂O₃The stacked gate dielectric is characterized in that: the stacking grid structure comprises a SiC substrate (11), wherein a SiC epitaxial layer (12), a stacking grid dielectric layer (2) and a positive electrode (4) are sequentially arranged on the SiC substrate (11), a negative electrode (3) is arranged at the lower part of the SiC substrate (11), and the stacking grid dielectric layer (2) comprises Al₂O₃A transition layer (21), an AlON gate dielectric layer (22), the aboveAl is sequentially arranged on the epitaxial layer (12)₂O₃The gate structure comprises a transition layer (21) and an AlON gate dielectric layer (22), wherein the AlON gate dielectric layer (22) is a high-k dielectric AlON with the oxygen content of 0-10%.

2. Silicon carbide power device AlON/Al according to claim 1₂O₃The stacked gate dielectric is characterized in that: the thickness of the SiC epitaxial layer (12) is 8-10 mu m, and the doping concentration is 8 multiplied by 10¹⁵-1×10¹⁶cm^-3。

3. Silicon carbide power device AlON/Al according to claim 1₂O₃The stacked gate dielectric is characterized in that: the Al is₂O₃The thickness of the transition layer (21) is 1-10 nm.

4. Silicon carbide power device AlON/Al according to claim 1₂O₃The stacked gate dielectric is characterized in that: the Al is₂O₃The thickness of the transition layer (21) is 1-10 nm.

5. Silicon carbide power device AlON/Al according to claim 1₂O₃The stacked gate dielectric is characterized in that: the thickness of the AlON gate dielectric layer (22) is 50-80 nm.

6. Silicon carbide power device AlON/Al according to claim 1₂O₃The stacked gate dielectric is characterized in that: the Al is₂O₃The thickness of the transition layer (21) is 1-10 nm.

7. Silicon carbide power device AlON/Al according to claim 1₂O₃The stacked gate dielectric is characterized in that: the negative electrode (3) and the positive electrode (4) are respectively connected from the surface of the AlON gate dielectric layer (22) and the back of the SiC substrate (11).

8. AlON/Al₂O₃The method for manufacturing the SiC gate dielectric capacitor of the stacked gate dielectric layer is characterized in thatThe method comprises the following steps: the method comprises the following steps:

A) performing standard cleaning treatment on the SiC substrate (11), depositing metal Ni/Au as an ohmic contact layer on the back surface of the SiC substrate (11) by a magnetron sputtering method, and then performing standard cleaning treatment on N₂Annealing treatment in the environment;

B) rinsing the N-type SiC epitaxial layer (12) on the SiC substrate (11) by BOE, and depositing a layer of Al with the thickness of 1-10nm on the SiC epitaxial layer (12) by using an atomic layer deposition ALD method₂O₃A transition layer (21);

C) method for ALD on Al₂O₃Depositing an AlON gate dielectric layer (22) with the thickness of 50-80nm on the transition layer (21);

D) growing AlON/Al₂O₃Stacking gate dielectric layer on N₂Annealing treatment in the environment, wherein the specific annealing temperature is 400-;

E) by utilizing a magnetron sputtering method, sputtering metal Al on the surface of the AlON gate dielectric layer (22) as a positive electrode.

9. According to AlON/Al₂O₃The manufacturing method of the SiC gate dielectric capacitor with the stacked gate dielectric layers is characterized by comprising the following steps: depositing a layer of Al with the thickness of 1-10nm in the step B₂O₃And the deposition temperature of the transition layer (21) is 350 ℃, and the deposition time is 5-20 min.

Technical Field

The invention relates to the technical field of microelectronics, in particular to a silicon carbide power device AlON/Al₂O₃A stacked gate dielectric and a method of making the same.

Background

4H-SiC is suitable for high power devices due to high breakdown strength, high electron drift velocity and high thermal conductivity. The SiC material is a typical representative of third-generation semiconductors, and the excellent physical and chemical properties of the SiC material are ideal materials for manufacturing high-temperature, high-power, high-frequency and high-radiation-resistance devices. Although 4H-SiC power MOSFETs have been commercialized, the study of their gate dielectrics is still of great interest. The gate dielectric is essentially critical in 4H-SiC MOS devices because it is required to maintain high electric fields and low gate leakage currents. For SiO₂a/SiC MOS device according to the Gaussian theorem (k)_SiCE_SiC＝k_oxideE_oxide) When SiC (k ═ 9.6-10) reaches its critical breakdown field (3MV/cm), SiO₂The electric field in the dielectric layer (k ═ 3.9) will reach around 7.5MV/cm, and such a high electric field will seriously degrade the reliability of the oxide layer. Therefore, high-k dielectrics are potential candidates, replacing SiO with high-k materials₂As a gate dielectric layer, many transition metal oxides having a high dielectric constant (high-k) have been widely studied for Si-based electronic devices. For SiC MOS devices, reliability may be improved by using high-k materials because the electric field in the gate dielectric may be reduced.

Generally, higher dielectric constant dielectrics have smaller bandgaps. Thus, among the various high-k materials, alumina (Al)₂O₃) It is suitable for SiC MOS devices due to its wide band gap and high thermal stability. High-k dielectric material is adopted to replace SiO₂As a gate dielectric material of an MOS device, although the withstand voltage capability of a dielectric layer can be improved to a certain extent, traps are introduced into the material in the process technology, the interface state density of the device cannot be effectively reduced, and the gate leakage current is overlarge, so that the gate dielectric is limited to bear a higher electric field.

Disclosure of Invention

The invention aims to provide AlON/Al₂O₃The stacked gate dielectric capacitor structure and the manufacturing method can reduce gate leakage current, further improve the voltage endurance capability of the gate dielectric layer and the reliability of the device, and solve the problems in the prior art.

In order to achieve the purpose, the invention provides the following scheme:

the invention provides a silicon carbide power device AlON/Al₂O₃The stacked gate dielectric comprises a SiC substrate, wherein a SiC epitaxial layer, a stacked gate dielectric layer and a positive electrode are sequentially arranged on the SiC substrate, a negative electrode is arranged at the lower part of the SiC substrate, and the stacked gate dielectric layer comprises Al₂O₃The gate electrode comprises a transition layer and an AlON gate dielectric layer, wherein Al is sequentially arranged on the epitaxial layer₂O₃The gate dielectric layer of AlON, the said AlON gate dielectric layer is oxygen content of the high-k medium 0-10% AlON.

Preferably, the thickness of the SiC epitaxial layer is 8-10 mu m, and the doping concentration is 8 multiplied by 10¹⁵-1×10¹⁶cm^-3。

Preferably, the Al₂O₃The thickness of the transition layer is 1-10 nm.

Preferably, the Al₂O₃The thickness of the transition layer is 1-10 nm.

Preferably, the thickness of the AlON gate dielectric layer is 50-80 nm.

Preferably, the Al₂O₃The thickness of the transition layer is 1-10 nm.

Preferably, the negative electrode and the positive electrode are respectively connected from the surface of the AlON gate dielectric layer and the back of the SiC substrate.

AlON/Al₂O₃The manufacturing method of the SiC gate dielectric capacitor with the stacked gate dielectric layers is characterized by comprising the following steps: the method comprises the following steps:

A) carrying out standard cleaning treatment on the SiC substrate, depositing metal Ni/Au as an ohmic contact layer on the back of the SiC substrate by utilizing a magnetron sputtering method, and then carrying out standard cleaning treatment on N₂Annealing treatment in the environment;

B) rinsing the N-type SiC epitaxial layer on the SiC substrate by BOE, and depositing a layer of Al with the thickness of 1-10nm on the SiC epitaxial layer by utilizing an Atomic Layer Deposition (ALD) method₂O₃A transition layer;

C) method for ALD on Al₂O₃Depositing a layer thickness on the transition layerAlON gate dielectric layer of 50-80 nm;

D) growing AlON/Al₂O₃Stacking gate dielectric layer on N₂Annealing treatment in the environment, wherein the specific annealing temperature is 400-;

E) and sputtering metal Al on the surface of the AlON gate dielectric layer as a positive electrode by using a magnetron sputtering method.

Preferably, a layer of Al with the thickness of 1-10nm is deposited in the step B₂O₃And (3) a transition layer, wherein the deposition temperature is 350 ℃, and the deposition time is 5-20 min.

The invention discloses the following technical effects:

1. the gate dielectric material AlON (oxygen content is 0-10%) adopted by the invention is a high-k material, has good thermal stability and high crystallization temperature, thereby increasing the critical breakdown electric field of the gate dielectric layer and improving the reliability of the device. Meanwhile, the stack gate dielectric material is annealed by adopting nitrogen, so that the interface state density and the boundary trap density between the silicon carbide and the gate dielectric are reduced, the channel mobility is increased, and the device performance is improved.

2. The invention adopts the lower layer Al₂O₃Transition layer of Al₂O₃The material has higher conduction band offset, increases the barrier height between the gate dielectric and the silicon carbide, and can prevent electrons from being injected into a high-k material with a low barrier from the SiC substrate, thereby reducing gate leakage current and improving the stability of the device.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

FIG. 1 shows AlON/Al of the present invention₂O₃The structure schematic diagram of the stacked gate dielectric capacitor;

FIG. 2 shows AlON/Al of the present invention₂O₃Manufacturing process of stacked gate dielectric capacitorA schematic diagram;

FIG. 3 shows AlON/Al of the present invention₂O₃The manufacturing structure schematic diagram of the stacked gate dielectric capacitor;

11 is a SiC substrate, 12 is a SiC epitaxial layer, 2 is a stacked gate dielectric layer, 21 is Al₂O₃The transition layer, the transition layer 22 are AlON gate dielectric layers with the oxygen content of 0-10%, the transition layer 3 is a negative electrode, and the transition layer 4 is a positive electrode.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

Referring to FIGS. 1-3, a silicon carbide power device AlON/Al₂O₃The stacked gate dielectric comprises a SiC substrate 11, wherein a SiC epitaxial layer 12, a stacked gate dielectric layer 2 and a positive electrode 4 are sequentially arranged on the SiC substrate 11, a negative electrode 3 is arranged at the lower part of the SiC substrate 11, and the stacked gate dielectric layer 2 comprises Al₂O₃ A transition layer 21 and an AlON gate dielectric layer 22, wherein Al is sequentially arranged on the epitaxial layer 12₂O₃The gate structure comprises a transition layer 21 and an AlON gate dielectric layer 22, wherein the AlON gate dielectric layer 22 is AlON with the oxygen content of 0-10% of a high-k dielectric.

Further, the thickness of the SiC epitaxial layer 12 is 8-10 μm, and the doping concentration is 8 × 10¹⁵-1×10¹⁶cm^-3。

Further, the Al₂O₃The thickness of the transition layer 21 is 1-10 nm.

Further, the Al₂O₃The thickness of the transition layer 21 is 1-10 nm.

Further, the thickness of the AlON gate dielectric layer 22 is 50-80 nm.

Further, the Al₂O₃The thickness of the transition layer 21 is 1-10 nm.

Further, the negative electrode 3 and the positive electrode 4 are respectively connected from the surface of the AlON gate dielectric layer 22 and the back of the SiC substrate 11.

AlON/Al₂O₃The manufacturing method of the SiC gate dielectric capacitor with the stacked gate dielectric layers comprises the following steps:

A) performing standard cleaning treatment on the SiC substrate 11, depositing metal Ni/Au as an ohmic contact layer on the back surface of the SiC substrate 11 by a magnetron sputtering method, and then performing standard cleaning treatment on N₂And (5) annealing treatment in the environment.

A1) SiC substrate 11 is subjected to a standard cleaning process.

A1.1)H₂SO₄:H₂O₂Cleaning and waiting for cooling in a ratio of 7:3, flushing with deionized water, and drying with nitrogen;

A1.2)NH₄OH:H₂O₂cleaning for 2min at a ratio of 1:1:6 under DIW, washing with deionized water, and drying with nitrogen;

A1.3)HCl:H₂O₂cleaning for 2min at a ratio of 1:1:6 under DIW, washing with deionized water, and drying with nitrogen;

a1.4) BOE (1:20 or 1:7) for 2min, deionized water rinsing and nitrogen blow-drying.

A2) Sputtering 200nm of metal Ni and then 70nm of metal Au on the back of the SiC substrate 11 by a magnetron sputtering method, wherein the vacuum degree is 8 multiplied by 10^-4Pa。

A3) In N₂Annealing at 950 deg.C for 30 min.

B) Rinsing the N-type SiC epitaxial layer (12) on the SiC substrate (11) by BOE, and depositing a layer of Al with the thickness of 1-10nm on the SiC epitaxial layer (12) by utilizing an Atomic Layer Deposition (ALD) method₂O₃ A transition layer 21.

B1) BOE rinsing is carried out on the front SiC epitaxial layer 12, deionized water rinsing is carried out, and nitrogen blow drying is carried out;

B2) depositing Al with a thickness of 5nm on the SiC epitaxial layer 12 by an Atomic Layer Deposition (ALD) method₂O₃Layer 21, deposition temperature 350 deg.CAnd the time is 11 min.

C) Method for ALD on Al₂O₃Depositing an AlON gate dielectric layer 22 with the thickness of 50-80nm on the transition layer 21;

D) growing AlON/Al₂O₃Stacking gate dielectric layer on N₂Annealing treatment in the environment, wherein the specific annealing temperature is 400-;

E) and sputtering metal Al on the surface of the AlON gate dielectric layer 22 by using a magnetron sputtering method to serve as a positive electrode.

Further, a layer of Al with the thickness of 1-10nm is deposited in the step B₂O₃The deposition temperature of the transition layer 21 is 350 ℃, and the deposition time is 5-20 min.

In the description of the present invention, it is to be understood that the terms "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on those shown in the drawings, are merely for convenience of description of the present invention, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention.

The above-described embodiments are merely illustrative of the preferred embodiments of the present invention, and do not limit the scope of the present invention, and various modifications and improvements of the technical solutions of the present invention can be made by those skilled in the art without departing from the spirit of the present invention, and the technical solutions of the present invention are within the scope of the present invention defined by the claims.