阅读说明：本技术 沟槽栅半导体器件及其制造方法 (Trench gate semiconductor device and method of manufacturing the same ) 是由 杨继业 赵龙杰 李�昊 于 2019-10-21 设计创作，主要内容包括：本发明公开了一种沟槽栅半导体器件,沟槽栅包括形成于半导体衬底中沟槽、形成于所述沟槽的底部表面和侧面的栅氧化层；栅氧化层由第一氧化层和第二氧化层叠加而成；第一氧化层为炉管热氧化层；第二氧化层为PECVD氧化层；栅氧化层具有通过RTA处理的热致密结构；利用沟槽中形成的PECVD氧化层具有底部表面的厚度大于侧面厚度的特性,使栅氧化层具有位于沟槽的底部表面的厚度大于位于沟槽的侧面的厚度的结构。本发明还公开了一种沟槽栅半导体器件的制造方法。本发明能提高器件的BVGSS,同时不影响器件的阈值电压,工艺简单且成本低。(The invention discloses a kind of trench gate semiconductor device, wherein the trench gate comprises a trench formed in a semiconductor substrate and gate oxide layers formed on the bottom surface and the side surfaces of the trench, the gate oxide layer is formed by overlapping a th oxide layer and a second oxide layer, a th oxide layer is a furnace tube thermal oxide layer, the second oxide layer is a PECVD oxide layer, the gate oxide layer has a thermal dense structure processed by RTA, and the gate oxide layer has a structure that the thickness of the bottom surface is larger than that of the side surfaces by utilizing the characteristic that the thickness of the PECVD oxide layer formed in the trench is larger than that of the side surfaces, so that the gate oxide layer has the thickness of the bottom surface positioned in the trench larger than that of the side surfaces of the trench.)

A semiconductor device with trench gate, wherein the trench gate comprises a trench formed in a semiconductor substrate, and gate oxide layers formed on the bottom surface and side surfaces of the trench;

the gate oxide layer is formed by overlapping an th oxide layer and a second oxide layer;

the th oxidation layer is a furnace tube thermal oxidation layer;

the second oxide layer is a PECVD oxide layer;

the gate oxide layer is provided with a heat dense structure processed by RTA;

and by utilizing the characteristic that the PECVD oxide layer formed in the groove has the thickness of the bottom surface larger than the thickness of the side surface, the gate oxide layer has a structure that the thickness of the bottom surface of the groove is larger than the thickness of the side surface of the groove.

2. The trench-gate semiconductor device of claim 1 wherein: the trench gate further comprises a gate conductive material layer filled in the trench formed with the gate oxide layer.

3. The trench-gate semiconductor device of claim 2 wherein: the semiconductor substrate includes a silicon substrate.

4. The trench-gate semiconductor device of claim 3 wherein: the gate conductive material layer includes a polysilicon gate.

5. The trench gate semiconductor device of claim 1 further comprising a body region doped with a second conductivity type, said body region being formed in said semiconductor substrate, a source region heavily doped with th conductivity type being formed on a surface of said body region, said trench passing through said body region, said surface of said body region being covered by sides of said layer of gate conductive material for forming a channel, a thickness of said gate oxide layer on said sides of said trench for adjusting a threshold voltage of said device, and a thickness of said gate oxide layer on a bottom surface of said trench for increasing a gate-source withstand voltage of said device.

6. The trench-gate semiconductor device of claim 5 wherein said semiconductor device is a DMOS device and further comprising a th heavily doped drain region of conductivity type formed in said thinned back surface of said semiconductor substrate.

7. The trench-gate semiconductor device of claim 4 wherein said th oxide layer has a thickness of

A method of manufacturing a trench gate semiconductor device of the type 8, , comprising the steps of:

step , forming a trench in the semiconductor substrate;

step two, forming an th oxidation layer on the bottom surface and the side surface of the groove by adopting a furnace tube thermal oxidation process;

step three, forming a second oxide layer on the bottom surface and the side surface of the groove with the th oxide layer formed by adopting a PECVD (plasma enhanced chemical vapor deposition) process, and forming a gate oxide layer by overlapping the th oxide layer and the second oxide layer;

the thickness of an oxide layer grown on the bottom surface of the groove by the PECVD process is larger than that of an oxide layer grown on the side surface of the groove, so that the gate oxide layer has a structure that the thickness of the oxide layer on the bottom surface of the groove is larger than that of the oxide layer on the side surface of the groove;

and fourthly, performing RTA treatment on the gate oxide layer to ensure that the gate oxide layer is thermally compact.

9. The method of manufacturing a trench-gate semiconductor device according to claim 8, further comprising, after step four, the steps of:

and step five, filling a gate conductive material layer in the groove formed with the gate oxide layer.

10. The method of manufacturing a trench-gate semiconductor device according to claim 9, wherein: the semiconductor substrate includes a silicon substrate.

11. The method of manufacturing a trench-gate semiconductor device according to claim 10, wherein: the gate conductive material layer includes a polysilicon gate.

12. The method of manufacturing a trench-gate semiconductor device according to claim 8, wherein: further comprising the steps of:

sixthly, forming a body region doped with a second conduction type in the semiconductor substrate;

the groove penetrates through the body region, the surface of the body region covered by the side face of the gate conductive material layer is used for forming a channel, the thickness of the gate oxide layer, which is positioned on the side face of the groove, is used for adjusting the threshold voltage of a device, and the thickness of the gate oxide layer, which is positioned on the side face of the groove, is used for improving the gate-source withstand voltage of the device;

and seventhly, forming a heavily doped source region of the conductive type on the surface of the body region.

13. The method of manufacturing a trench-gate semiconductor device according to claim 12, wherein: the semiconductor device is a DMOS device, further comprising the steps of:

and step eight, thinning the semiconductor substrate, and forming an th conduction type heavily doped drain region on the back of the thinned semiconductor substrate.

14. The method of claim 12 wherein said th oxide layer has a thickness of

15. The method of claim 13, wherein said semiconductor device is an N-type device and the th conductivity type is N-type and the second conductivity type is P-type, or wherein said semiconductor device is a P-type device and the th conductivity type is P-type and the second conductivity type is N-type.

Technical Field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to types of trench gate semiconductor devices and a manufacturing method of types of trench gate semiconductor devices.

Background

The gate structure of a semiconductor device includes both a planar gate and a trench gate, and the trench gate can obtain larger current density and smaller on-resistance and is often applied to a power device such as a DMOS device.

For trench gates, it is common to include a trench, a gate oxide layer formed on the inside surface of the trench, including the bottom surface and the sides, and a polysilicon gate completely filling the trench. The trench gate needs to pass through the body region so that the polysilicon gate can laterally cover the body region so that a channel can be formed on the surface of the body region that is laterally covered by the polysilicon gate when the gate is opened.

In the trench gate semiconductor device, the gate-source withstand voltage, that is, the reverse breakdown voltage between gates and sources (BVGSS) of the device is difficult to increase. BVGSS is mainly related to the gate oxide and cannot be improved by simply increasing the thickness of the gate oxide.

Disclosure of Invention

The invention aims to provide kinds of trench gate semiconductor devices, which can improve the BVGSS of the devices, and the invention also provides a manufacturing method of kinds of trench gate semiconductor devices.

In order to solve the technical problem, the trench gate of the trench gate semiconductor device provided by the invention comprises a trench formed in a semiconductor substrate and gate oxide layers formed on the bottom surface and the side surface of the trench.

The gate oxide layer is formed by overlapping an th oxide layer and a second oxide layer.

The th oxide layer is a furnace tube thermal oxide layer.

The second oxide layer is a Plasma Enhanced Chemical Vapor Deposition (PECVD) oxide layer.

The gate oxide layer has a thermally dense structure processed by RTA.

And by utilizing the characteristic that the PECVD oxide layer formed in the groove has the thickness of the bottom surface larger than the thickness of the side surface, the gate oxide layer has a structure that the thickness of the bottom surface of the groove is larger than the thickness of the side surface of the groove.

In a further improvement of , the trench gate further includes a layer of gate conductive material filled in the trench in which the gate oxide layer is formed.

A further improvement of is that the semiconductor substrate comprises a silicon substrate.

A further improvement of is that the layer of gate conductive material comprises a polysilicon gate.

The improvement of is that the semiconductor device further comprises a body region doped with the second conductivity type, the body region is formed in the semiconductor substrate, a source region heavily doped with the conductivity type is formed on the surface of the body region, the trench penetrates through the body region, the surface of the body region covered by the side face of the gate conductive material layer is used for forming a channel, the thickness of the gate oxide layer on the side face of the trench is used for adjusting the threshold voltage of the device, and the thickness of the gate oxide layer on the bottom surface of the trench is used for improving the gate-source withstand voltage of the device.

In a further improvement of , the semiconductor device is a DMOS device and further includes a conductivity type heavily doped drain region formed in the back of the thinned semiconductor substrate.

, the oxide layer has a thickness of

In order to solve the above technical problem, the method for manufacturing a trench gate semiconductor device according to the present invention comprises the steps of:

step forms a trench in the semiconductor substrate.

And step two, forming an th oxidation layer on the bottom surface and the side surface of the groove by adopting a furnace tube thermal oxidation process.

And step three, forming a second oxide layer on the bottom surface and the side surface of the groove with the th oxide layer formed by adopting a PECVD process, and forming a gate oxide layer by overlapping the th oxide layer and the second oxide layer.

The thickness of the oxide layer grown on the bottom surface of the groove by the PECVD process is larger than that of the oxide layer grown on the side surface of the groove, so that the gate oxide layer has a structure that the thickness of the oxide layer on the bottom surface of the groove is larger than that of the oxide layer on the side surface of the groove.

And fourthly, performing RTA treatment on the gate oxide layer to ensure that the gate oxide layer is thermally compact.

A further improvement of step is that step four is followed by the step of:

and step five, filling a gate conductive material layer in the groove formed with the gate oxide layer.

A further improvement of is that the semiconductor substrate comprises a silicon substrate.

A further improvement of is that the layer of gate conductive material comprises a polysilicon gate.

The improvement of step is that it further comprises the steps of:

sixthly, forming a body region doped with a second conduction type in the semiconductor substrate;

the groove penetrates through the body region, the surface of the body region covered by the side face of the gate conductive material layer is used for forming a channel, the thickness of the gate oxide layer, located on the side face of the groove, is used for adjusting the threshold voltage of the device, and the thickness of the gate oxide layer, located on the side face of the groove, is used for improving the gate-source withstand voltage of the device.

And seventhly, forming a heavily doped source region of the conductive type on the surface of the body region.

In a further improvement of , the semiconductor device is a DMOS device, further comprising the steps of:

and step eight, thinning the semiconductor substrate, and forming an th conduction type heavily doped drain region on the back of the thinned semiconductor substrate.

, the oxide layer has a thickness of

The improvement of step is that the semiconductor device is an N-type device, the conductivity type is N-type, and the second conductivity type is P-type, or the semiconductor device is a P-type device, the conductivity type is P-type, and the second conductivity type is N-type.

The invention makes special improvement on the process structure of the gate oxide layer of the trench gate, the gate oxide layer is formed by overlapping th oxide layer and second oxide layer, wherein the th oxide layer adopts a furnace tube thermal oxide layer with better film forming quality, the second oxide layer adopts a PECVD oxide layer with film forming thickness of not samples on the bottom surface and the side surface of the trench, and finally the gate oxide layer has a structure that the thickness of the bottom surface of the trench is larger than the thickness of the side surface of the trench, the invention can also carry out thermal densification on the gate oxide layer so as to improve the quality of the thermally densified PECVD oxide layer, and the gate oxide layer structure of the invention has the following advantages:

firstly, the invention can ensure that the gate oxide layer with thinner side surface of the groove is provided, thereby not influencing the threshold voltage of the device and not influencing the control capability of the device channel.

Secondly, the thicker gate oxide layer on the bottom surface of the groove can be obtained, the gate oxide layer comprises a furnace tube thermal oxide layer with good quality, and the PECVD oxide layer is also subjected to thermal densification treatment, so that the quality and the thickness of the gate oxide layer on the bottom surface of the groove can be ensured at the same time, the bottom surface of the groove, particularly the bottom corner of the groove, can be well protected, and the BVGSS of the device can be improved and the reliability of the device can be improved.

In addition, the gate oxide layer of the invention can form a structure with the thickness of the bottom of the groove larger than that of the side surface by directly superposing two oxide layers without adding a photoetching process for definition, so the invention also has lower process cost.

Drawings

The invention is further described in detail in conjunction with the figures and the detailed description:

FIG. 1 is a schematic view of a trench gate of a trench-gate semiconductor device in accordance with an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a trench-gate semiconductor device according to an embodiment of the present invention using the trench gate shown in fig. 1;

FIGS. 3A-3F are schematic structural views of the device at various steps of a method of manufacturing a trench-gate semiconductor device in accordance with an embodiment of the present invention;

fig. 4A is an SEM photograph of a trench gate semiconductor device in accordance with an embodiment of the present invention;

FIG. 4B is an enlarged view of the bottom of the trench gate of FIG. 4A;

fig. 5 is a comparison graph of the BVGSS curve of the trench gate semiconductor device according to the embodiment of the present invention and the BVGSS curve of the conventional device.

Detailed Description

Fig. 1 is a schematic view of a trench gate semiconductor device according to an embodiment of the present invention; the trench gate of the trench gate semiconductor device in the embodiment of the invention comprises a trench 2 formed in a semiconductor substrate 1 and a gate oxide layer 101 formed on the bottom surface and the side surface of the trench 2.

The gate oxide layer 101 is formed by overlapping an th oxide layer 3 and a second oxide layer 4.

The th oxide layer 3 is a furnace tube thermal oxide layer.

The second oxide layer 4 is a PECVD oxide layer.

The gate oxide layer 101 has a thermally dense structure by RTA processing.

By utilizing the characteristic that the PECVD oxide layer formed in the trench 2 has the thickness of the bottom surface larger than the thickness of the side surface, the gate oxide layer 101 has a structure that the thickness d1 at the bottom surface of the trench 2 is larger than the thickness d2 at the side surface of the trench 2.

The trench gate further comprises a gate conductive material layer 5 filled in the trench 2 formed with the gate oxide layer 101.

In the embodiment of the present invention, the semiconductor substrate 1 includes a silicon substrate. The gate conductive material layer 5 is made of a polysilicon gate.

The semiconductor device is a DMOS device, as shown in FIG. 2, the semiconductor device is a structural schematic diagram of a trench gate semiconductor device of the embodiment of the invention adopting a trench gate shown in FIG. 1, the semiconductor device further comprises a body region 6 doped with a second conductive type, the body region 6 is formed in the semiconductor substrate 1, a source region 7 heavily doped with conductive type is formed on the surface of the body region 6, the trench 2 penetrates through the body region 6, the surface of the body region 6 covered by the side surface of the gate conductive material layer 5 is used for forming a channel, the thickness of the gate oxide layer 101, which is located on the side surface of the trench 2, is used for adjusting the threshold voltage of the device, and the thickness of the gate oxide layer 101, which is located on the bottom surface of the trench 2, is used for improving the gate-source.

The thickness of the th oxide layer 3 is

The semiconductor device further comprises a th conduction type heavily doped drain region 11, wherein the drain region 11 is formed on the back surface of the thinned semiconductor substrate 1.

Further comprising: an interlayer film 8, a contact hole 9 and a front metal layer 10, wherein the contact hole 9 penetrates through the interlayer film 8, the source region 7 is connected to a source electrode composed of the front metal layer 10 through the corresponding contact hole 9 at the top, and the gate conductive material layer 5 is connected to a gate electrode composed of the front metal layer 10 through the corresponding contact hole 9.

A drain electrode composed of a back metal layer 12 is formed on the back surface of the drain region 11.

In other embodiments, the semiconductor device is a P-type device, the conductivity type is P-type, and the second conductivity type is N-type.

The embodiment of the invention makes a special improvement on the process structure of the gate oxide layer 101 of the trench gate, and the gate oxide layer 101 is formed by overlapping a th oxide layer 3 and a second oxide layer 4, wherein the th oxide layer 3 adopts a furnace tube thermal oxide layer with better film-forming quality, and the second oxide layer 4 adopts a PECVD oxide layer with film-forming thickness of not samples on the bottom surface and the side surface of the trench 2, so that the gate oxide layer 101 has a structure that the thickness of the bottom surface of the trench 2 is larger than that of the side surface of the trench 2, and the embodiment of the invention can also carry out thermal densification on the gate oxide layer 101, so that the quality of the thermally densified PECVD oxide layer is improved, and the gate oxide layer 101 structure of the embodiment of the invention has the following advantages:

firstly, the embodiment of the invention can ensure that the gate oxide layer 101 with a thinner side surface of the groove 2 is provided, thereby not influencing the threshold voltage of the device and not influencing the control capability of the channel of the device.

Secondly, the embodiment of the invention can obtain the thicker gate oxide layer 101 on the bottom surface of the groove 2, the gate oxide layer 101 comprises a furnace tube thermal oxide layer with good quality, and the PECVD oxide layer is also subjected to thermal densification treatment, so that the quality and the thickness of the gate oxide layer 101 on the bottom surface of the groove 2 are ensured simultaneously, the bottom surface of the groove 2, particularly the bottom corner of the groove 2, can be well protected, and the BVGSS of the device can be improved and the reliability of the device can be improved.

In addition, the gate oxide layer 101 in the embodiment of the invention can form a structure in which the thickness d1 of the bottom of the trench 2 is greater than the thickness d2 of the side face by directly overlapping two oxide layers without adding a photoetching process for definition, so the embodiment of the invention also has lower process cost.

Fig. 4A is an SEM photograph of a trench gate semiconductor device according to an embodiment of the present invention; FIG. 4B is an enlarged view of the bottom of the trench gate of FIG. 4B; the thickness d1 of the gate oxide layer 101 at the bottom surface of the trench 2 is measured to beThe thickness d2 of the gate oxide layer 101 at the side of the trench 2 is

So d1 is greater than d 2; and the thickness of the gate oxide layer 101 at the corners of the trench 2 is also reached

The corner of the trench 2 is the weakest part of the trench gate, and the increase of the thickness of the gate oxide layer 101 at the corner of the trench 2 can improve the reliability of the device.

As shown in fig. 5, which is a comparison graph of the BVGSS curve of the trench-gate semiconductor device according to the embodiment of the present invention and the BVGSS curve of the conventional device, the curve 201 is the BVGSS curve of the conventional device, the curve 202 is the BVGSS curve of the trench-gate semiconductor device according to the embodiment of the present invention, VG represents the gate voltage of the device, IGSS represents the leakage current between the gate and the source of the device, IGSS suddenly increases to represent the gate-source breakdown, and the corresponding voltage is BVGSS, it can be seen that the BVGSS of the curve 202 is increased.

Fig. 3A to 3F are schematic structural diagrams of the device in each step of the method for manufacturing a trench-gate semiconductor device according to the embodiment of the present invention; the manufacturing method of the trench gate semiconductor device comprises the following steps:

step , as shown in fig. 3A, forms a trench 2 in the semiconductor substrate 1.

The semiconductor substrate 1 includes a silicon substrate.

Step two, as shown in fig. 3A, an th oxide layer 3 is formed on the bottom surface and the side surface of the trench 2 by using a furnace thermal oxidation process.

Step three, as shown in fig. 3A, forming a second oxide layer 4 on the bottom surface and the side surface of the trench 2 on which the -th oxide layer 3 is formed by a PECVD process, and forming a gate oxide layer 101 by overlapping the -th oxide layer 3 and the second oxide layer 4.

The thickness of the oxide layer grown on the bottom surface of the trench 2 by the PECVD process is greater than the thickness of the oxide layer grown on the side surface of the trench 2, so that the gate oxide layer 101 has a structure in which the thickness d1 on the bottom surface of the trench 2 is greater than the thickness d2 on the side surface of the trench 2.

And fourthly, as shown in fig. 3A, performing RTA treatment on the gate oxide layer 101 to thermally compact the gate oxide layer 101.

And step five, as shown in fig. 3B, filling a gate conductive material layer 5 in the trench 2 formed with the gate oxide layer 101.

The layer of gate conductive material 5 comprises a polysilicon gate.

Further comprising the steps of:

step six, as shown in fig. 3C, a body region 6 doped with the second conductivity type is formed in the semiconductor substrate 1. The trench 2 penetrates through the body region 6, the surface of the body region 6 covered by the side face of the gate conductive material layer 5 is used for forming a channel, the thickness of the gate oxide layer 101, which is located on the side face of the trench 2, is used for adjusting the threshold voltage of a device, and the thickness of the gate oxide layer 101, which is located on the side face of the trench 2, is used for improving the gate-source withstand voltage of the device.

In the method of the embodiment of the present invention, the thickness of the th oxide layer 3 is

Seventhly, as shown in fig. 3D, a th source region 7 with a heavily doped conductive type is formed on the surface of the body region 6.

The method also comprises the following front process:

forming an interlayer film 8;

forming a contact hole 9 through the interlayer film 8;

forming a front metal layer 10 and patterning the front metal layer 10 to form a source electrode and a grid electrode; the source region 7 is connected to the source electrode composed of a front metal layer 10 through the corresponding contact hole 9 at the top, and the gate conductive material layer 5 is connected to the gate electrode composed of a front metal layer 10 through the corresponding contact hole 9.

The semiconductor device is a DMOS device, and further comprises the steps of:

and step eight, thinning the semiconductor substrate 1, and forming an th conduction type heavily doped drain region 11 on the back surface of the thinned semiconductor substrate 1.

Forming a back metal layer 12, and forming a drain electrode by the back metal layer 12.

In the method of the embodiment of the present invention, the semiconductor device is an N-type device, the th conductivity type is an N-type, and the second conductivity type is a P-type.

The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.