阅读说明：本技术 半导体器件封装件和方法
(Semiconductor device package and method
) 是由 余振华
叶松峯
陈明发
陈宪伟
刘惠雯
袁景滨 于 2018-12-11 设计创作，主要内容包括：在实施例中,一种方法包括：堆叠多个第一管芯以形成器件堆叠件；暴露器件堆叠件的最顶部管芯的测试焊盘；使用最顶部管芯的测试焊盘测试器件堆叠件；以及在测试器件堆叠件之后,在最顶部管芯中形成接合焊盘,其中,接合焊盘与测试焊盘不同。本发明的实施例还涉及半导体器件封装件和方法。(In an embodiment, a method comprises: stacking a plurality of first die to form a device stack; exposing a test pad of a topmost die of the device stack; testing the device stack using the test pad of the topmost die; and forming a bond pad in the topmost die after testing the device stack, wherein the bond pad is different from the test pad. Embodiments of the invention also relate to semiconductor device packages and methods.)
1. A method of forming a semiconductor device, comprising:
stacking a plurality of first die to form a device stack;
exposing a test pad of a topmost die of the device stack;
testing the device stack using the test pads of the topmost die; and
after testing the device stack, forming a bond pad in the topmost die, wherein the bond pad is different from the test pad.
2. The method of claim 1, further comprising:
after testing the device stack, covering the test pads of the topmost die.
3. The method of claim 1, wherein stacking the plurality of first dies comprises:
bonding the topmost die to a first carrier substrate, wherein, during the bonding, the topmost die includes a dielectric layer over the test pad and is free of the bond pad;
stacking a bottommost die over the topmost die, wherein during the stacking, the topmost die comprises the bond pad and a dielectric layer over the bond pad.
4. The method of claim 3, wherein bonding the topmost die to the first carrier substrate comprises forming an oxide-to-oxide bond with the dielectric layer of the topmost die, and stacking the bottommost die over the topmost die comprises performing a hybrid bond with the bond pad of the bottommost die and the dielectric layer.
5. The method of claim 3, wherein stacking the plurality of first dies further comprises:
sealing the topmost die with a topmost sealing layer; and
after sealing the topmost die, sealing the bottommost die with a bottommost sealing layer.
6. The method of claim 5, wherein stacking the plurality of first dies further comprises:
sealing a topmost dummy device with the topmost sealing layer; and
after sealing the topmost dummy device, sealing a bottommost dummy device with the bottommost sealing layer.
7. The method of claim 6, further comprising:
forming alignment marks in the topmost dummy device and the bottommost dummy device.
8. The method of claim 7, further comprising:
forming an alignment mark in the first carrier substrate; and
aligning the alignment marks of the topmost and bottommost dummy devices with the alignment marks of the first carrier substrate.
9. A method of forming a semiconductor device, comprising:
bonding the first die to a first carrier substrate;
stacking a plurality of second dies and a plurality of dummy devices on the first die to form a device stack;
bonding a second carrier substrate to the plurality of second dies and the plurality of dummy devices of the device stack;
removing the first carrier substrate from the first die;
forming a conductive bump on the first die;
testing the first die and the device stack using the conductive bumps of the first die; and
singulating the second carrier substrate and portions of the dummy devices to form a first device package.
10. A semiconductor device, comprising:
a first die having a first function;
a device stack on the first die, the device stack comprising a plurality of layers, each layer comprising:
a second die having a second function;
a dummy device adjacent to the second die, the dummy device including an alignment mark; and
an encapsulant disposed between the dummy device and the second die; and
a first substrate on the device stack, the first substrate including an alignment mark.
Technical Field
Embodiments of the invention relate to semiconductor device packages and methods.
Background
With the development of Integrated Circuits (ICs), the semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this improvement in integration density comes from the ever-decreasing size of the smallest components, which allows more components to be integrated into a given area.
These integration improvements are two-dimensional (2D) in nature because the area occupied by the integrated components is substantially on the surface of the semiconductor wafer. The increased density and corresponding reduction in area of integrated circuits often exceeds the ability to bond integrated circuit chips directly to a substrate. Interposers have been used to redistribute the ball contact regions from the die to a larger area of the interposer. Furthermore, interposers have allowed for three-dimensional (3D) packages that include multiple chips. Other packages have also been developed to incorporate 3D aspects.
Disclosure of Invention
An embodiment of the present invention provides a method of forming a semiconductor device, including: stacking a plurality of first die to form a device stack; exposing a test pad of a topmost die of the device stack; testing the device stack using the test pads of the topmost die; and forming a bond pad in the topmost die after testing the device stack, wherein the bond pad is different from the test pad.
Another embodiment of the present invention provides a method of forming a semiconductor device, including: bonding the first die to a first carrier substrate; stacking a plurality of second dies and a plurality of dummy devices on the first die to form a device stack; bonding a second carrier substrate to the plurality of second dies and the plurality of dummy devices of the device stack; removing the first carrier substrate from the first die; forming a conductive bump on the first die; testing the first die and the device stack using the conductive bumps of the first die; and singulating portions of the second carrier substrate and the dummy device to form a first device package.
Still another embodiment of the present invention provides a semiconductor device including: a first die having a first function; a device stack on the first die, the device stack comprising a plurality of layers, each layer comprising: a second die having a second function; a dummy device adjacent to the second die, the dummy device including an alignment mark; and an encapsulant disposed between the dummy device and the second die; and a first substrate on the device stack, the first substrate including an alignment mark.
Drawings
The various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 is a cross-sectional view of an integrated circuit device according to some embodiments.
Fig. 2A-2L are various diagrams of intermediate steps during a process of forming a device package, according to some embodiments.
Fig. 3 is a cross-sectional view of a dummy device according to some embodiments.
Fig. 4A-4D are plan views of alignment marks according to various embodiments.
Fig. 5A-5J are various diagrams of intermediate steps during a process of forming a device package, according to some embodiments.
Fig. 6A and 6B illustrate variations of device packages according to various embodiments.
Fig. 7A-7C are top views illustrating a device stack at different stages of fabrication according to various embodiments.
Fig. 8A-8C are plan views of device package layers according to some embodiments.
Fig. 9A-9H are various diagrams of intermediate steps during a process of forming a device package, according to some embodiments.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Also, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
According to some embodiments, a device stack is formed on a carrier substrate. The device stack may be, for example, a memory cube including a plurality of memory dies. The device stack is then removed from the carrier substrate and tested using the dedicated test pads. Only good device stacks are known for subsequent processing, which may improve manufacturing yield. Further, in some embodiments, dummy devices are added to the device stack layers. The dummy device may improve heat dissipation of the device stack. Finally, in some embodiments, the dummy device includes an alignment mark. By using dummy devices for alignment, alignment marks may be omitted from the die of the device stack, which may increase the available routing area of the die.
Fig. 1 is a cross-sectional view of an integrated circuit device 50 according to some embodiments. The integrated circuit device 50 may be a logic die (e.g., a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a system on chip (SoC), a microcontroller, etc.), a memory die (e.g., a Dynamic Random Access Memory (DRAM) die, a Static Random Access Memory (SRAM) die, etc.), a power management die (e.g., a Power Management Integrated Circuit (PMIC) die), a Radio Frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a Digital Signal Processing (DSP) die), a front end die (e.g., an Analog Front End (AFE) die), etc., or combinations thereof, the integrated circuit device 50 may be formed in a wafer (not shown), wherein the wafer may include different device regions that are singulated to form a plurality of integrated circuit devices 50 in subsequent steps, the integrated circuit device 50 is to be stacked to form a device package in subsequent processing, the integrated circuit device 50 includes a substrate 52, a plurality of integrated circuit devices 50, a plurality of integrated circuit, Conductive via 54, interconnect structure 56, test pad 58, dielectric layer 60, bond pad 62, and conductive via 64.
The substrate 52 may include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multilayer semiconductor substrate, or the like. The semiconductor material of the substrate 52 may be silicon, germanium, a compound semiconductor including silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. Other substrates such as multilayer substrates or gradient substrates may also be used. The substrate 52 may be doped or undoped. Devices (not shown) such as transistors, capacitors, resistors, diodes, and the like may be formed in and/or on an active surface (e.g., an upward facing surface) of substrate 52.
Conductive vias 54 are formed to extend from the active surface of substrate 52 into substrate 52. In some embodiments, the conductive vias 54 do not extend to the back side of the substrate 52 (e.g., face down, the surface opposite the active surface) when initially formed. Conductive vias 54 are also sometimes referred to as through-substrate vias or, when substrate 52 is a silicon substrate, as through-silicon vias (TSVs). The conductive vias 54 may be formed by forming grooves in the substrate 52, for example, by etching, milling, laser techniques, combinations thereof, and the like. A thin dielectric material may be formed in the recess, such as by using an oxidation technique. A thin barrier layer can be conformally deposited over the active surface of the substrate 52 and in the openings, such as by CVD, ALD, PVD, thermal oxidation, combinations thereof, and the like. The barrier layer may be formed of an oxide, nitride, or oxynitride such as titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, combinations thereof, or the like. A conductive material may be deposited over the barrier layer and in the opening. The conductive material can be formed by an electrochemical plating process, CVD, ALD, PVD, combinations thereof, and the like. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, combinations thereof, and the like. Excess conductive material and barrier layer are removed from the active surface of substrate 52 by, for example, Chemical Mechanical Polishing (CMP). The conductive vias 54 collectively include a barrier layer and a conductive material, wherein the barrier layer is located between the conductive material and the substrate 52.
An interconnect structure 56 having one or more dielectric layers and corresponding metallization patterns is formed over the conductive vias 54 on the active surface of the substrate 52. The dielectric layer may be an inter-metal dielectric (IMD) layer. For example, low-K dielectric materials, such as undoped silicate glass, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiO, may be formed from low-K dielectric materials by any suitable method known in the art, such as spin-on coating, Chemical Vapor Deposition (CVD), plasma-enhanced CVD (pecvd), high-density plasma chemical vapor deposition (HDP-CVD)xCySpin-on glass, spin-on polymer, silicon carbon material, compounds thereof, composites thereof, combinations thereof, etc.) to form the IMD layer. The one or more metallization patterns in the one or more dielectric layers may route electrical signals between devices of the substrate 52, such as through the use of vias and/or traces, and may also include various electronic devices such as capacitors, resistors, inductors, and the like. In addition, conductive vias 54 are electrically connected to the metallization pattern. The metallization pattern may be made of, for example, copperAluminum, or the like, or combinations thereof. The various devices and metallization patterns may be interconnected to implement one or more functions. The functions may include memory structures, processing structures, sensors, amplifiers, power dividers, input/output circuits, and the like. Additionally, connections, such as conductive pillars or contact pads, are formed in and/or on the interconnect structure 56 to provide external electrical connections to the circuitry and devices. The above examples are provided for illustrative purposes only, and other embodiments may use fewer or additional elements. Other circuits may be used as appropriate for a given application.
Test pads 58 are a subset of connections formed in and/or on interconnect structure 56. The test pads 58 are used for subsequent device testing steps and are not electrically connected or active during normal operation of the integrated circuit device 50. In some embodiments, test pads 58 are formed of a lower cost conductive material (e.g., aluminum) than the conductive material of the metallization patterns in interconnect structure 56.
Dielectric layer 60 covers test pad 58 and is located over interconnect structure 56. Dielectric layer 60 comprises one or more layers of non-photopatternable dielectric material such as silicon nitride, silicon oxide, and the like. In some embodiments, the dielectric layer 60 is subsequently used for bonding and may be an oxide such as silicon oxide. The dielectric layer 60 may be formed using CVD, PVD, ALD, spin-on processes, combinations thereof, and the like.
Bond pads 62 are formed in dielectric layer 60 and are physically and electrically connected to interconnect structure 56 by conductive vias 64. The bond pads 62 and the conductive vias 64 comprise a conductive material, wherein the conductive material may be a metallic material comprising a metal or metal alloy such as copper, silver, gold, tungsten, cobalt, aluminum, or alloys thereof. In some embodiments, bond pads 62 and conductive vias 64 are formed using a dual damascene process. As an example of such a process, openings for bond pads 62 and conductive vias 64 may be formed in dielectric layer 60, a thin seed layer deposited in the openings, and a conductive material filled in the openings from the seed layer using, for example, ECP or electroless plating. A planarization process such as CMP may be performed so that the bond pad 62 and the top surface of the dielectric layer 60 are flush. In some embodiments, the bond pads 62 and the test pads 58 are formed of different conductive materials.
Fig. 2A-2L are various cross-sectional views of intermediate steps during a process of forming a device package, according to some embodiments. As will be discussed in more detail below, fig. 2A-2L illustrate a process of forming a device stack 102 by stacking a plurality of first integrated circuit devices (such as the integrated circuit device 50 shown in fig. 1), and in an embodiment, the first integrated circuit devices may be memory dies. The device stack 102 is formed in a top-down (or reverse) manner, wherein the topmost device of the first integrated circuit device 50 is attached face-down to the carrier, and the underlying layers of the device stack 102 are subsequently attached to the topmost device. The device stack 102 is tested after formation to reduce or prevent subsequent processing of known bad chip stacks.
Subsequently, the device stack 102 is attached to a second integrated circuit device 120 (see, e.g., fig. 2I) to form a first device package 100 (see, e.g., fig. 2I). The second integrated circuit device 120 may have a similar structure as the integrated circuit device 50, and in embodiments the second integrated circuit device 120 may be a logic die. In an embodiment, the first device package 100 is a chip on wafer (CoW) package, but it should be understood that the embodiments may be applied to other 3DIC packages. A second device package 150 is then formed by mounting the first device package 100 to a substrate (see, e.g., fig. 2L). In an embodiment, the second device package 150 is a chip on wafer on substrate (CoWoS) package, but it should be understood that embodiments may be applied to other 3DIC packages.
Referring now to fig. 2A, a bonding layer 106 is deposited on the first carrier substrate 104, and the topmost integrated circuit device 50A is attached to the bonding layer 106. The first carrier substrate 104 may be a glass carrier substrate, a ceramic carrier substrate, a silicon wafer, or the like. Multiple device packages may be formed simultaneously on the first carrier substrate 104. The bonding layer 106 may be used to attach the topmost integrated circuit device 50A to the first carrier substrate 104. In some embodiments, the first carrier substrate 104 is a silicon wafer. In such embodiments, the bonding layer 106 includes a silicon-containing dielectric material such as silicon oxide or silicon nitride, and may be formed using CVD, PVD, spin coating, or the like. The dielectric material may be used for bonding, such as oxide-to-oxide bonding, where the dielectric layer 60 of the topmost integrated circuit device 50A is bonded to the bonding layer 106. In some embodiments, the first carrier substrate 104 is glass. In such embodiments, the bonding layer 106 includes a release layer such as a light-to-heat conversion (LTHC) release coating, an Ultraviolet (UV) glue, or the like. The release layer may be an adhesive and may be used to adhere the topmost integrated circuit device 50A to the first carrier substrate 104. The topmost integrated circuit device 50A may be tested prior to attachment, such that only known good dies are used to form the device stack 102.
The topmost integrated circuit device 50A may be similar to the integrated circuit device 50 discussed above with reference to fig. 1, except that the bond pads 62 and conductive vias 64 are not formed prior to adhering to the first carrier substrate 104. As will be discussed further below, the device stack 102 is tested after being formed. Because the topmost integrated circuit device 50A is located at the topmost level of the device stack 102, the test pads 58 of the topmost integrated circuit device 50A will be used for device testing. The bond pads 62 and conductive vias 64 of the topmost integrated circuit device 50A may be formed after testing to prevent damage to the bond pads 62 during testing.
In fig. 2B, a topmost encapsulant 110A is formed around the topmost integrated circuit device 50A and over the first carrier substrate 104. The topmost encapsulant 110A may be a molding compound, epoxy, or the like, and may be applied by compression molding, transfer molding, or the like. A topmost encapsulant 110A may be formed over the topmost integrated circuit device 50A and the first carrier substrate 104 such that they are buried or covered. The topmost encapsulant 110A is then cured. The topmost encapsulant 110A and topmost integrated circuit device 50A are thinned, for example by CMP, to expose the conductive vias 54 of the topmost integrated circuit device 50A. After thinning, the surfaces of the topmost encapsulant 110A and conductive vias 54 are flush with the backside of the topmost integrated circuit device 50A.
In fig. 2C, the middle integrated circuit device 50B is attached to the topmost integrated circuit device 50A. In particular, the active surface of the middle integrated circuit device 50B is attached to the back surface of the topmost integrated circuit device 50A. Unlike the topmost integrated circuit device 50A, the intermediate integrated circuit device 50B does include bond pads 62 and conductive vias 64 when adhered to the topmost integrated circuit device 50A. The intermediate integrated circuit device 50B may be tested prior to attachment, such that only known good dies are used to form the device stack 102.
In some embodiments, integrated circuit devices 50A and 50B are attached by hybrid bonding. Before bonding is performed, surface treatment may be performed on the integrated circuit devices 50A and 50B. The surface treatment may be a plasma treatment process, and the process gas for generating plasma may be a hydrogen-containing gas, wherein the hydrogen-containing gas includes a hydrogen-containing gas (H)2) And argon (Ar) gas, H2And nitrogen (N)2) Or a second gas containing H2And a third gas of helium (He). By this treatment, the number of OH groups at the surface of the dielectric layer 60 increases. Next, a pre-bonding process may be performed in which the integrated circuit devices 50A and 50B are aligned. Integrated circuit devices 50A and 50B are pressed together to form a weak bond between substrate 52 of topmost integrated circuit device 50A and dielectric layer 60 of middle integrated circuit device 50B. After the pre-bonding process, the integrated circuit devices 50A and 50B are annealed to strengthen the weak bonds and form fusion bonds. During the anneal, the OH bonds are H-removed, thereby forming Si-O-Si bonds between the integrated circuit devices 50A and 50B, thereby strengthening the bonds. During hybrid bonding, direct metal-to-metal bonding also occurs between conductive via 54 of topmost integrated circuit device 50A and bond pad 62 of intermediate integrated circuit device 50B. Thus, the resulting bond is a hybrid bond that includes both Si-O-Si bonds and metal-metal direct bonds.
In fig. 2D, an intermediate encapsulant 110B is formed around the intermediate integrated circuit device 50B and over the first carrier substrate 104. The middle encapsulant 110B may be formed of a material selected from candidate materials for the topmost encapsulant 110A, or may include a different material. The intermediate sealant 110B may be formed by a method selected from candidate methods of forming the topmost sealant 110A, or may be formed by a different method.
In fig. 2E, the above steps are repeated until the device stack 102 includes a bottommost integrated circuit device 50C surrounded by a bottommost encapsulant 110C. Bottommost integrated circuit device 50C may not be thinned such that conductive vias 54 of bottommost integrated circuit device 50C remain electrically isolated. The bottommost integrated circuit device 50C may be tested prior to attachment, such that only known good dies are used to form the device stack 102.
It should be understood that the device stack 102 may include any number of layers. In the illustrated embodiment, the device stack 102 includes three layers. In another embodiment, the device stack 102 includes two or more layers.
In fig. 2F, the device stack 102 is removed from the first carrier substrate 104, the device stack 102 is flipped over and the device stack 102 is attached to the second carrier substrate 112. In embodiments where the first carrier substrate 104 is a silicon wafer and the bonding layer 106 is a dielectric layer, the removal may be accomplished by etching or grinding away the silicon wafer and dielectric layer. In embodiments where the first carrier substrate 104 is glass and the adhesive layer 106 is a release layer, removal may be achieved by projecting light, such as laser or UV light, onto the release layer, such that under the heat of the light the release layer decomposes and debonds the glass. The second carrier substrate 112 may be a silicon wafer, and the device stack 102 may be attached to the second carrier substrate 112 by a bond, such as an oxide-to-oxide bond, using a bonding layer 114. Bonding layer 114 may be an oxide such as silicon oxide that is compatible with fusion bonding. Bonding layer 114 may be applied to the backside of device stack 102 (such as to the backside of bottommost integrated circuit device 50C), such as by CVD, or may be applied over the surface of second carrier substrate 112.
In fig. 2G, the device stack 102 is tested by using the probes 116. Test pads 58 of topmost integrated circuit device 50A are exposed by patterning dielectric layer 60 of topmost integrated circuit device 50A to form openings 118. Dielectric layer 60 may be patterned using suitable photolithography and etching methods. In some embodiments, a photoresist material (not shown) is formed over the dielectric layer 60. Subsequently, the photoresist material is irradiated (exposed) and developed to remove portions of the photoresist material. Subsequently, the exposed portions of the dielectric layer 60 are removed, for example, using a suitable etch process to form the openings 118. The probes 116 are then physically and electrically connected to the test pads 58 exposed by the openings 118. The test pads 58 are used to test the device stack 102 so that only good device stacks are known for further processing. Testing may include testing the functionality of individual integrated circuit devices, or may include testing known opens or shorts that are anticipated based on the design of the integrated circuit device. During testing, all integrated circuit devices of device stack 102 may be tested in a daisy-chain (daisy-chain) manner.
In fig. 2H, the probes 116 are removed and the openings 118 are filled. The opening 118 may be filled by forming (e.g., depositing) more dielectric material of the dielectric layer 60 in the opening 118, and performing a planarization, such as a CMP, to remove excess dielectric material outside the opening 118. Bond pads 62 and conductive vias 64 are then formed in dielectric layer 60 of topmost integrated circuit device 50A using the techniques described above. Notably, the bond pads 62 are different from the test pads 58. After testing is complete, test pads 58 may remain unused in the topmost integrated circuit device 50A.
In fig. 2I, a second integrated circuit device 120 is attached to the device stack 102, thereby forming the first device package 100. The second integrated circuit device 120 may perform different functions than the integrated circuit devices 50A, 50B, and 50C. For example, the integrated circuit devices 50A, 50B, and 50C may be memory devices, and the second integrated circuit device 120 may be a logic device (e.g., a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a system on a chip (SoC), a microcontroller, etc.). The second integrated circuit device 120 may be attached to the topmost integrated circuit device 50A by hybrid bonding using the dielectric layer 60 and the bond pads 62 of the topmost integrated circuit device 50A. An encapsulant 121 may be formed around the second integrated circuit device 120 and over the device stack 102. The sealant 121 may be formed of a material selected from candidate materials of the topmost sealant 110A, or may include a different material. The sealant 121 may be formed by a method selected from candidate methods of forming the topmost sealant 110A, or may be formed by a different method.
In fig. 2J, the first device package 100 is tested by using the probe 122. The first device package 100 is tested using the test pads 58 of the second integrated circuit device 120. Openings 124 may be formed that expose the test pads 58 of the second integrated circuit device 120, and the second integrated circuit device 120 may be tested using a method similar to that used for testing the device stack 102. Testing may include testing the functionality of the integrated circuit devices of the first device package 100, or may include testing known open or short circuits expected based on the design of the integrated circuit devices.
In fig. 2K, the probes 122 are removed and the openings 124 are filled. Opening 124 may be filled using a method similar to that of filling opening 118. Bumps 126 are then formed on the second integrated circuit device 120 and conductive connections 128 are formed on the bumps 126.
Bumps 126 may be metal posts, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed by electroless nickel palladium immersion gold (ENEPIG), Ball Grid Array (BGA) bumps, and the like. In an embodiment, the bump 126 is a C4 bump. The bump 126 may be formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The bumps 126 may be solder-free and have substantially vertical sidewalls. In some embodiments, a metal cap layer (not shown) is formed on top of the bump 126. The metal capping layer may include nickel, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or the like, or a combination thereof and may be formed by a plating process.
The conductive connection 128 may be formed of a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive connection 128 is formed by first forming a solder layer by methods such as evaporation, plating, printing, solder transfer, ball placement, and the like. Once the solder layer has been formed on the structure, reflow may be performed to shape the conductive connections 128 into the desired bump shape. In some embodiments, both the bump 126 and the conductive connection 128 may be solder.
Once the formation of the first device package 100 is complete, the first device package 100 is singulated from adjacent device packages formed on the same carrier wafer. The singulation may be performed by, for example, sawing or laser cutting. In some embodiments, the second carrier substrate 112 remains after singulation. As will be discussed further below, the second carrier substrate 112 facilitates heat dissipation of the first device package 100. In some embodiments, the second carrier substrate 112 may be removed and, optionally, other structures such as a cooling system may be attached. In the illustrated embodiment, the conductive vias 54 of the topmost integrated circuit device 50A are electrically isolated in the first device package 100. These conductive vias 54 may be unused so that the same die may be used for stacking in the device stack 102.
In fig. 2L, a second device package 150 is formed by mounting the first device package 100 to a package substrate 152. The package substrate 152 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, and the like may also be used. Additionally, the package substrate 152 may be an SOI substrate. Typically, the SOI substrate comprises a layer of semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In an alternative embodiment, the package substrate 152 is based on an insulating core, such as a fiberglass reinforced resin core. One exemplary core material is a fiberglass resin such as FR 4. Alternative materials for the core material include bismaleimide-triazine BT resin, or alternatively, other PCB materials or films. A build-up film such as ABF or other laminate may be used for the package substrate 152.
The package substrate 152 may include active and passive devices (not shown). A variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to create structural and functional requirements for the design of the second device package 150. Any suitable method may be used to form the device.
The package substrate 152 may also include metallization layers and vias (not shown) and bond pads 154 over the metallization layers and vias. Metallization layers may be formed over the active and passive devices and designed to connect the various devices to form functional circuitry. The metallization layer may be formed of alternating layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material, and may be formed by any suitable process, such as deposition, damascene, dual damascene, etc. In some embodiments, the package substrate 152 is substantially free of active and passive devices.
In some embodiments, the conductive connections 128 are reflowed to attach the first device package 100 to the bond pads 154 to bond the second integrated circuit device 120 to the package substrate 152. The conductive connections 128 electrically and/or physically connect the package substrate 152 (including metallization layers in the package substrate 152) to the first device package 100. In some embodiments, a passive device (e.g., a Surface Mount Device (SMD), not shown) may be attached to the second device package 150 (e.g., bonded to the bond pads 154) prior to mounting the passive device to the package substrate 152. In such embodiments, the passive devices may be bonded to the same surface of the second device package 150 as the conductive connections 128.
The conductive connections 128 may have epoxy solder (not shown) formed thereon before reflowing the conductive connections 128 with at least some of the epoxy portion of the epoxy solder remaining after the second device package 150 is attached to the package substrate 152. The remaining epoxy portion may be used as an underfill to reduce stress and protect the joints created by reflowing the conductive connections 128.
An underfill (not shown) may be formed between the second integrated circuit device 120 and the package substrate 152, surrounding the conductive connection 128. The underfill may be formed by a capillary flow process after attaching the first device package 100, or may be formed by a suitable deposition method before attaching the first device package 100.
Fig. 3 is a cross-sectional view of a dummy device 300 according to some embodiments. The dummy device 300 does not perform an electrical function and no active device or passive device is formed therein. Rather, as will be discussed further below (e.g., with respect to the embodiments of fig. 5A-5J and the embodiments of fig. 9A-9H), dummy device 300 may be included in an embodiment device package (e.g., device packages 550 and 950, see below) to improve heat dissipation of the final package. The dummy device 300 includes a substrate 302, an isolation film 304, an etch stop layer 306, an inter-metal dielectric (IMD) layer 308, an alignment mark 310, and a bonding film 312.
An isolation film 304 is formed on the substrate 302. Substrate 302 may be formed of a material selected from candidate materials for substrate 52, or may comprise a different material. The substrate 302 may be formed by a method selected from candidate methods of forming the substrate 52, or may be formed by a different method. The isolation film 304 helps to electrically isolate the alignment marks 310. The isolation film 304 may be formed of a dielectric material such as silicon carbide, silicon nitride, or the like, and may be formed by CVD, PVD, or the like. In an embodiment, the isolation diaphragm 304 is formed to be less than about
Is measured.
An etch stop layer 306 is formed on the isolation film 304. The etch stop layer 306 may be formed of silicon carbide, silicon nitride, silicon oxynitride, silicon carbonitride, or the like. The etch stop layer 306 may be formed by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), spin-on dielectric process, the like, or combinations thereof. In an embodiment, the etch stop layer 306 is formed to have a thickness from about
To about
Is measured.
An IMD layer 308 is formed over the etch stop layer 306. IMD layer 308 may be a layer formed from a low-k dielectric material having a k value less than about 3.0. IMD layer 308 may be derived from a super-high k value of less than 2.5Low k (elk) dielectric materials. In some embodiments, IMD layer 308 may be formed from Black Diamond (a registered trademark of applied materials corporation), oxygen-and/or carbon-containing low-k dielectric materials, Hydrogen Silsesquioxane (HSQ), Methyl Silsesquioxane (MSQ), and the like. IMD layer 308 may be a porous material. IMD layer 308 may also be from a dielectric material such as silicon nitride, silicon oxide, etc. In an embodiment, IMD layer 308 is formed to have a thickness from about
To about
Is measured. In some embodiments, the materials of
etch stop layer 306 and
IMD layer 308 are selected to achieve a high etch selectivity between
etch stop layer 306 and
IMD layer 308, and thus etch
stop layer 306 may be used to stop etching of
IMD layer 308 in subsequent processing steps.
The alignment mark 310 is formed in the IMD layer 308 and may extend through the etch stop layer 306 and the isolation film 304. The alignment mark 310 may be formed using a single damascene process. As an example of forming the alignment mark 310, an opening (not shown) may be formed in the IMD layer 308 by an etching process. The etch process may remove material of IMD layer 308 and may not remove material of etch stop layer 306. Once the etch stop layer 306 is exposed, a different etch process may be performed to extend the opening through the etch stop layer 306. The opening may also extend at least partially into the isolation diaphragm 304. One or more diffusion barrier layers (not shown) are optionally formed in the openings, and then a conductive material is formed over the diffusion barrier layers (if present). The diffusion barrier layer may be formed of TaN, Ta, TiN, Ti, CoW, or the like, and may be formed in the opening by a deposition process such as ALD or the like. The conductive material may include copper, aluminum, tungsten, silver, combinations thereof, and the like, and may be formed over the diffusion barrier layer located in the opening by an electrochemical plating process, CVD, ALD, PVD, the like, or combinations thereof. In an embodiment, the conductive material is copper, and the diffusion barrier is a thin barrier layer that prevents copper from diffusing into IMD layer 308. After the diffusion barrier and the conductive material are formed, excess diffusion barrier and conductive material may be removed by, for example, a planarization process such as CMP.
A bonding film 312 is formed on the alignment mark 310 and the IMD layer 308. The bonding film 312 is used for bonding such as oxide-to-oxide bonding in a subsequent step, and is formed of a material that can be used to form oxide-to-oxide bonding with a semiconductor substrate. In an embodiment, the bonding film 312 is formed of an oxide such as silicon oxide, and may be formed using CVD, PVD, ALD, spin-on process, a combination thereof, or the like. In an embodiment, the bonding film 312 is formed to have a thickness of from about 0.8 μm to about 2 μm.
Fig. 4A-4D are plan views of alignment marks 310 according to various embodiments. As shown, the alignment mark 310 may be formed to have various shapes in a plan view. For example, the alignment mark 310 may have a closed square shape (see fig. 4A), a circular shape (see fig. 4B), a cross shape (see fig. 4C), or an open square shape (see fig. 4D). It should be understood that other shapes may be used.
Fig. 5A-5J are various cross-sectional views of intermediate steps during a process of forming a device package, according to some embodiments. In fig. 5A to 5J, a device stack 502 is formed by stacking a plurality of dummy devices (such as the dummy device 300 described above with reference to fig. 3 and 4A to 4D) and a first integrated circuit device (such as the integrated circuit device 50 described above with reference to fig. 1). Device stack 502 may be tested after formation. A subsequent device package is then formed with device stack 502. Forming device stack 502 with dummy device 300 facilitates heat dissipation of the resulting device package. In addition, the alignment mark 310 in the dummy device 300 may improve device stacking accuracy in subsequent processes. The device package may be a CoW or CoWoS package, but it is understood that the embodiments may be applied to other 3DIC packages.
Referring first to fig. 5A, a plurality of topmost integrated circuit devices 50A and dummy devices 300A are adhered to a first carrier substrate 508. In some embodiments, the topmost integrated circuit device 50A is free of bond pads when adhered to the first carrier substrate 508. The topmost integrated circuit device 50A may be tested prior to attachment, such that only known good dies are used to form the device stack 502.
The first carrier substrate 508 may be formed of a silicon wafer or the like, and alignment marks 510 are formed in or above the silicon wafer. The alignment mark 510 may be formed in a similar manner as the alignment mark 310 of the dummy device 300A.
The topmost integrated circuit device 50A and the dummy device 300A are placed face down on the first carrier substrate 508 and adhered to the dielectric layer 60 and the bonding film 312, respectively, using a bond such as an oxide-to-oxide bond. The placement may be performed by, for example, a pick and place process. During placement, the alignment marks 310 of the dummy devices 300A are aligned with the alignment marks 510 of the first carrier substrate 508, which may allow for more accurate placement during pick and place processes. The corners of the topmost integrated circuit device 50A may be aligned during pick and place. In some embodiments, the integrated circuit device 50A is placed before the dummy device 300A. In some embodiments, the dummy device 300A is placed before the integrated circuit device 50A. Details regarding how the alignment marks 310 are used will be discussed in further detail below.
In fig. 5B, a topmost encapsulant 514A is formed around the topmost integrated circuit device 50A, the dummy device 300A, and over the first carrier substrate 508. The topmost encapsulant 514A may be formed of a material selected from candidate materials for the topmost encapsulant 110A (see fig. 2B), or may include a different material. The topmost encapsulant 514A may be formed by a method selected from candidate methods of forming the topmost encapsulant 110A, or may be formed by a different method. The topmost encapsulant 514A, topmost integrated circuit device 50A, and dummy device 300A are thinned, for example by CMP, to expose the conductive vias 54 of the topmost integrated circuit device 50A.
In fig. 5C, the above steps are repeated to form additional layers of device stack 502. Middle integrated circuit device 50B and dummy device 300B are attached to topmost integrated circuit device 50A and dummy device 300A. Likewise, the bottommost integrated circuit device 50C and the dummy device 300C are attached to the middle integrated circuit device 50B and the dummy device 300B. The middle integrated circuit device 50B and the bottommost integrated circuit device 50C, when adhered, include bond pads 62. In this way, the integrated circuit devices of each layer are attached to the underlying layer by hybrid bonding. Each integrated circuit device may be tested prior to attachment, such that only known good dies are used to form device stack 502.
It should be understood that device stack 502 may include any number of layers. In the illustrated embodiment, device stack 502 includes four layers (e.g., a topmost integrated circuit device 50A and a dummy device 300A; two layers of middle integrated circuit devices 50B and dummy devices 300B; and a bottommost integrated circuit device 50C and dummy device 300C). In another embodiment, device stack 502 includes a greater or lesser number of layers, such as five layers or two layers.
In fig. 5D, a second carrier substrate 516 is attached to device stack 502 with a bond, such as an oxide-to-oxide bond, using a bonding layer 518. The second carrier substrate 516 may be formed of a silicon wafer or the like, and the alignment marks 520 are formed in or above the silicon wafer. The alignment marks 520 may be formed in a similar manner as the alignment marks 310 of the dummy device 300A. The alignment marks 520 of the second carrier substrate 516 are aligned with the alignment marks 310 of the dummy devices 300A, 300B, and 300C, thereby making it possible to more accurately place the second carrier substrate 516. The bonding layer 518 may be formed of a material selected from candidate materials for the bonding layer 114, or may include a different material. The bonding layer 518 may be formed by a method selected from candidate methods for forming the bonding layer 114 (see fig. 2F), or may be formed by a different method. In an embodiment, the bonding layer 518 is an oxide, such as silicon oxide, that is compatible with oxide-to-oxide bonding.
In fig. 5E, device stack 502 is removed from first carrier substrate 508 and device stack 502 is flipped over. In embodiments where the first carrier substrate 508 is a silicon wafer and the bonding layer 518 is a dielectric layer, the removal may be accomplished by etching or grinding away the silicon wafer and dielectric layer. Device stack 502 may then be tested such that only known good device stacks are used for further processing. Similar to device stack 102, topmost integrated circuit device 50A may include test pads (not shown) for testing. The test pads for testing may be exposed and then covered after testing to electrically isolate them. The test pads may be formed of a different material than the bond pads 62.
In fig. 5F, bond pads 62 are formed in dielectric layer 60 of topmost integrated circuit device 50A. After testing, bond pads 62 may be formed by a dual damascene process. Notably, the bond pads 62 are different from the test pads 58 (not shown in fig. 5F, but shown above in fig. 1).
In fig. 5G, a second integrated circuit device 522 is attached to the device stack 502 by hybrid bonding with the bond pads 62 of the topmost integrated circuit device 50A, forming the first device package 500. The second integrated circuit device 522 may perform different functions than the integrated circuit devices 50A, 50B, and 50C. Prior to attachment, the second integrated circuit device 522 may be tested such that only known good dies are used to form the first device package 500.
An encapsulant 524 is formed around the second integrated circuit device 522. The sealant 524 may be formed of a material selected from candidate materials of the topmost sealant 110A (see fig. 2B), or may include a different material. The sealant 524 may be formed by a method selected from candidate methods of forming the topmost sealant 110A, or may be formed by a different method. The encapsulant 524 and the second integrated circuit device 522 are thinned, for example by CMP, so that they have flush surfaces.
In fig. 5H, an opening is formed in the dielectric layer 60 of the second integrated circuit device 522, and a bump 526 is formed in the opening. The bump 526 may be formed of a material selected from candidate materials for the bump 126 (see fig. 2K), or may include a different material. The bump 526 may be formed by a method selected from candidate methods of forming the bump 126, or may be formed by a different method.
Conductive connections 528 are then formed over bumps 526. The conductive connection 528 may be formed of a material selected from candidate materials for the conductive connection 128 (see fig. 2K), or may comprise a different material. The conductive connection 528 may be formed by a method selected from candidate methods of forming the conductive connection 128, or may be formed by a different method. The first device package 500 may then be probe tested using the conductive connections 528 such that only known good devices are used for further processing.
In fig. 5I, the first device package 500 is singulated from adjacent device packages. Singulation may be performed along scribe lines 530 by, for example, sawing or laser cutting. Although not shown, it should be understood that the alignment marks 520 of the second carrier substrate 516 may be disposed along scribe lines 530. As such, the singulation process may result in cutting or removing some of the alignment marks 520 such that the portion of the second carrier substrate 516 in the first device package 500 has a fragment or portion of the alignment marks 520.
In fig. 5J, a second device package 550 is formed by mounting the first device package 500 to a package substrate 552. Package substrate 552 may be similar to package substrate 152 (see fig. 2L). Package substrate 552 may include metallization layers and vias (not shown) and bond pads 554 over the metallization layers and vias. Conductive connections 528 of first device package 500 are connected to bond pads 554 of package substrate 552 to form second device package 550.
The dummy devices 300A, 300B, and 300C may form a thermal path between the second integrated circuit device 522 and the second carrier substrate 516. In this way, heat dissipation of the resulting second device package 550 may be improved. Further, by forming the alignment mark 310 in the dummy devices 300A, 300B, and 300C, the alignment mark may be omitted from the integrated circuit devices 50A, 50B, and 50C. The available routing area in each integrated circuit device can be increased.
Fig. 6A and 6B illustrate variations of the second device package 550 according to various embodiments. In a first modification (e.g., fig. 6A), the dummy device may be omitted. As such, only the second carrier substrate 516 includes the alignment marks 520 located in the second device package 550. During formation, the alignment marks 520 of the second carrier substrate 516 may be aligned with the alignment marks 510 (see fig. 5D) of the first carrier substrate 508. In a second variation (e.g., fig. 6B), the dummy device 300 and the alignment mark 310 may be omitted. The variant shown can have a low manufacturing cost.
Fig. 7A-7C are top views illustrating device stack 502 at different stages of fabrication according to various embodiments. In the illustrated example, fig. 7A may correspond to placing a topmost integrated circuit device 50A (as shown in fig. 5A), fig. 7B may correspond to placing a topmost dummy device 300A (as shown in fig. 5A), and fig. 7C may correspond to placing an intermediate integrated circuit device 50B and dummy device 300B (as shown in fig. 5C). The use of alignment marks 310 and 510 is shown. In fig. 7A, a first layer of integrated circuit devices 50 is placed over a first carrier substrate 508. The alignment marks 510 of the first carrier substrate 508 are disposed between the integrated circuit devices 50. In fig. 7B, a first layer of dummy devices 300 is disposed over a first carrier substrate 508 located between the integrated circuit devices 50. The alignment marks 310 of the first tier dummy devices 300 are aligned with a first subset 510A of the alignment marks 510. In fig. 7C, a second level of integrated circuit devices 50 and dummy devices 300 is placed on the first level. The alignment marks 310 of the second tier dummy device 300 are aligned with a second subset 510B of the alignment marks 510. The material of the dummy device 300 is transparent to the light used for alignment of the alignment marks 310. Further, the first and second sub-groups 510A, 510B of the alignment marks 510 may have different shapes (see, e.g., fig. 4A to 4D). For example, the first tier dummy devices 300 may be aligned with underlying alignment marks 510 having a first shape, and the second tier dummy devices 300 may be aligned with underlying alignment marks 510 having a second shape. Furthermore, some dummy devices 300 may have a plurality of laterally offset alignment marks 310 (see fig. 7C) to ensure that the dummy devices 300 are properly rotated during alignment. In addition, the alignment marks 310 of the dummy devices 300 in different layers do not overlap in a plan view or a top view.
Fig. 8A-8C are plan views of one layer of a first device package 500 (see, e.g., fig. 5A-5I) according to some embodiments. The layout of the dummy device 300 is shown with respect to the integrated circuit device 50. The dummy device 300 may be arranged in a variety of ways and may have a variety of shapes. In some embodiments (e.g., fig. 8A), dummy devices 300 are disposed along two edges of integrated circuit device 50. In some embodiments (e.g., fig. 8B), the dummy devices 300 are arranged along four edges of the integrated circuit device 50. In some embodiments (e.g., fig. 8C), a single dummy device 300 surrounds the integrated circuit device 50. Other dummy device layouts are also possible.
Fig. 9A-9H are various cross-sectional views of intermediate steps during a process of forming a device package, according to some embodiments. In fig. 9A to 9H, a device stack 902 is formed by stacking a plurality of dummy devices and first integrated circuit devices on a second integrated circuit device. The first integrated circuit device may have a similar structure to integrated circuit device 50 (see fig. 1) and may be a memory die in an embodiment. The second integrated circuit device may have a similar structure as integrated circuit device 50 (see fig. 1), and in an embodiment, the second integrated circuit device may be a logic die. The dummy device may have a similar structure to the dummy device 300 (see fig. 3). The device stack 902 is tested after being formed.
In fig. 9A, a first integrated circuit device 904 is attached to a first carrier substrate 906. The first carrier substrate 906 may be formed of a silicon wafer or the like, and alignment marks 908 are formed in or above the silicon wafer. The alignment marks 908 may be formed in a similar manner as the alignment marks 310 of the dummy device 300 (see fig. 3). The first integrated circuit device 904 may be placed on a first carrier substrate 906 and attached with a dielectric layer 60 of the first integrated circuit device 904 by a bond, such as an oxide-to-oxide bond. The first integrated circuit device 904 may be tested prior to attachment so that only good dies are known for processing.
In fig. 9B, a first encapsulant 912 is formed around the first integrated circuit device 904. The first sealant 912 may be formed of a material selected from candidate materials of the topmost sealant 110A (see fig. 2B), or may include a different material. The first sealant 912 may be formed by a method selected from candidate methods of forming the topmost sealant 110A, or may be formed by a different method. The first encapsulant 912 and the first integrated circuit device 904 are thinned, for example by CMP, to expose the conductive vias 54 of the first integrated circuit device 904.
In fig. 9C, a device stack 902 is formed on a first integrated circuit device 904. The device stack 902 includes multiple layers of integrated circuit devices 50A-50D, dummy devices 300A-300D, and encapsulants 918A-918D. The bottommost layers of the integrated circuit device 50D and the dummy device 300D may not be planarized such that the conductive vias 54 of the integrated circuit device 50D remain insulated. Each layer may be attached using, for example, a bond such as an oxide-to-oxide bond. During placement, the alignment marks 310 of the dummy devices 300A-300D are aligned with the alignment marks 908 of the first carrier substrate 906.
In fig. 9D, a second carrier substrate 920 is attached to the device stack 902 by bonding, such as oxide-to-oxide bonding, using a dielectric layer 922, forming a first device package 900. The second carrier substrate 920 may be formed of a material selected from candidate materials for the second carrier substrate 112, or may include a different material. The second carrier substrate 920 includes alignment marks 924, the alignment marks 924 being aligned with the alignment marks 310 of the integrated circuit devices 50A-50D during placement.
In fig. 9E, the first carrier substrate 906 is removed from the first integrated circuit device 904. In embodiments where the first carrier substrate 906 is a silicon wafer, the removal may be accomplished by etching or grinding away the silicon wafer and the dielectric layer.
In fig. 9F, an opening is formed in the dielectric layer 60 of the first integrated circuit device 904 and a bump 926 is formed in the opening. Bump 926 may be formed of a material selected from the candidate materials for bump 126 (see fig. 2K), or may include a different material. The bump 926 may be formed by a method selected from candidate methods of forming the bump 126, or may be formed by a different method.
A conductive connection 928 is then formed over the bump 926. The conductive connector 928 may be formed of a material selected from candidate materials for the conductive connector 128, or may include a different material. The conductive connection 928 may be formed by a method selected from candidate methods of forming the conductive connection 128, or may be formed by a different method. The first device package 900 may then be probe tested using the conductive connections 928 so that only known good devices are used for further processing.
In fig. 9G, the first device package 900 is singulated from adjacent device packages. Singulation may be performed along scribe lines 930 by, for example, sawing or laser cutting. Alignment marks 924 of the second carrier substrate 920 may be disposed along scribe lines 930. As such, the singulation process may result in cutting or removing some of the alignment marks 924 such that the portion of the second carrier substrate 920 in the first device package 900 has a fragment or portion of the alignment marks 924.
In fig. 9H, a second device package 950 is formed by mounting the first device package 900 to a package substrate 952. The package substrate 952 may be similar to the package substrate 152 (see fig. 2L). The package substrate 952 may include metallization layers and vias (not shown) and bond pads 954 located over the metallization layers and vias. The conductive connectors 928 of the first device package 900 are connected to the bond pads 954 of the package substrate 952 to form a second device package 950.
